From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>,
xen-devel <xen-devel@lists.xenproject.org>
Cc: Brian Woods <brian.woods@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: [Xen-devel] [PATCH 2/9] AMD/IOMMU: use bit field for control register
Date: Tue, 18 Jun 2019 10:54:20 +0100 [thread overview]
Message-ID: <246c43d3-6725-597b-eb1d-32c42ff68c9e@citrix.com> (raw)
In-Reply-To: <5D024E2B0200007800237E00@prv1-mh.provo.novell.com>
On 13/06/2019 14:22, Jan Beulich wrote:
> Also introduce a field in struct amd_iommu caching the most recently
> written control register. All writes should now happen exclusively from
> that cached value, such that it is guaranteed to be up to date.
>
> Take the opportunity and add further fields. Also convert a few boolean
> function parameters to bool, such that use of !! can be avoided.
Critically also, some previous writel()'s have turned into writeq(),
which needs calling out.
> --- a/xen/drivers/passthrough/amd/iommu_init.c
> +++ b/xen/drivers/passthrough/amd/iommu_init.c
> @@ -69,31 +69,18 @@ static void __init unmap_iommu_mmio_regi
>
> static void set_iommu_ht_flags(struct amd_iommu *iommu)
> {
> - u32 entry;
> - entry = readl(iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
> -
> /* Setup HT flags */
> if ( iommu_has_cap(iommu, PCI_CAP_HT_TUNNEL_SHIFT) )
> - iommu_has_ht_flag(iommu, ACPI_IVHD_TT_ENABLE) ?
> - iommu_set_bit(&entry, IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT) :
> - iommu_clear_bit(&entry, IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT);
> -
> - iommu_has_ht_flag(iommu, ACPI_IVHD_RES_PASS_PW) ?
> - iommu_set_bit(&entry, IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_SHIFT):
> - iommu_clear_bit(&entry, IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_SHIFT);
> -
> - iommu_has_ht_flag(iommu, ACPI_IVHD_ISOC) ?
> - iommu_set_bit(&entry, IOMMU_CONTROL_ISOCHRONOUS_SHIFT):
> - iommu_clear_bit(&entry, IOMMU_CONTROL_ISOCHRONOUS_SHIFT);
> -
> - iommu_has_ht_flag(iommu, ACPI_IVHD_PASS_PW) ?
> - iommu_set_bit(&entry, IOMMU_CONTROL_PASS_POSTED_WRITE_SHIFT):
> - iommu_clear_bit(&entry, IOMMU_CONTROL_PASS_POSTED_WRITE_SHIFT);
> + iommu->ctrl.ht_tun_en = iommu_has_ht_flag(iommu, ACPI_IVHD_TT_ENABLE);
> +
> + iommu->ctrl.pass_pw = iommu_has_ht_flag(iommu, ACPI_IVHD_PASS_PW);
> + iommu->ctrl.res_pass_pw = iommu_has_ht_flag(iommu, ACPI_IVHD_RES_PASS_PW);
> + iommu->ctrl.isoc = iommu_has_ht_flag(iommu, ACPI_IVHD_ISOC);
>
> /* Force coherent */
> - iommu_set_bit(&entry, IOMMU_CONTROL_COHERENT_SHIFT);
> + iommu->ctrl.coherent = 1;
Ah - so this is the AMD version of Intel's iommu=snoop
> --- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
> +++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
> @@ -295,38 +295,55 @@ struct amd_iommu_dte {
>
> +union amd_iommu_control {
> + uint64_t raw;
> + struct {
> + unsigned int iommu_en:1;
> + unsigned int ht_tun_en:1;
> + unsigned int event_log_en:1;
> + unsigned int event_int_en:1;
> + unsigned int com_wait_int_en:1;
> + unsigned int inv_timeout:3;
> + unsigned int pass_pw:1;
> + unsigned int res_pass_pw:1;
> + unsigned int coherent:1;
> + unsigned int isoc:1;
> + unsigned int cmd_buf_en:1;
> + unsigned int ppr_log_en:1;
> + unsigned int ppr_int_en:1;
> + unsigned int ppr_en:1;
> + unsigned int gt_en:1;
> + unsigned int ga_en:1;
> + unsigned int crw:4;
This field does have an assigned name, but is also documented as Res0
for forwards compatibility. I think this field wants handling
consistently with...
> + unsigned int smif_en:1;
> + unsigned int slf_wb_dis:1;
> + unsigned int smif_log_en:1;
> + unsigned int gam_en:3;
> + unsigned int ga_log_en:1;
> + unsigned int ga_int_en:1;
> + unsigned int dual_ppr_log_en:2;
> + unsigned int dual_event_log_en:2;
> + unsigned int dev_tbl_seg_en:3;
> + unsigned int priv_abrt_en:2;
> + unsigned int ppr_auto_rsp_en:1;
> + unsigned int marc_en:1;
> + unsigned int blk_stop_mrk_en:1;
> + unsigned int ppr_auto_rsp_aon:1;
> + unsigned int :2;
... this, where you have dropped the DomainIDPNE bit (whatever the PN
stands for).
~Andrew
> + unsigned int eph_en:1;
> + unsigned int had_update:2;
> + unsigned int gd_update_dis:1;
> + unsigned int :1;
> + unsigned int xt_en:1;
> + unsigned int int_cap_xt_en:1;
> + unsigned int vcmd_en:1;
> + unsigned int viommu_en:1;
> + unsigned int ga_update_dis:1;
> + unsigned int gappi_en:1;
> + unsigned int :8;
> + };
> +};
>
> /* Exclusion Register */
> #define IOMMU_EXCLUSION_BASE_LOW_OFFSET 0x20
>
>
>
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next prev parent reply other threads:[~2019-06-18 9:55 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-13 13:14 [Xen-devel] [PATCH 0/9] x86: AMD x2APIC support Jan Beulich
2019-06-13 13:22 ` [Xen-devel] [PATCH 1/9] AMD/IOMMU: use bit field for extended feature register Jan Beulich
2019-06-17 19:07 ` Woods, Brian
2019-06-18 9:37 ` Jan Beulich
2019-06-17 20:23 ` Andrew Cooper
2019-06-18 9:33 ` Jan Beulich
2019-06-13 13:22 ` [Xen-devel] [PATCH 2/9] AMD/IOMMU: use bit field for control register Jan Beulich
2019-06-18 9:54 ` Andrew Cooper [this message]
2019-06-18 10:45 ` Jan Beulich
2019-06-13 13:23 ` [Xen-devel] [PATCH 3/9] AMD/IOMMU: use bit field for IRTE Jan Beulich
2019-06-18 10:37 ` Andrew Cooper
2019-06-18 11:53 ` Jan Beulich
2019-06-18 12:16 ` Andrew Cooper
2019-06-18 12:55 ` Jan Beulich
2019-06-18 11:31 ` Andrew Cooper
2019-06-18 11:47 ` Jan Beulich
2019-06-13 13:23 ` [Xen-devel] [PATCH 4/9] AMD/IOMMU: introduce 128-bit IRTE non-guest-APIC IRTE format Jan Beulich
2019-06-18 11:57 ` Andrew Cooper
2019-06-18 15:31 ` Jan Beulich
2019-06-13 13:24 ` [Xen-devel] [PATCH 5/9] AMD/IOMMU: split amd_iommu_init_one() Jan Beulich
2019-06-18 12:17 ` Andrew Cooper
2019-06-13 13:25 ` [Xen-devel] [PATCH 6/9] AMD/IOMMU: allow enabling with IRQ not yet set up Jan Beulich
2019-06-18 12:22 ` Andrew Cooper
2019-06-13 13:26 ` [Xen-devel] [PATCH 7/9] AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode Jan Beulich
2019-06-18 12:35 ` Andrew Cooper
2019-06-13 13:27 ` [Xen-devel] [PATCH 8/9] AMD/IOMMU: enable x2APIC mode when available Jan Beulich
2019-06-18 13:40 ` Andrew Cooper
2019-06-18 14:02 ` Jan Beulich
2019-06-13 13:28 ` [Xen-devel] [PATCH RFC 9/9] AMD/IOMMU: correct IRTE updating Jan Beulich
2019-06-18 13:28 ` Andrew Cooper
2019-06-18 14:58 ` Jan Beulich
2019-06-27 15:15 ` [Xen-devel] [PATCH v2 00/10] x86: AMD x2APIC support Jan Beulich
2019-06-27 15:19 ` [Xen-devel] [PATCH v2 01/10] AMD/IOMMU: restrict feature logging Jan Beulich
2019-07-01 15:37 ` Andrew Cooper
2019-07-01 15:59 ` Woods, Brian
2019-06-27 15:19 ` [Xen-devel] [PATCH v2 02/10] AMD/IOMMU: use bit field for extended feature register Jan Beulich
2019-07-02 12:09 ` Andrew Cooper
2019-07-02 13:48 ` Jan Beulich
2019-07-16 16:02 ` Jan Beulich
2019-06-27 15:20 ` [Xen-devel] [PATCH v2 03/10] AMD/IOMMU: use bit field for control register Jan Beulich
2019-07-02 12:20 ` Andrew Cooper
2019-06-27 15:20 ` [Xen-devel] [PATCH v2 04/10] AMD/IOMMU: use bit field for IRTE Jan Beulich
2019-07-02 12:33 ` Andrew Cooper
2019-07-02 13:56 ` Jan Beulich
2019-06-27 15:21 ` [Xen-devel] [PATCH v2 05/10] AMD/IOMMU: introduce 128-bit IRTE non-guest-APIC IRTE format Jan Beulich
2019-07-02 14:41 ` Andrew Cooper
2019-07-03 8:46 ` Jan Beulich
2019-07-16 6:39 ` Jan Beulich
2019-06-27 15:21 ` [Xen-devel] [PATCH v2 06/10] AMD/IOMMU: split amd_iommu_init_one() Jan Beulich
2019-06-27 15:22 ` [Xen-devel] [PATCH v2 07/10] AMD/IOMMU: allow enabling with IRQ not yet set up Jan Beulich
2019-06-27 15:22 ` [Xen-devel] [PATCH v2 08/10] AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode Jan Beulich
2019-06-27 15:23 ` [Xen-devel] [PATCH v2 09/10] AMD/IOMMU: enable x2APIC mode when available Jan Beulich
2019-07-02 14:50 ` Andrew Cooper
2019-06-27 15:23 ` [Xen-devel] [PATCH RFC v2 10/10] AMD/IOMMU: correct IRTE updating Jan Beulich
2019-07-02 15:08 ` Andrew Cooper
2019-07-03 8:55 ` Jan Beulich
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