From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Xen-devel <xen-devel@lists.xenproject.org>,
"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [PATCH] x86/traps: Rework #PF[Rsvd] bit handling
Date: Tue, 19 May 2020 16:48:55 +0200 [thread overview]
Message-ID: <3088e420-a72a-1b2d-144f-115610488418@suse.com> (raw)
In-Reply-To: <62d4999b-7db3-bac6-28ed-bb636347df38@citrix.com>
On 19.05.2020 16:11, Andrew Cooper wrote:
> On 19/05/2020 09:34, Jan Beulich wrote:
>> On 18.05.2020 17:38, Andrew Cooper wrote:
>>> @@ -1439,6 +1418,18 @@ void do_page_fault(struct cpu_user_regs *regs)
>>> if ( unlikely(fixup_page_fault(addr, regs) != 0) )
>>> return;
>>>
>>> + /*
>>> + * Xen have reserved bits in its pagetables, nor do we permit PV guests to
>>> + * write any. Such entries would be vulnerable to the L1TF sidechannel.
>>> + *
>>> + * The only logic which intentionally sets reserved bits is the shadow
>>> + * MMIO fastpath (SH_L1E_MMIO_*), which is careful not to be
>>> + * L1TF-vulnerable, and handled via the VMExit #PF intercept path, rather
>>> + * than here.
>> What about SH_L1E_MAGIC and sh_l1e_gnp()? The latter gets used by
>> _sh_propagate() without visible restriction to HVM.
>
> SH_L1E_MAGIC looks to be redundant with SH_L1E_MMIO_MAGIC.
> sh_l1e_mmio() is the only path which ever creates an entry like that.
>
> sh_l1e_gnp() is a very well hidden use of reserved bits, but surely
> can't be used for PV guests, as there doesn't appear to be anything to
> turn the resulting fault back into a plain not-present.
Well, in this case the implied question remains: How does this fit
with what _sh_propagate() does?
>> And of course every time I look at this code I wonder how we can
>> get away with (quoting a comment) "We store 28 bits of GFN in
>> bits 4:32 of the entry." Do we have a hidden restriction
>> somewhere guaranteeing that guests won't have (emulated MMIO)
>> GFNs above 1Tb when run in shadow mode?
>
> I've raised that several times before. Its broken.
>
> Given that shadow frames are limited to 44 bits anyway (and not yet
> levelled safely in the migration stream), my suggestion for fixing this
> was just to use one extra nibble for the extra 4 bits and call it done.
Would you remind(?) me of where this 44-bit restriction is coming
from?
Jan
next prev parent reply other threads:[~2020-05-19 14:49 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-18 15:38 [PATCH] x86/traps: Rework #PF[Rsvd] bit handling Andrew Cooper
2020-05-18 15:40 ` Andrew Cooper
2020-05-19 8:14 ` Jan Beulich
2020-05-19 14:29 ` Andrew Cooper
2020-05-19 14:55 ` Jan Beulich
2020-05-19 15:59 ` Andrew Cooper
2020-05-19 8:34 ` Jan Beulich
2020-05-19 14:11 ` Andrew Cooper
2020-05-19 14:48 ` Jan Beulich [this message]
2020-05-19 15:33 ` Andrew Cooper
2020-05-19 16:09 ` Jan Beulich
2020-05-19 18:00 ` Andrew Cooper
2020-05-20 7:48 ` Jan Beulich
2020-05-20 15:48 ` Andrew Cooper
2020-05-20 7:10 ` Tim Deegan
2020-05-21 15:43 ` [PATCH v2] " Andrew Cooper
2020-05-22 13:51 ` Jan Beulich
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