* [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
@ 2019-08-16 6:28 tony.nguyen
2019-08-16 7:08 ` [Xen-devel] [Qemu-devel] [PATCH v7 01/42] configure: Define TARGET_ALIGNED_ONLY tony.nguyen
` (43 more replies)
0 siblings, 44 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 6:28 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
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dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.
It is an attempt of the instructions outlined by Richard Henderson to Mark
Cave-Ayland.
Tested with OpenBSD on sun4u. Solaris 10 is my actual goal, but unfortunately a
separate keyboard issue remains in the way.
On 01/11/17 19:15, Mark Cave-Ayland wrote:
>On 15/08/17 19:10, Richard Henderson wrote:
>
>> [CC Peter re MemTxAttrs below]
>>
>> On 08/15/2017 09:38 AM, Mark Cave-Ayland wrote:
>>> Working through an incorrect endian issue on qemu-system-sparc64, it has
>>> become apparent that at least one OS makes use of the IE (Invert Endian)
>>> bit in the SPARCv9 MMU TTE to map PCI memory space without the
>>> programmer having to manually endian-swap accesses.
>>>
>>> In other words, to quote the UltraSPARC specification: "if this bit is
>>> set, accesses to the associated page are processed with inverse
>>> endianness from what is specified by the instruction (big-for-little and
>>> little-for-big)".
A good explanation by Mark why the IE bit is required.
>>>
>>> Looking through various bits of code, I'm trying to get a feel for the
>>> best way to implement this in an efficient manner. From what I can see
>>> this could be solved using an additional MMU index, however I'm not
>>> overly familiar with the memory and softmmu subsystems.
>>
>> No, it can't be solved with an MMU index.
>>
>>> Can anyone point me in the right direction as to what would be the best
>>> way to implement this feature within QEMU?
>>
>> It's definitely tricky.
>>
>> We definitely need some TLB_FLAGS_MASK bit set so that we're forced through
>> the
>> memory slow path. There is no other way to bypass the endianness that we've
>> already encoded from the target instruction.
>>
>> Given the tlb_set_page_with_attrs interface, I would think that we need a new
>> bit in MemTxAttrs, so that the target/sparc tlb_fill (and subroutines) can
>> pass
>> along the TTE bit for the given page.
>>
>> We have an existing problem in softmmu_template.h,
>>
>> /* ??? Note that the io helpers always read data in the target
>> byte ordering. We should push the LE/BE request down into io. */
>> res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
>> res = TGT_BE(res);
>>
>> We do not want to add a third(!) byte swap along the i/o path. We need to
>> collapse the two that we have already before considering this one.
>>
>> This probably takes the form of:
>>
>> (1) Replacing the "int size" argument with "TCGMemOp memop" for
>> a) io_{read,write}x in accel/tcg/cputlb.c,
>> b) memory_region_dispatch_{read,write} in memory.c,
>> c) adjust_endianness in memory.c.
>> This carries size+sign+endianness down to the next level.
>>
>> (2) In memory.c, adjust_endianness,
>>
>> if (memory_region_wrong_endianness(mr)) {
>> - switch (size) {
>> + memop ^= MO_BSWAP;
>> + }
>> + if (memop & MO_BSWAP) {
>>
>> For extra credit, re-arrange memory_region_wrong_endianness
>> to something more explicit -- "wrong" isn't helpful.
>
>Finally I've had a bit of spare time to experiment with this approach,
>and from what I can see there are currently 2 issues:
>
>
>1) Using TCGMemOp in memory.c means it is no longer accelerator agnostic
>
>For the moment I've defined a separate MemOp in memory.h and provided a
>mapping function in io_{read,write}x to map from TCGMemOp to MemOp and
>then pass that into memory_region_dispatch_{read,write}.
>
>Other than not referencing TCGMemOp in the memory API, another reason
>for doing this was that I wasn't convinced that all the MO_ attributes
>were valid outside of TCG. I do, of course, strongly defer to other
>people's knowledge in this area though.
>
>
>2) The above changes to adjust_endianness() fail when
>memory_region_dispatch_{read,write} are called recursively
>
>Whilst booting qemu-system-sparc64 I see that
>memory_region_dispatch_{read,write} get called recursively - once via
>io_{read,write}x and then again via flatview_read_continue() in exec.c.
>
>The net effect of this is that we perform the bswap correctly at the
>tail of the recursion, but then as we travel back up the stack we hit
>memory_region_dispatch_{read,write} once again causing a second bswap
>which means the value is returned with the incorrect endian again.
>
>
>My understanding from your softmmu_template.h comment above is that the
>memory API should do the endian swapping internally allowing the removal
>of the final TGT_BE/TGT_LE applied to the result, or did I get this wrong?
>
>> (3) In tlb_set_page_with_attrs, notice attrs.byte_swap and set
>> a new TLB_FORCE_SLOW bit within TLB_FLAGS_MASK.
>>
>> (4) In io_{read,write}x, if iotlbentry->attrs.byte_swap is set,
>> then memop ^= MO_BSWAP.
Thanks all for the feedback. Learnt a lot =)
v2:
- Moved size+sign+endianness attributes from TCGMemOp into MemOp.
In v1 TCGMemOp was re-purposed entirely into MemOp.
- Replaced MemOp MO_{8|16|32|64} with TCGMemOp MO_{UB|UW|UL|UQ} alias.
This is to avoid warnings on comparing and coercing different enums.
- Renamed get_memop to get_tcgmemop for clarity.
- MEMOP is now SIZE_MEMOP, which is just ctzl(size).
- Split patch 3/4 so one memory_region_dispatch_{read|write} interface
is converted per patch.
- Do not reuse TLB_RECHECK, use new TLB_FORCE_SLOW instead.
- Split patch 4/4 so adding the MemTxAddrs parameters and converting
tlb_set_page() to tlb_set_page_with_attrs() is separate from usage.
- CC'd maintainers.
v3:
- Like v1, the entire TCGMemOp enum is now MemOp.
- MemOp target dependant attributes are conditional upon NEED_CPU_H
v4:
- Added Paolo Bonzini as include/exec/memop.h maintainer
v5:
- Improved commit messages to clarify how interface to access
MemoryRegion will be converted from "unsigned size" to "MemOp op".
- Moved cpu_transaction_failed() MemOp conversion from patch #11 to #9
to make review easier.
v6:
- Improved commit messages.
- Include as patch #1 an earlier posted TARGET_ALIGNED_ONLY configure patch.
- Typeless macro SIZE_MEMOP is now inline.
- size_memop now includes CONFIG_DEBUG_TCG code.
- size_memop now also encodes endianness via MO_TE.
- Reverted size_memop operand "unsigned long" back to "unsigned".
- Second pass of size_memop to replace no-op place holder with MO_{8|16|32|64}.
- Delay memory_region_dispatch_{read,write} operand conversion until no-op
size_memop is implemented so we have proper typing at all points in between.
- Fixed bug where not all memory_region_dispatch_{read,write} callers where
encoding endianness into the MemOp operand, see patch #20.
- Fixed bug where not all memory_region_dispatch_{read,write} callers were
collapsing their byte swap into adjust_endianness, see patch #20 and #22.
- Split byte swap collapsing patch (v5 #11) into #21 and #22.
- Corrected non-common *-common-obj to *-obj.
- Replaced enum device_endian with MemOp to simplify endianness checks. A
straight forward sed but touched *alot* of files. See patch #16 and #17.
- Deleted enum device_endian.
- Deleted DEVICE_HOST_ENDIAN definition.
- Generalized the description of introduced MemTxAttrs attribute byte_swap.
v7:
- Fixed bug where size_memop was implicitly encoding MO_TE. Endianness,
{MO_TE|MO_BE|MO_LE}, is now explicitly encoded by MemoryRegion accessors.
- While a no-op, size_memop return type remains an unsigned.
- Use '= 0' short hand instead of macro logic to declare host endianness.
- With a new set of constant arguments, sanity checked the compiler is still
folding away tests in cputlb.c
- Re-declared many native endian devices as little or big endian. This is why
v7 has +16 patches.
Tony Nguyen (42):
configure: Define TARGET_ALIGNED_ONLY in configure
tcg: TCGMemOp is now accelerator independent MemOp
memory: Introduce size_memop
target/mips: Access MemoryRegion with MemOp
hw/s390x: Access MemoryRegion with MemOp
hw/intc/armv7m_nic: Access MemoryRegion with MemOp
hw/virtio: Access MemoryRegion with MemOp
hw/vfio: Access MemoryRegion with MemOp
exec: Access MemoryRegion with MemOp
cputlb: Access MemoryRegion with MemOp
memory: Access MemoryRegion with MemOp
hw/s390x: Hard code size with MO_{8|16|32|64}
target/mips: Hard code size with MO_{8|16|32|64}
exec: Hard code size with MO_{8|16|32|64}
hw/audio: Declare device little or big endian
hw/block: Declare device little or big endian
hw/char: Declare device little or big endian
hw/display: Declare device little or big endian
hw/dma: Declare device little or big endian
hw/gpio: Declare device little or big endian
hw/i2c: Declare device little or big endian
hw/input: Declare device little or big endian
hw/intc: Declare device little or big endian
hw/isa: Declare device little or big endian
hw/misc: Declare device little or big endian
hw/net: Declare device little or big endian
hw/pci-host: Declare device little or big endian
hw/sd: Declare device little or big endian
hw/ssi: Declare device little or big endian
hw/timer: Declare device little or big endian
build: Correct non-common common-obj-* to obj-*
exec: Map device_endian onto MemOp
exec: Replace device_endian with MemOp
exec: Delete device_endian
exec: Delete DEVICE_HOST_ENDIAN
memory: Access MemoryRegion with endianness
cputlb: Replace size and endian operands for MemOp
memory: Single byte swap along the I/O path
cpu: TLB_FLAGS_MASK bit to force memory slow path
cputlb: Byte swap memory transaction attribute
target/sparc: Add TLB entry with attributes
target/sparc: sun4u Invert Endian TTE bit
MAINTAINERS | 1 +
accel/tcg/cputlb.c | 197 ++++++++++++++------------------
configure | 10 +-
exec.c | 15 ++-
hw/acpi/core.c | 6 +-
hw/acpi/cpu.c | 2 +-
hw/acpi/cpu_hotplug.c | 2 +-
hw/acpi/ich9.c | 4 +-
hw/acpi/memory_hotplug.c | 2 +-
hw/acpi/nvdimm.c | 2 +-
hw/acpi/pcihp.c | 2 +-
hw/acpi/piix4.c | 2 +-
hw/acpi/tco.c | 2 +-
hw/adc/stm32f2xx_adc.c | 2 +-
hw/alpha/pci.c | 6 +-
hw/alpha/typhoon.c | 6 +-
hw/arm/allwinner-a10.c | 2 +-
hw/arm/armv7m.c | 2 +-
hw/arm/aspeed.c | 2 +-
hw/arm/aspeed_soc.c | 2 +-
hw/arm/exynos4210.c | 2 +-
hw/arm/highbank.c | 2 +-
hw/arm/integratorcp.c | 6 +-
hw/arm/kzm.c | 2 +-
hw/arm/msf2-soc.c | 2 +-
hw/arm/musicpal.c | 20 ++--
hw/arm/omap1.c | 40 +++----
hw/arm/omap2.c | 10 +-
hw/arm/omap_sx1.c | 2 +-
hw/arm/palm.c | 2 +-
hw/arm/pxa2xx.c | 20 ++--
hw/arm/pxa2xx_gpio.c | 2 +-
hw/arm/pxa2xx_pic.c | 2 +-
hw/arm/smmuv3.c | 2 +-
hw/arm/spitz.c | 2 +-
hw/arm/stellaris.c | 8 +-
hw/arm/strongarm.c | 12 +-
hw/arm/versatilepb.c | 2 +-
hw/audio/Makefile.objs | 3 +-
hw/audio/ac97.c | 4 +-
hw/audio/cs4231.c | 2 +-
hw/audio/es1370.c | 2 +-
hw/audio/intel-hda.c | 2 +-
hw/audio/marvell_88w8618.c | 2 +-
hw/audio/milkymist-ac97.c | 2 +-
hw/audio/pl041.c | 2 +-
hw/block/Makefile.objs | 6 +-
hw/block/fdc.c | 4 +-
hw/block/nvme.c | 4 +-
hw/block/onenand.c | 2 +-
hw/block/pflash_cfi01.c | 2 +-
hw/block/pflash_cfi02.c | 2 +-
hw/char/Makefile.objs | 4 +-
hw/char/bcm2835_aux.c | 2 +-
hw/char/cadence_uart.c | 2 +-
hw/char/cmsdk-apb-uart.c | 2 +-
hw/char/debugcon.c | 2 +-
hw/char/digic-uart.c | 2 +-
hw/char/escc.c | 2 +-
hw/char/etraxfs_ser.c | 2 +-
hw/char/exynos4210_uart.c | 2 +-
hw/char/grlib_apbuart.c | 2 +-
hw/char/imx_serial.c | 2 +-
hw/char/lm32_uart.c | 2 +-
hw/char/mcf_uart.c | 2 +-
hw/char/milkymist-uart.c | 2 +-
hw/char/nrf51_uart.c | 2 +-
hw/char/omap_uart.c | 6 +-
hw/char/parallel.c | 2 +-
hw/char/pl011.c | 2 +-
hw/char/serial.c | 26 ++---
hw/char/sh_serial.c | 2 +-
hw/char/stm32f2xx_usart.c | 2 +-
hw/char/xilinx_uartlite.c | 2 +-
hw/core/Makefile.objs | 2 +-
hw/core/empty_slot.c | 2 +-
hw/cris/axis_dev88.c | 4 +-
hw/display/Makefile.objs | 6 +-
hw/display/ati.c | 2 +-
hw/display/bcm2835_fb.c | 2 +-
hw/display/bochs-display.c | 4 +-
hw/display/cg3.c | 2 +-
hw/display/cirrus_vga.c | 10 +-
hw/display/edid-region.c | 2 +-
hw/display/exynos4210_fimd.c | 2 +-
hw/display/g364fb.c | 2 +-
hw/display/jazz_led.c | 2 +-
hw/display/milkymist-tmu2.c | 2 +-
hw/display/milkymist-vgafb.c | 2 +-
hw/display/omap_dss.c | 10 +-
hw/display/omap_lcdc.c | 2 +-
hw/display/pl110.c | 2 +-
hw/display/pxa2xx_lcd.c | 2 +-
hw/display/sm501.c | 10 +-
hw/display/tc6393xb.c | 2 +-
hw/display/tcx.c | 14 +--
hw/display/vga-isa-mm.c | 2 +-
hw/display/vga-pci.c | 6 +-
hw/display/vga.c | 2 +-
hw/display/vmware_vga.c | 2 +-
hw/display/xlnx_dp.c | 8 +-
hw/dma/Makefile.objs | 6 +-
hw/dma/bcm2835_dma.c | 4 +-
hw/dma/etraxfs_dma.c | 2 +-
hw/dma/i8257.c | 4 +-
hw/dma/omap_dma.c | 4 +-
hw/dma/pl080.c | 2 +-
hw/dma/pl330.c | 2 +-
hw/dma/puv3_dma.c | 2 +-
hw/dma/pxa2xx_dma.c | 2 +-
hw/dma/rc4030.c | 4 +-
hw/dma/sparc32_dma.c | 2 +-
hw/dma/xilinx_axidma.c | 2 +-
hw/dma/xlnx-zdma.c | 2 +-
hw/dma/xlnx-zynq-devcfg.c | 2 +-
hw/dma/xlnx_dpdma.c | 2 +-
hw/gpio/Makefile.objs | 2 +-
hw/gpio/bcm2835_gpio.c | 2 +-
hw/gpio/imx_gpio.c | 2 +-
hw/gpio/mpc8xxx.c | 2 +-
hw/gpio/nrf51_gpio.c | 2 +-
hw/gpio/omap_gpio.c | 6 +-
hw/gpio/pl061.c | 2 +-
hw/gpio/puv3_gpio.c | 2 +-
hw/gpio/zaurus.c | 2 +-
hw/hppa/dino.c | 6 +-
hw/hppa/machine.c | 2 +-
hw/hppa/pci.c | 6 +-
hw/hyperv/hyperv_testdev.c | 2 +-
hw/i2c/Makefile.objs | 2 +-
hw/i2c/aspeed_i2c.c | 4 +-
hw/i2c/exynos4210_i2c.c | 2 +-
hw/i2c/imx_i2c.c | 2 +-
hw/i2c/microbit_i2c.c | 2 +-
hw/i2c/mpc_i2c.c | 2 +-
hw/i2c/omap_i2c.c | 2 +-
hw/i2c/pm_smbus.c | 2 +-
hw/i2c/ppc4xx_i2c.c | 2 +-
hw/i2c/versatile_i2c.c | 2 +-
hw/i386/amd_iommu.c | 4 +-
hw/i386/intel_iommu.c | 4 +-
hw/i386/kvm/apic.c | 2 +-
hw/i386/kvmvapic.c | 2 +-
hw/i386/pc.c | 6 +-
hw/i386/vmport.c | 2 +-
hw/i386/xen/xen_apic.c | 2 +-
hw/i386/xen/xen_platform.c | 4 +-
hw/i386/xen/xen_pvdevice.c | 2 +-
hw/ide/ahci-allwinner.c | 2 +-
hw/ide/ahci.c | 4 +-
hw/ide/macio.c | 2 +-
hw/ide/mmio.c | 4 +-
hw/ide/pci.c | 6 +-
hw/ide/sii3112.c | 2 +-
hw/input/Makefile.objs | 2 +-
hw/input/milkymist-softusb.c | 2 +-
hw/input/pckbd.c | 6 +-
hw/input/pl050.c | 2 +-
hw/input/pxa2xx_keypad.c | 2 +-
hw/intc/Makefile.objs | 6 +-
hw/intc/allwinner-a10-pic.c | 2 +-
hw/intc/apic.c | 2 +-
hw/intc/arm_gic.c | 12 +-
hw/intc/arm_gicv2m.c | 2 +-
hw/intc/arm_gicv3.c | 4 +-
hw/intc/arm_gicv3_its_common.c | 2 +-
hw/intc/armv7m_nvic.c | 19 +--
hw/intc/aspeed_vic.c | 2 +-
hw/intc/bcm2835_ic.c | 2 +-
hw/intc/bcm2836_control.c | 2 +-
hw/intc/etraxfs_pic.c | 2 +-
hw/intc/exynos4210_combiner.c | 2 +-
hw/intc/grlib_irqmp.c | 2 +-
hw/intc/heathrow_pic.c | 2 +-
hw/intc/imx_avic.c | 2 +-
hw/intc/imx_gpcv2.c | 2 +-
hw/intc/ioapic.c | 2 +-
hw/intc/mips_gic.c | 2 +-
hw/intc/omap_intc.c | 4 +-
hw/intc/ompic.c | 2 +-
hw/intc/openpic.c | 20 ++--
hw/intc/openpic_kvm.c | 2 +-
hw/intc/pl190.c | 2 +-
hw/intc/pnv_xive.c | 14 +--
hw/intc/puv3_intc.c | 2 +-
hw/intc/sh_intc.c | 2 +-
hw/intc/slavio_intctl.c | 4 +-
hw/intc/xics_pnv.c | 2 +-
hw/intc/xilinx_intc.c | 2 +-
hw/intc/xive.c | 6 +-
hw/intc/xlnx-pmu-iomod-intc.c | 2 +-
hw/intc/xlnx-zynqmp-ipi.c | 2 +-
hw/ipack/Makefile.objs | 2 +-
hw/ipack/tpci200.c | 10 +-
hw/ipmi/isa_ipmi_bt.c | 2 +-
hw/ipmi/isa_ipmi_kcs.c | 2 +-
hw/isa/lpc_ich9.c | 4 +-
hw/isa/pc87312.c | 2 +-
hw/isa/vt82c686.c | 2 +-
hw/m68k/mcf5206.c | 2 +-
hw/m68k/mcf5208.c | 4 +-
hw/m68k/mcf_intc.c | 2 +-
hw/microblaze/petalogix_ml605_mmu.c | 2 +-
hw/mips/boston.c | 6 +-
hw/mips/gt64xxx_pci.c | 2 +-
hw/mips/mips_jazz.c | 8 +-
hw/mips/mips_malta.c | 4 +-
hw/mips/mips_r4k.c | 2 +-
hw/misc/Makefile.objs | 10 +-
hw/misc/a9scu.c | 2 +-
hw/misc/applesmc.c | 6 +-
hw/misc/arm11scu.c | 2 +-
hw/misc/arm_integrator_debug.c | 2 +-
hw/misc/arm_l2x0.c | 2 +-
hw/misc/arm_sysctl.c | 2 +-
hw/misc/armsse-cpuid.c | 2 +-
hw/misc/armsse-mhu.c | 2 +-
hw/misc/aspeed_scu.c | 2 +-
hw/misc/aspeed_sdmc.c | 2 +-
hw/misc/aspeed_xdma.c | 2 +-
hw/misc/bcm2835_mbox.c | 2 +-
hw/misc/bcm2835_property.c | 2 +-
hw/misc/bcm2835_rng.c | 2 +-
hw/misc/debugexit.c | 2 +-
hw/misc/eccmemctl.c | 4 +-
hw/misc/edu.c | 2 +-
hw/misc/exynos4210_clk.c | 2 +-
hw/misc/exynos4210_pmu.c | 2 +-
hw/misc/exynos4210_rng.c | 2 +-
hw/misc/grlib_ahb_apb_pnp.c | 4 +-
hw/misc/imx25_ccm.c | 2 +-
hw/misc/imx2_wdt.c | 2 +-
hw/misc/imx31_ccm.c | 2 +-
hw/misc/imx6_ccm.c | 4 +-
hw/misc/imx6_src.c | 2 +-
hw/misc/imx6ul_ccm.c | 4 +-
hw/misc/imx7_ccm.c | 4 +-
hw/misc/imx7_gpr.c | 2 +-
hw/misc/imx7_snvs.c | 2 +-
hw/misc/iotkit-secctl.c | 4 +-
hw/misc/iotkit-sysctl.c | 2 +-
hw/misc/iotkit-sysinfo.c | 2 +-
hw/misc/ivshmem.c | 2 +-
hw/misc/macio/cuda.c | 2 +-
hw/misc/macio/gpio.c | 2 +-
hw/misc/macio/mac_dbdma.c | 2 +-
hw/misc/macio/macio.c | 2 +-
hw/misc/macio/pmu.c | 2 +-
hw/misc/milkymist-hpdmc.c | 2 +-
hw/misc/milkymist-pfpu.c | 2 +-
hw/misc/mips_cmgcr.c | 2 +-
hw/misc/mips_cpc.c | 2 +-
hw/misc/mips_itu.c | 4 +-
hw/misc/mos6522.c | 2 +-
hw/misc/mps2-fpgaio.c | 2 +-
hw/misc/mps2-scc.c | 2 +-
hw/misc/msf2-sysreg.c | 2 +-
hw/misc/mst_fpga.c | 2 +-
hw/misc/nrf51_rng.c | 2 +-
hw/misc/omap_gpmc.c | 6 +-
hw/misc/omap_l4.c | 2 +-
hw/misc/omap_sdrc.c | 2 +-
hw/misc/omap_tap.c | 2 +-
hw/misc/pc-testdev.c | 10 +-
hw/misc/pci-testdev.c | 4 +-
hw/misc/puv3_pm.c | 2 +-
hw/misc/slavio_misc.c | 16 +--
hw/misc/stm32f2xx_syscfg.c | 2 +-
hw/misc/tz-mpc.c | 4 +-
hw/misc/tz-msc.c | 2 +-
hw/misc/tz-ppc.c | 2 +-
hw/misc/unimp.c | 2 +-
hw/misc/zynq-xadc.c | 2 +-
hw/misc/zynq_slcr.c | 2 +-
hw/moxie/moxiesim.c | 2 +-
hw/net/Makefile.objs | 2 +-
hw/net/allwinner_emac.c | 2 +-
hw/net/cadence_gem.c | 2 +-
hw/net/can/can_kvaser_pci.c | 6 +-
hw/net/can/can_mioe3680_pci.c | 4 +-
hw/net/can/can_pcm3680_pci.c | 4 +-
hw/net/dp8393x.c | 2 +-
hw/net/e1000.c | 4 +-
hw/net/e1000e.c | 4 +-
hw/net/eepro100.c | 2 +-
hw/net/etraxfs_eth.c | 2 +-
hw/net/fsl_etsec/etsec.c | 2 +-
hw/net/ftgmac100.c | 2 +-
hw/net/imx_fec.c | 2 +-
hw/net/lan9118.c | 4 +-
hw/net/lance.c | 2 +-
hw/net/mcf_fec.c | 2 +-
hw/net/milkymist-minimac2.c | 2 +-
hw/net/ne2000.c | 2 +-
hw/net/pcnet-pci.c | 4 +-
hw/net/rocker/rocker.c | 2 +-
hw/net/rtl8139.c | 2 +-
hw/net/smc91c111.c | 2 +-
hw/net/stellaris_enet.c | 2 +-
hw/net/sungem.c | 12 +-
hw/net/sunhme.c | 10 +-
hw/net/vmxnet3.c | 4 +-
hw/net/xgmac.c | 2 +-
hw/net/xilinx_axienet.c | 2 +-
hw/net/xilinx_ethlite.c | 2 +-
hw/nios2/10m50_devboard.c | 2 +-
hw/nvram/ds1225y.c | 2 +-
hw/nvram/fw_cfg.c | 8 +-
hw/nvram/mac_nvram.c | 2 +-
hw/nvram/nrf51_nvm.c | 8 +-
hw/openrisc/openrisc_sim.c | 2 +-
hw/pci-host/Makefile.objs | 2 +-
hw/pci-host/bonito.c | 10 +-
hw/pci-host/designware.c | 6 +-
hw/pci-host/piix.c | 2 +-
hw/pci-host/ppce500.c | 2 +-
hw/pci-host/prep.c | 4 +-
hw/pci-host/q35.c | 4 +-
hw/pci-host/sabre.c | 4 +-
hw/pci-host/uninorth.c | 4 +-
hw/pci-host/versatile.c | 4 +-
hw/pci/msix.c | 4 +-
hw/pci/pci_host.c | 8 +-
hw/pci/pcie_host.c | 2 +-
hw/pci/shpc.c | 2 +-
hw/pcmcia/pxa2xx.c | 6 +-
hw/ppc/e500.c | 4 +-
hw/ppc/mpc8544_guts.c | 2 +-
hw/ppc/pnv_core.c | 6 +-
hw/ppc/pnv_lpc.c | 8 +-
hw/ppc/pnv_occ.c | 4 +-
hw/ppc/pnv_psi.c | 8 +-
hw/ppc/pnv_xscom.c | 2 +-
hw/ppc/ppc405_boards.c | 4 +-
hw/ppc/ppc405_uc.c | 14 +--
hw/ppc/ppc440_bamboo.c | 4 +-
hw/ppc/ppc440_pcix.c | 4 +-
hw/ppc/ppc4xx_pci.c | 2 +-
hw/ppc/ppce500_spin.c | 2 +-
hw/ppc/sam460ex.c | 4 +-
hw/ppc/spapr_pci.c | 2 +-
hw/ppc/virtex_ml507.c | 2 +-
hw/rdma/vmw/pvrdma_main.c | 4 +-
hw/riscv/sifive_clint.c | 2 +-
hw/riscv/sifive_gpio.c | 2 +-
hw/riscv/sifive_plic.c | 2 +-
hw/riscv/sifive_prci.c | 2 +-
hw/riscv/sifive_test.c | 2 +-
hw/riscv/sifive_uart.c | 2 +-
hw/riscv/virt.c | 2 +-
hw/s390x/s390-pci-bus.c | 2 +-
hw/s390x/s390-pci-inst.c | 11 +-
hw/scsi/Makefile.objs | 2 +-
hw/scsi/esp-pci.c | 2 +-
hw/scsi/esp.c | 2 +-
hw/scsi/lsi53c895a.c | 6 +-
hw/scsi/megasas.c | 6 +-
hw/scsi/mptsas.c | 6 +-
hw/scsi/vmw_pvscsi.c | 2 +-
hw/sd/bcm2835_sdhost.c | 2 +-
hw/sd/milkymist-memcard.c | 2 +-
hw/sd/omap_mmc.c | 2 +-
hw/sd/pl181.c | 2 +-
hw/sd/pxa2xx_mmci.c | 2 +-
hw/sd/sdhci.c | 4 +-
hw/sh4/r2d.c | 2 +-
hw/sh4/sh7750.c | 4 +-
hw/sh4/sh_pci.c | 2 +-
hw/sparc/sun4m_iommu.c | 2 +-
hw/sparc64/niagara.c | 2 +-
hw/sparc64/sun4u.c | 4 +-
hw/sparc64/sun4u_iommu.c | 2 +-
hw/ssi/Makefile.objs | 2 +-
hw/ssi/aspeed_smc.c | 6 +-
hw/ssi/imx_spi.c | 2 +-
hw/ssi/mss-spi.c | 2 +-
hw/ssi/omap_spi.c | 2 +-
hw/ssi/pl022.c | 2 +-
hw/ssi/stm32f2xx_spi.c | 2 +-
hw/ssi/xilinx_spi.c | 2 +-
hw/ssi/xilinx_spips.c | 8 +-
hw/timer/Makefile.objs | 6 +-
hw/timer/a9gtimer.c | 4 +-
hw/timer/allwinner-a10-pit.c | 2 +-
hw/timer/altera_timer.c | 2 +-
hw/timer/arm_mptimer.c | 4 +-
hw/timer/arm_timer.c | 4 +-
hw/timer/armv7m_systick.c | 2 +-
hw/timer/aspeed_rtc.c | 2 +-
hw/timer/aspeed_timer.c | 2 +-
hw/timer/cadence_ttc.c | 2 +-
hw/timer/cmsdk-apb-dualtimer.c | 2 +-
hw/timer/cmsdk-apb-timer.c | 2 +-
hw/timer/digic-timer.c | 2 +-
hw/timer/etraxfs_timer.c | 2 +-
hw/timer/exynos4210_mct.c | 2 +-
hw/timer/exynos4210_pwm.c | 2 +-
hw/timer/exynos4210_rtc.c | 2 +-
hw/timer/grlib_gptimer.c | 2 +-
hw/timer/hpet.c | 2 +-
hw/timer/i8254.c | 2 +-
hw/timer/imx_epit.c | 2 +-
hw/timer/imx_gpt.c | 2 +-
hw/timer/lm32_timer.c | 2 +-
hw/timer/m48t59.c | 4 +-
hw/timer/mc146818rtc.c | 2 +-
hw/timer/milkymist-sysctl.c | 2 +-
hw/timer/mss-timer.c | 2 +-
hw/timer/nrf51_timer.c | 2 +-
hw/timer/omap_gptimer.c | 2 +-
hw/timer/omap_synctimer.c | 2 +-
hw/timer/pl031.c | 2 +-
hw/timer/puv3_ost.c | 2 +-
hw/timer/pxa2xx_timer.c | 2 +-
hw/timer/sh_timer.c | 2 +-
hw/timer/slavio_timer.c | 2 +-
hw/timer/stm32f2xx_timer.c | 2 +-
hw/timer/sun4v-rtc.c | 2 +-
hw/timer/xilinx_timer.c | 2 +-
hw/timer/xlnx-zynqmp-rtc.c | 2 +-
hw/tpm/tpm_crb.c | 2 +-
hw/tpm/tpm_tis.c | 2 +-
hw/usb/chipidea.c | 4 +-
hw/usb/hcd-ehci-sysbus.c | 2 +-
hw/usb/hcd-ehci.c | 6 +-
hw/usb/hcd-ohci.c | 2 +-
hw/usb/hcd-uhci.c | 2 +-
hw/usb/hcd-xhci.c | 10 +-
hw/usb/tusb6010.c | 2 +-
hw/vfio/common.c | 2 +-
hw/vfio/pci-quirks.c | 33 +++---
hw/vfio/pci.c | 4 +-
hw/virtio/Makefile.objs | 2 +-
hw/virtio/virtio-mmio.c | 2 +-
hw/virtio/virtio-pci.c | 27 +++--
hw/watchdog/cmsdk-apb-watchdog.c | 2 +-
hw/watchdog/wdt_aspeed.c | 2 +-
hw/watchdog/wdt_i6300esb.c | 2 +-
hw/xen/xen_pt.c | 2 +-
hw/xen/xen_pt_msi.c | 2 +-
hw/xtensa/mx_pic.c | 2 +-
hw/xtensa/xtfpga.c | 6 +-
include/exec/cpu-all.h | 10 +-
include/exec/cpu-common.h | 12 --
include/exec/memattrs.h | 2 +
include/exec/memop.h | 134 ++++++++++++++++++++++
include/exec/memory.h | 11 +-
include/exec/poison.h | 1 +
include/hw/char/serial.h | 2 +-
include/qom/cpu.h | 2 +-
ioport.c | 4 +-
memory.c | 55 ++++-----
memory_ldst.inc.c | 153 ++++++++-----------------
target/alpha/cpu.h | 2 -
target/alpha/translate.c | 2 +-
target/arm/translate-a64.c | 48 ++++----
target/arm/translate-a64.h | 2 +-
target/arm/translate-sve.c | 2 +-
target/arm/translate.c | 32 +++---
target/arm/translate.h | 2 +-
target/hppa/cpu.h | 1 -
target/hppa/translate.c | 14 +--
target/i386/translate.c | 132 ++++++++++-----------
target/m68k/translate.c | 2 +-
target/microblaze/translate.c | 4 +-
target/mips/cpu.h | 2 -
target/mips/op_helper.c | 5 +-
target/mips/translate.c | 8 +-
target/openrisc/translate.c | 4 +-
target/ppc/translate.c | 12 +-
target/riscv/insn_trans/trans_rva.inc.c | 8 +-
target/riscv/insn_trans/trans_rvi.inc.c | 4 +-
target/s390x/translate.c | 6 +-
target/s390x/translate_vx.inc.c | 10 +-
target/sh4/cpu.h | 2 -
target/sparc/cpu.h | 4 +-
target/sparc/mmu_helper.c | 40 ++++---
target/sparc/translate.c | 14 +--
target/tilegx/translate.c | 10 +-
target/tricore/translate.c | 8 +-
target/xtensa/cpu.h | 2 -
tcg/README | 2 +-
tcg/aarch64/tcg-target.inc.c | 26 ++---
tcg/arm/tcg-target.inc.c | 26 ++---
tcg/i386/tcg-target.inc.c | 24 ++--
tcg/mips/tcg-target.inc.c | 16 +--
tcg/optimize.c | 2 +-
tcg/ppc/tcg-target.inc.c | 12 +-
tcg/riscv/tcg-target.inc.c | 20 ++--
tcg/s390/tcg-target.inc.c | 14 +--
tcg/sparc/tcg-target.inc.c | 6 +-
tcg/tcg-op.c | 38 +++---
tcg/tcg-op.h | 86 +++++++-------
tcg/tcg.c | 4 +-
tcg/tcg.h | 99 +---------------
trace/mem-internal.h | 4 +-
trace/mem.h | 4 +-
497 files changed, 1436 insertions(+), 1473 deletions(-)
create mode 100644 include/exec/memop.h
--
1.8.3.1
_______________________________________________
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Xen-devel@lists.xenproject.org
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^ permalink raw reply [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 01/42] configure: Define TARGET_ALIGNED_ONLY
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
@ 2019-08-16 7:08 ` tony.nguyen
2019-08-16 7:26 ` [Xen-devel] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen
` (42 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:08 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 6445 bytes --]
Rename ALIGNED_ONLY to TARGET_ALIGNED_ONLY for clarity and move
defines out of target/foo/cpu.h into configure, as we do with
TARGET_WORDS_BIGENDIAN, so that it is always defined early.
Poisoned TARGET_ALIGNED_ONLY to prevent use in common code.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
---
configure | 10 +++++++++-
include/exec/poison.h | 1 +
include/qom/cpu.h | 2 +-
target/alpha/cpu.h | 2 --
target/hppa/cpu.h | 1 -
target/mips/cpu.h | 2 --
target/sh4/cpu.h | 2 --
target/sparc/cpu.h | 2 --
target/xtensa/cpu.h | 2 --
tcg/tcg.c | 2 +-
tcg/tcg.h | 8 +++++---
11 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/configure b/configure
index 714e7fb..482ba0b 100755
--- a/configure
+++ b/configure
@@ -7431,8 +7431,13 @@ for target in $target_list; do
target_dir="$target"
config_target_mak=$target_dir/config-target.mak
target_name=$(echo $target | cut -d '-' -f 1)
+target_aligned_only="no"
+case "$target_name" in
+ alpha|hppa|mips64el|mips64|mipsel|mips|mipsn32|mipsn32el|sh4|sh4eb|sparc|sparc64|sparc32plus|xtensa|xtensaeb)
+ target_aligned_only="yes"
+ ;;
+esac
target_bigendian="no"
-
case "$target_name" in
armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
target_bigendian=yes
@@ -7717,6 +7722,9 @@ fi
if supported_whpx_target $target; then
echo "CONFIG_WHPX=y" >> $config_target_mak
fi
+if test "$target_aligned_only" = "yes" ; then
+ echo "TARGET_ALIGNED_ONLY=y" >> $config_target_mak
+fi
if test "$target_bigendian" = "yes" ; then
echo "TARGET_WORDS_BIGENDIAN=y" >> $config_target_mak
fi
diff --git a/include/exec/poison.h b/include/exec/poison.h
index b862320..955eb86 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -35,6 +35,7 @@
#pragma GCC poison TARGET_UNICORE32
#pragma GCC poison TARGET_XTENSA
+#pragma GCC poison TARGET_ALIGNED_ONLY
#pragma GCC poison TARGET_HAS_BFLT
#pragma GCC poison TARGET_NAME
#pragma GCC poison TARGET_SUPPORTS_MTTCG
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 5ee0046..9b50b73 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -89,7 +89,7 @@ struct TranslationBlock;
* @do_unassigned_access: Callback for unassigned access handling.
* (this is deprecated: new targets should use do_transaction_failed instead)
* @do_unaligned_access: Callback for unaligned access handling, if
- * the target defines #ALIGNED_ONLY.
+ * the target defines #TARGET_ALIGNED_ONLY.
* @do_transaction_failed: Callback for handling failed memory transactions
* (ie bus faults or external aborts; not MMU faults)
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index b3e8a82..16eb804 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -23,8 +23,6 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-#define ALIGNED_ONLY
-
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index aab251b..2be67c2 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -30,7 +30,6 @@
basis. It's probably easier to fall back to a strong memory model. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-#define ALIGNED_ONLY
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
#define MMU_PHYS_IDX 4
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 21c0615..c13cd4e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1,8 +1,6 @@
#ifndef MIPS_CPU_H
#define MIPS_CPU_H
-#define ALIGNED_ONLY
-
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index aee733e..ecaa7a1 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -23,8 +23,6 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-#define ALIGNED_ONLY
-
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
#define SH_CPU_SH7750S (1 << 1)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 8ed2250..1406f0b 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -5,8 +5,6 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-#define ALIGNED_ONLY
-
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
#else
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 2c27713..0459243 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -32,8 +32,6 @@
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
-#define ALIGNED_ONLY
-
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index be2c33c..8d23fb0 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1926,7 +1926,7 @@ static const char * const ldst_name[] =
};
static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = {
-#ifdef ALIGNED_ONLY
+#ifdef TARGET_ALIGNED_ONLY
[MO_UNALN >> MO_ASHIFT] = "un+",
[MO_ALIGN >> MO_ASHIFT] = "",
#else
diff --git a/tcg/tcg.h b/tcg/tcg.h
index b411e17..529acb2 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -333,10 +333,12 @@ typedef enum TCGMemOp {
MO_TE = MO_LE,
#endif
- /* MO_UNALN accesses are never checked for alignment.
+ /*
+ * MO_UNALN accesses are never checked for alignment.
* MO_ALIGN accesses will result in a call to the CPU's
* do_unaligned_access hook if the guest address is not aligned.
- * The default depends on whether the target CPU defines ALIGNED_ONLY.
+ * The default depends on whether the target CPU defines
+ * TARGET_ALIGNED_ONLY.
*
* Some architectures (e.g. ARMv8) need the address which is aligned
* to a size more than the size of the memory access.
@@ -353,7 +355,7 @@ typedef enum TCGMemOp {
*/
MO_ASHIFT = 4,
MO_AMASK = 7 << MO_ASHIFT,
-#ifdef ALIGNED_ONLY
+#ifdef TARGET_ALIGNED_ONLY
MO_ALIGN = 0,
MO_UNALN = MO_AMASK,
#else
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 10960 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
2019-08-16 7:08 ` [Xen-devel] [Qemu-devel] [PATCH v7 01/42] configure: Define TARGET_ALIGNED_ONLY tony.nguyen
@ 2019-08-16 7:26 ` tony.nguyen
2019-08-16 7:27 ` [Xen-devel] [Qemu-devel] [PATCH v7 03/42] memory: Introduce size_memop tony.nguyen
` (41 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:26 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 108419 bytes --]
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.
Target dependant attributes are conditionalized upon NEED_CPU_H.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
---
MAINTAINERS | 1 +
accel/tcg/cputlb.c | 2 +-
include/exec/memop.h | 110 ++++++++++++++++++++++++++
target/alpha/translate.c | 2 +-
target/arm/translate-a64.c | 48 ++++++------
target/arm/translate-a64.h | 2 +-
target/arm/translate-sve.c | 2 +-
target/arm/translate.c | 32 ++++----
target/arm/translate.h | 2 +-
target/hppa/translate.c | 14 ++--
target/i386/translate.c | 132 ++++++++++++++++----------------
target/m68k/translate.c | 2 +-
target/microblaze/translate.c | 4 +-
target/mips/translate.c | 8 +-
target/openrisc/translate.c | 4 +-
target/ppc/translate.c | 12 +--
target/riscv/insn_trans/trans_rva.inc.c | 8 +-
target/riscv/insn_trans/trans_rvi.inc.c | 4 +-
target/s390x/translate.c | 6 +-
target/s390x/translate_vx.inc.c | 10 +--
target/sparc/translate.c | 14 ++--
target/tilegx/translate.c | 10 +--
target/tricore/translate.c | 8 +-
tcg/README | 2 +-
tcg/aarch64/tcg-target.inc.c | 26 +++----
tcg/arm/tcg-target.inc.c | 26 +++----
tcg/i386/tcg-target.inc.c | 24 +++---
tcg/mips/tcg-target.inc.c | 16 ++--
tcg/optimize.c | 2 +-
tcg/ppc/tcg-target.inc.c | 12 +--
tcg/riscv/tcg-target.inc.c | 20 ++---
tcg/s390/tcg-target.inc.c | 14 ++--
tcg/sparc/tcg-target.inc.c | 6 +-
tcg/tcg-op.c | 38 ++++-----
tcg/tcg-op.h | 86 ++++++++++-----------
tcg/tcg.c | 2 +-
tcg/tcg.h | 101 ++----------------------
trace/mem-internal.h | 4 +-
trace/mem.h | 4 +-
39 files changed, 421 insertions(+), 399 deletions(-)
create mode 100644 include/exec/memop.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d6de200..c7cf84a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1889,6 +1889,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
S: Supported
F: include/exec/ioport.h
F: ioport.c
+F: include/exec/memop.h
F: include/exec/memory.h
F: include/exec/ram_addr.h
F: memory.c
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index bb9897b..523be4c 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1133,7 +1133,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
uintptr_t index = tlb_index(env, mmu_idx, addr);
CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr);
target_ulong tlb_addr = tlb_addr_write(tlbe);
- TCGMemOp mop = get_memop(oi);
+ MemOp mop = get_memop(oi);
int a_bits = get_alignment_bits(mop);
int s_bits = mop & MO_SIZE;
void *hostaddr;
diff --git a/include/exec/memop.h b/include/exec/memop.h
new file mode 100644
index 0000000..7262ca3
--- /dev/null
+++ b/include/exec/memop.h
@@ -0,0 +1,110 @@
+/*
+ * Constants for memory operations
+ *
+ * Authors:
+ * Richard Henderson <rth@twiddle.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef MEMOP_H
+#define MEMOP_H
+
+typedef enum MemOp {
+ MO_8 = 0,
+ MO_16 = 1,
+ MO_32 = 2,
+ MO_64 = 3,
+ MO_SIZE = 3, /* Mask for the above. */
+
+ MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
+
+ MO_BSWAP = 8, /* Host reverse endian. */
+#ifdef HOST_WORDS_BIGENDIAN
+ MO_LE = MO_BSWAP,
+ MO_BE = 0,
+#else
+ MO_LE = 0,
+ MO_BE = MO_BSWAP,
+#endif
+#ifdef NEED_CPU_H
+#ifdef TARGET_WORDS_BIGENDIAN
+ MO_TE = MO_BE,
+#else
+ MO_TE = MO_LE,
+#endif
+#endif
+
+ /*
+ * MO_UNALN accesses are never checked for alignment.
+ * MO_ALIGN accesses will result in a call to the CPU's
+ * do_unaligned_access hook if the guest address is not aligned.
+ * The default depends on whether the target CPU defines
+ * TARGET_ALIGNED_ONLY.
+ *
+ * Some architectures (e.g. ARMv8) need the address which is aligned
+ * to a size more than the size of the memory access.
+ * Some architectures (e.g. SPARCv9) need an address which is aligned,
+ * but less strictly than the natural alignment.
+ *
+ * MO_ALIGN supposes the alignment size is the size of a memory access.
+ *
+ * There are three options:
+ * - unaligned access permitted (MO_UNALN).
+ * - an alignment to the size of an access (MO_ALIGN);
+ * - an alignment to a specified size, which may be more or less than
+ * the access size (MO_ALIGN_x where 'x' is a size in bytes);
+ */
+ MO_ASHIFT = 4,
+ MO_AMASK = 7 << MO_ASHIFT,
+#ifdef NEED_CPU_H
+#ifdef TARGET_ALIGNED_ONLY
+ MO_ALIGN = 0,
+ MO_UNALN = MO_AMASK,
+#else
+ MO_ALIGN = MO_AMASK,
+ MO_UNALN = 0,
+#endif
+#endif
+ MO_ALIGN_2 = 1 << MO_ASHIFT,
+ MO_ALIGN_4 = 2 << MO_ASHIFT,
+ MO_ALIGN_8 = 3 << MO_ASHIFT,
+ MO_ALIGN_16 = 4 << MO_ASHIFT,
+ MO_ALIGN_32 = 5 << MO_ASHIFT,
+ MO_ALIGN_64 = 6 << MO_ASHIFT,
+
+ /* Combinations of the above, for ease of use. */
+ MO_UB = MO_8,
+ MO_UW = MO_16,
+ MO_UL = MO_32,
+ MO_SB = MO_SIGN | MO_8,
+ MO_SW = MO_SIGN | MO_16,
+ MO_SL = MO_SIGN | MO_32,
+ MO_Q = MO_64,
+
+ MO_LEUW = MO_LE | MO_UW,
+ MO_LEUL = MO_LE | MO_UL,
+ MO_LESW = MO_LE | MO_SW,
+ MO_LESL = MO_LE | MO_SL,
+ MO_LEQ = MO_LE | MO_Q,
+
+ MO_BEUW = MO_BE | MO_UW,
+ MO_BEUL = MO_BE | MO_UL,
+ MO_BESW = MO_BE | MO_SW,
+ MO_BESL = MO_BE | MO_SL,
+ MO_BEQ = MO_BE | MO_Q,
+
+#ifdef NEED_CPU_H
+ MO_TEUW = MO_TE | MO_UW,
+ MO_TEUL = MO_TE | MO_UL,
+ MO_TESW = MO_TE | MO_SW,
+ MO_TESL = MO_TE | MO_SL,
+ MO_TEQ = MO_TE | MO_Q,
+#endif
+
+ MO_SSIZE = MO_SIZE | MO_SIGN,
+} MemOp;
+
+#endif
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 2c9cccf..d5d4888 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -403,7 +403,7 @@ static inline void gen_store_mem(DisasContext *ctx,
static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
int32_t disp16, int mem_idx,
- TCGMemOp op)
+ MemOp op)
{
TCGLabel *lab_fail, *lab_done;
TCGv addr, val;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d323147..b6c07d6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -85,7 +85,7 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp);
+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
/* initialize TCG globals. */
void a64_translate_init(void)
@@ -455,7 +455,7 @@ TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
* Dn, Sn, Hn or Bn).
* (Note that this is not the same mapping as for A32; see cpu.h)
*/
-static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)
+static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size)
{
return vec_reg_offset(s, regno, 0, size);
}
@@ -871,7 +871,7 @@ static void do_gpr_ld_memidx(DisasContext *s,
bool iss_valid, unsigned int iss_srt,
bool iss_sf, bool iss_ar)
{
- TCGMemOp memop = s->be_data + size;
+ MemOp memop = s->be_data + size;
g_assert(size <= 3);
@@ -948,7 +948,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
TCGv_i64 tmphi;
if (size < 4) {
- TCGMemOp memop = s->be_data + size;
+ MemOp memop = s->be_data + size;
tmphi = tcg_const_i64(0);
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
} else {
@@ -989,7 +989,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
/* Get value of an element within a vector register */
static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
- int element, TCGMemOp memop)
+ int element, MemOp memop)
{
int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
switch (memop) {
@@ -1021,7 +1021,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
}
static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
- int element, TCGMemOp memop)
+ int element, MemOp memop)
{
int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
switch (memop) {
@@ -1048,7 +1048,7 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
/* Set value of an element within a vector register */
static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
- int element, TCGMemOp memop)
+ int element, MemOp memop)
{
int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
switch (memop) {
@@ -1070,7 +1070,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
}
static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
- int destidx, int element, TCGMemOp memop)
+ int destidx, int element, MemOp memop)
{
int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
switch (memop) {
@@ -1090,7 +1090,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
/* Store from vector register to memory */
static void do_vec_st(DisasContext *s, int srcidx, int element,
- TCGv_i64 tcg_addr, int size, TCGMemOp endian)
+ TCGv_i64 tcg_addr, int size, MemOp endian)
{
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
@@ -1102,7 +1102,7 @@ static void do_vec_st(DisasContext *s, int srcidx, int element,
/* Load from memory to vector register */
static void do_vec_ld(DisasContext *s, int destidx, int element,
- TCGv_i64 tcg_addr, int size, TCGMemOp endian)
+ TCGv_i64 tcg_addr, int size, MemOp endian)
{
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
@@ -2200,7 +2200,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
TCGv_i64 addr, int size, bool is_pair)
{
int idx = get_mem_index(s);
- TCGMemOp memop = s->be_data;
+ MemOp memop = s->be_data;
g_assert(size <= 3);
if (is_pair) {
@@ -3286,7 +3286,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
bool is_postidx = extract32(insn, 23, 1);
bool is_q = extract32(insn, 30, 1);
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
- TCGMemOp endian = s->be_data;
+ MemOp endian = s->be_data;
int ebytes; /* bytes per element */
int elements; /* elements per vector */
@@ -5455,7 +5455,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
unsigned int mos, type, rm, cond, rn, rd;
TCGv_i64 t_true, t_false, t_zero;
DisasCompare64 c;
- TCGMemOp sz;
+ MemOp sz;
mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2);
@@ -6267,7 +6267,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
int mos = extract32(insn, 29, 3);
uint64_t imm;
TCGv_i64 tcg_res;
- TCGMemOp sz;
+ MemOp sz;
if (mos || imm5) {
unallocated_encoding(s);
@@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
{
if (esize == size) {
int element;
- TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
+ MemOp msize = esize == 16 ? MO_16 : MO_32;
TCGv_i32 tcg_elem;
/* We should have one register left here */
@@ -8022,7 +8022,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
int shift = (2 * esize) - immhb;
int elements = is_scalar ? 1 : (64 / esize);
bool round = extract32(opcode, 0, 1);
- TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);
+ MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);
TCGv_i64 tcg_rn, tcg_rd, tcg_round;
TCGv_i32 tcg_rd_narrowed;
TCGv_i64 tcg_final;
@@ -8181,7 +8181,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
}
};
NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];
- TCGMemOp memop = scalar ? size : MO_32;
+ MemOp memop = scalar ? size : MO_32;
int maxpass = scalar ? 1 : is_q ? 4 : 2;
for (pass = 0; pass < maxpass; pass++) {
@@ -8225,7 +8225,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
TCGv_i32 tcg_shift = NULL;
- TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
+ MemOp mop = size | (is_signed ? MO_SIGN : 0);
int pass;
if (fracbits || size == MO_64) {
@@ -10004,7 +10004,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
int dsize = is_q ? 128 : 64;
int esize = 8 << size;
int elements = dsize/esize;
- TCGMemOp memop = size | (is_u ? 0 : MO_SIGN);
+ MemOp memop = size | (is_u ? 0 : MO_SIGN);
TCGv_i64 tcg_rn = new_tmp_a64(s);
TCGv_i64 tcg_rd = new_tmp_a64(s);
TCGv_i64 tcg_round;
@@ -10347,7 +10347,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
TCGv_i64 tcg_passres;
- TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
+ MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
int elt = pass + is_q * 2;
@@ -11827,7 +11827,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
if (size == 2) {
/* 32 + 32 -> 64 op */
- TCGMemOp memop = size + (u ? 0 : MO_SIGN);
+ MemOp memop = size + (u ? 0 : MO_SIGN);
for (pass = 0; pass < maxpass; pass++) {
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
@@ -12849,7 +12849,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
switch (is_fp) {
case 1: /* normal fp */
- /* convert insn encoded size to TCGMemOp size */
+ /* convert insn encoded size to MemOp size */
switch (size) {
case 0: /* half-precision */
size = MO_16;
@@ -12897,7 +12897,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
return;
}
- /* Given TCGMemOp size, adjust register and indexing. */
+ /* Given MemOp size, adjust register and indexing. */
switch (size) {
case MO_16:
index = h << 2 | l << 1 | m;
@@ -13194,7 +13194,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
TCGv_i64 tcg_res[2];
int pass;
bool satop = extract32(opcode, 0, 1);
- TCGMemOp memop = MO_32;
+ MemOp memop = MO_32;
if (satop || !u) {
memop |= MO_SIGN;
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 9ab4087..f1246b7 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -64,7 +64,7 @@ static inline void assert_fp_access_checked(DisasContext *s)
* the FP/vector register Qn.
*/
static inline int vec_reg_offset(DisasContext *s, int regno,
- int element, TCGMemOp size)
+ int element, MemOp size)
{
int element_size = 1 << size;
int offs = element * element_size;
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index fa068b0..5d7edd0 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4567,7 +4567,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)
*/
/* The memory mode of the dtype. */
-static const TCGMemOp dtype_mop[16] = {
+static const MemOp dtype_mop[16] = {
MO_UB, MO_UB, MO_UB, MO_UB,
MO_SL, MO_UW, MO_UW, MO_UW,
MO_SW, MO_SW, MO_UL, MO_UL,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7853462..d116c8c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -114,7 +114,7 @@ typedef enum ISSInfo {
} ISSInfo;
/* Save the syndrome information for a Data Abort */
-static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
+static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo)
{
uint32_t syn;
int sas = memop & MO_SIZE;
@@ -1079,7 +1079,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
* that the address argument is TCGv_i32 rather than TCGv.
*/
-static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)
+static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
{
TCGv addr = tcg_temp_new();
tcg_gen_extu_i32_tl(addr, a32);
@@ -1092,7 +1092,7 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)
}
static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
- int index, TCGMemOp opc)
+ int index, MemOp opc)
{
TCGv addr;
@@ -1107,7 +1107,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
}
static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
- int index, TCGMemOp opc)
+ int index, MemOp opc)
{
TCGv addr;
@@ -1160,7 +1160,7 @@ static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
}
static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, TCGMemOp opc)
+ int index, MemOp opc)
{
TCGv addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_ld_i64(val, addr, index, opc);
@@ -1175,7 +1175,7 @@ static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
}
static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, TCGMemOp opc)
+ int index, MemOp opc)
{
TCGv addr = gen_aa32_addr(s, a32, opc);
@@ -1400,7 +1400,7 @@ neon_reg_offset (int reg, int n)
* where 0 is the least significant end of the register.
*/
static inline long
-neon_element_offset(int reg, int element, TCGMemOp size)
+neon_element_offset(int reg, int element, MemOp size)
{
int element_size = 1 << size;
int ofs = element * element_size;
@@ -1422,7 +1422,7 @@ static TCGv_i32 neon_load_reg(int reg, int pass)
return tmp;
}
-static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop)
+static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
{
long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
@@ -1441,7 +1441,7 @@ static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop)
}
}
-static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)
+static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
{
long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
@@ -1469,7 +1469,7 @@ static void neon_store_reg(int reg, int pass, TCGv_i32 var)
tcg_temp_free_i32(var);
}
-static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)
+static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
{
long offset = neon_element_offset(reg, ele, size);
@@ -1488,7 +1488,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)
}
}
-static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)
+static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
{
long offset = neon_element_offset(reg, ele, size);
@@ -3558,7 +3558,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
int n;
int vec_size;
int mmu_idx;
- TCGMemOp endian;
+ MemOp endian;
TCGv_i32 addr;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -6867,7 +6867,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
} else if ((insn & 0x380) == 0) {
/* VDUP */
int element;
- TCGMemOp size;
+ MemOp size;
if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {
return 1;
@@ -7435,7 +7435,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
TCGv_i32 addr, int size)
{
TCGv_i32 tmp = tcg_temp_new_i32();
- TCGMemOp opc = size | MO_ALIGN | s->be_data;
+ MemOp opc = size | MO_ALIGN | s->be_data;
s->is_ldex = true;
@@ -7489,7 +7489,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
TCGv taddr;
TCGLabel *done_label;
TCGLabel *fail_label;
- TCGMemOp opc = size | MO_ALIGN | s->be_data;
+ MemOp opc = size | MO_ALIGN | s->be_data;
/* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
[addr] = {Rt};
@@ -8603,7 +8603,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
*/
TCGv taddr;
- TCGMemOp opc = s->be_data;
+ MemOp opc = s->be_data;
rm = (insn) & 0xf;
diff --git a/target/arm/translate.h b/target/arm/translate.h
index a20f6e2..284c510 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -21,7 +21,7 @@ typedef struct DisasContext {
int condexec_cond;
int thumb;
int sctlr_b;
- TCGMemOp be_data;
+ MemOp be_data;
#if !defined(CONFIG_USER_ONLY)
int user;
#endif
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 188fe68..ff4802a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1500,7 +1500,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
*/
static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
unsigned rx, int scale, target_sreg disp,
- unsigned sp, int modify, TCGMemOp mop)
+ unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
@@ -1518,7 +1518,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
unsigned rx, int scale, target_sreg disp,
- unsigned sp, int modify, TCGMemOp mop)
+ unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
@@ -1536,7 +1536,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
unsigned rx, int scale, target_sreg disp,
- unsigned sp, int modify, TCGMemOp mop)
+ unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
@@ -1554,7 +1554,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
unsigned rx, int scale, target_sreg disp,
- unsigned sp, int modify, TCGMemOp mop)
+ unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
@@ -1580,7 +1580,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
unsigned rx, int scale, target_sreg disp,
- unsigned sp, int modify, TCGMemOp mop)
+ unsigned sp, int modify, MemOp mop)
{
TCGv_reg dest;
@@ -1653,7 +1653,7 @@ static bool trans_fldd(DisasContext *ctx, arg_ldst *a)
static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
target_sreg disp, unsigned sp,
- int modify, TCGMemOp mop)
+ int modify, MemOp mop)
{
nullify_over(ctx);
do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);
@@ -2940,7 +2940,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a)
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
{
- TCGMemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;
+ MemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;
TCGv_reg zero, dest, ofs;
TCGv_tl addr;
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 03150a8..def9867 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -87,8 +87,8 @@ typedef struct DisasContext {
/* current insn context */
int override; /* -1 if no override */
int prefix;
- TCGMemOp aflag;
- TCGMemOp dflag;
+ MemOp aflag;
+ MemOp dflag;
target_ulong pc_start;
target_ulong pc; /* pc = eip + cs_base */
/* current block context */
@@ -149,7 +149,7 @@ static void gen_eob(DisasContext *s);
static void gen_jr(DisasContext *s, TCGv dest);
static void gen_jmp(DisasContext *s, target_ulong eip);
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
-static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d);
+static void gen_op(DisasContext *s1, int op, MemOp ot, int d);
/* i386 arith/logic operations */
enum {
@@ -320,7 +320,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int reg)
}
/* Select the size of a push/pop operation. */
-static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
+static inline MemOp mo_pushpop(DisasContext *s, MemOp ot)
{
if (CODE64(s)) {
return ot == MO_16 ? MO_16 : MO_64;
@@ -330,13 +330,13 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
}
/* Select the size of the stack pointer. */
-static inline TCGMemOp mo_stacksize(DisasContext *s)
+static inline MemOp mo_stacksize(DisasContext *s)
{
return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;
}
/* Select only size 64 else 32. Used for SSE operand sizes. */
-static inline TCGMemOp mo_64_32(TCGMemOp ot)
+static inline MemOp mo_64_32(MemOp ot)
{
#ifdef TARGET_X86_64
return ot == MO_64 ? MO_64 : MO_32;
@@ -347,19 +347,19 @@ static inline TCGMemOp mo_64_32(TCGMemOp ot)
/* Select size 8 if lsb of B is clear, else OT. Used for decoding
byte vs word opcodes. */
-static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)
+static inline MemOp mo_b_d(int b, MemOp ot)
{
return b & 1 ? ot : MO_8;
}
/* Select size 8 if lsb of B is clear, else OT capped at 32.
Used for decoding operand size of port opcodes. */
-static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)
+static inline MemOp mo_b_d32(int b, MemOp ot)
{
return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;
}
-static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)
+static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv t0)
{
switch(ot) {
case MO_8:
@@ -388,7 +388,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)
}
static inline
-void gen_op_mov_v_reg(DisasContext *s, TCGMemOp ot, TCGv t0, int reg)
+void gen_op_mov_v_reg(DisasContext *s, MemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(s, reg)) {
tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);
@@ -411,13 +411,13 @@ static inline void gen_op_jmp_v(TCGv dest)
}
static inline
-void gen_op_add_reg_im(DisasContext *s, TCGMemOp size, int reg, int32_t val)
+void gen_op_add_reg_im(DisasContext *s, MemOp size, int reg, int32_t val)
{
tcg_gen_addi_tl(s->tmp0, cpu_regs[reg], val);
gen_op_mov_reg_v(s, size, reg, s->tmp0);
}
-static inline void gen_op_add_reg_T0(DisasContext *s, TCGMemOp size, int reg)
+static inline void gen_op_add_reg_T0(DisasContext *s, MemOp size, int reg)
{
tcg_gen_add_tl(s->tmp0, cpu_regs[reg], s->T0);
gen_op_mov_reg_v(s, size, reg, s->tmp0);
@@ -451,7 +451,7 @@ static inline void gen_jmp_im(DisasContext *s, target_ulong pc)
/* Compute SEG:REG into A0. SEG is selected from the override segment
(OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to
indicate no override. */
-static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,
+static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0,
int def_seg, int ovr_seg)
{
switch (aflag) {
@@ -514,13 +514,13 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
gen_lea_v_seg(s, s->aflag, cpu_regs[R_EDI], R_ES, -1);
}
-static inline void gen_op_movl_T0_Dshift(DisasContext *s, TCGMemOp ot)
+static inline void gen_op_movl_T0_Dshift(DisasContext *s, MemOp ot)
{
tcg_gen_ld32s_tl(s->T0, cpu_env, offsetof(CPUX86State, df));
tcg_gen_shli_tl(s->T0, s->T0, ot);
};
-static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)
+static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign)
{
switch (size) {
case MO_8:
@@ -551,18 +551,18 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)
}
}
-static void gen_extu(TCGMemOp ot, TCGv reg)
+static void gen_extu(MemOp ot, TCGv reg)
{
gen_ext_tl(reg, reg, ot, false);
}
-static void gen_exts(TCGMemOp ot, TCGv reg)
+static void gen_exts(MemOp ot, TCGv reg)
{
gen_ext_tl(reg, reg, ot, true);
}
static inline
-void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)
+void gen_op_jnz_ecx(DisasContext *s, MemOp size, TCGLabel *label1)
{
tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]);
gen_extu(size, s->tmp0);
@@ -570,14 +570,14 @@ void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)
}
static inline
-void gen_op_jz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)
+void gen_op_jz_ecx(DisasContext *s, MemOp size, TCGLabel *label1)
{
tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]);
gen_extu(size, s->tmp0);
tcg_gen_brcondi_tl(TCG_COND_EQ, s->tmp0, 0, label1);
}
-static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)
+static void gen_helper_in_func(MemOp ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
case MO_8:
@@ -594,7 +594,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)
}
}
-static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)
+static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
case MO_8:
@@ -611,7 +611,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)
}
}
-static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
+static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip,
uint32_t svm_flags)
{
target_ulong next_eip;
@@ -644,7 +644,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
}
}
-static inline void gen_movs(DisasContext *s, TCGMemOp ot)
+static inline void gen_movs(DisasContext *s, MemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, s->T0, s->A0);
@@ -840,7 +840,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
default:
{
- TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
+ MemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };
}
@@ -885,7 +885,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
.mask = -1 };
default:
{
- TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
+ MemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
}
@@ -897,7 +897,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
{
int inv, jcc_op, cond;
- TCGMemOp size;
+ MemOp size;
CCPrepare cc;
TCGv t0;
@@ -1075,7 +1075,7 @@ static TCGLabel *gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
return l2;
}
-static inline void gen_stos(DisasContext *s, TCGMemOp ot)
+static inline void gen_stos(DisasContext *s, MemOp ot)
{
gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);
gen_string_movl_A0_EDI(s);
@@ -1084,7 +1084,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s, s->aflag, R_EDI);
}
-static inline void gen_lods(DisasContext *s, TCGMemOp ot)
+static inline void gen_lods(DisasContext *s, MemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, s->T0, s->A0);
@@ -1093,7 +1093,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s, s->aflag, R_ESI);
}
-static inline void gen_scas(DisasContext *s, TCGMemOp ot)
+static inline void gen_scas(DisasContext *s, MemOp ot)
{
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, s->T1, s->A0);
@@ -1102,7 +1102,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s, s->aflag, R_EDI);
}
-static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
+static inline void gen_cmps(DisasContext *s, MemOp ot)
{
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, s->T1, s->A0);
@@ -1126,7 +1126,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)
}
-static inline void gen_ins(DisasContext *s, TCGMemOp ot)
+static inline void gen_ins(DisasContext *s, MemOp ot)
{
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -1148,7 +1148,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
}
}
-static inline void gen_outs(DisasContext *s, TCGMemOp ot)
+static inline void gen_outs(DisasContext *s, MemOp ot)
{
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -1171,7 +1171,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
/* same method as Valgrind : we generate jumps to current or next
instruction */
#define GEN_REPZ(op) \
-static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
+static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \
target_ulong cur_eip, target_ulong next_eip) \
{ \
TCGLabel *l2; \
@@ -1187,7 +1187,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
}
#define GEN_REPZ2(op) \
-static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
+static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \
target_ulong cur_eip, \
target_ulong next_eip, \
int nz) \
@@ -1284,7 +1284,7 @@ static void gen_illegal_opcode(DisasContext *s)
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
-static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
+static void gen_op(DisasContext *s1, int op, MemOp ot, int d)
{
if (d != OR_TMP0) {
if (s1->prefix & PREFIX_LOCK) {
@@ -1395,7 +1395,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
-static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
+static void gen_inc(DisasContext *s1, MemOp ot, int d, int c)
{
if (s1->prefix & PREFIX_LOCK) {
if (d != OR_TMP0) {
@@ -1421,7 +1421,7 @@ static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
set_cc_op(s1, (c > 0 ? CC_OP_INCB : CC_OP_DECB) + ot);
}
-static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,
+static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
TCGv shm1, TCGv count, bool is_right)
{
TCGv_i32 z32, s32, oldop;
@@ -1466,7 +1466,7 @@ static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,
set_cc_op(s, CC_OP_DYNAMIC);
}
-static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
+static void gen_shift_rm_T1(DisasContext *s, MemOp ot, int op1,
int is_right, int is_arith)
{
target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1502,7 +1502,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, is_right);
}
-static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
+static void gen_shift_rm_im(DisasContext *s, MemOp ot, int op1, int op2,
int is_right, int is_arith)
{
int mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1542,7 +1542,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
}
}
-static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
+static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
{
target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
TCGv_i32 t0, t1;
@@ -1627,7 +1627,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
set_cc_op(s, CC_OP_DYNAMIC);
}
-static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
+static void gen_rot_rm_im(DisasContext *s, MemOp ot, int op1, int op2,
int is_right)
{
int mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1705,7 +1705,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
}
/* XXX: add faster immediate = 1 case */
-static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
+static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,
int is_right)
{
gen_compute_eflags(s);
@@ -1761,7 +1761,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
}
/* XXX: add faster immediate case */
-static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
+static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1,
bool is_right, TCGv count_in)
{
target_ulong mask = (ot == MO_64 ? 63 : 31);
@@ -1842,7 +1842,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
tcg_temp_free(count);
}
-static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
+static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s)
{
if (s != OR_TMP1)
gen_op_mov_v_reg(s1, ot, s1->T1, s);
@@ -1872,7 +1872,7 @@ static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
}
}
-static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)
+static void gen_shifti(DisasContext *s1, int op, MemOp ot, int d, int c)
{
switch(op) {
case OP_ROL:
@@ -2149,7 +2149,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
OR_TMP0 */
static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
- TCGMemOp ot, int reg, int is_store)
+ MemOp ot, int reg, int is_store)
{
int mod, rm;
@@ -2179,7 +2179,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
}
}
-static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)
+static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)
{
uint32_t ret;
@@ -2202,7 +2202,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)
return ret;
}
-static inline int insn_const_size(TCGMemOp ot)
+static inline int insn_const_size(MemOp ot)
{
if (ot <= MO_32) {
return 1 << ot;
@@ -2266,7 +2266,7 @@ static inline void gen_jcc(DisasContext *s, int b,
}
}
-static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
+static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,
int modrm, int reg)
{
CCPrepare cc;
@@ -2363,8 +2363,8 @@ static inline void gen_stack_update(DisasContext *s, int addend)
/* Generate a push. It depends on ss32, addseg and dflag. */
static void gen_push_v(DisasContext *s, TCGv val)
{
- TCGMemOp d_ot = mo_pushpop(s, s->dflag);
- TCGMemOp a_ot = mo_stacksize(s);
+ MemOp d_ot = mo_pushpop(s, s->dflag);
+ MemOp a_ot = mo_stacksize(s);
int size = 1 << d_ot;
TCGv new_esp = s->A0;
@@ -2383,9 +2383,9 @@ static void gen_push_v(DisasContext *s, TCGv val)
}
/* two step pop is necessary for precise exceptions */
-static TCGMemOp gen_pop_T0(DisasContext *s)
+static MemOp gen_pop_T0(DisasContext *s)
{
- TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ MemOp d_ot = mo_pushpop(s, s->dflag);
gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1);
gen_op_ld_v(s, d_ot, s->T0, s->A0);
@@ -2393,7 +2393,7 @@ static TCGMemOp gen_pop_T0(DisasContext *s)
return d_ot;
}
-static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)
+static inline void gen_pop_update(DisasContext *s, MemOp ot)
{
gen_stack_update(s, 1 << ot);
}
@@ -2405,8 +2405,8 @@ static inline void gen_stack_A0(DisasContext *s)
static void gen_pusha(DisasContext *s)
{
- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;
- TCGMemOp d_ot = s->dflag;
+ MemOp s_ot = s->ss32 ? MO_32 : MO_16;
+ MemOp d_ot = s->dflag;
int size = 1 << d_ot;
int i;
@@ -2421,8 +2421,8 @@ static void gen_pusha(DisasContext *s)
static void gen_popa(DisasContext *s)
{
- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;
- TCGMemOp d_ot = s->dflag;
+ MemOp s_ot = s->ss32 ? MO_32 : MO_16;
+ MemOp d_ot = s->dflag;
int size = 1 << d_ot;
int i;
@@ -2442,8 +2442,8 @@ static void gen_popa(DisasContext *s)
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- TCGMemOp d_ot = mo_pushpop(s, s->dflag);
- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;
+ MemOp d_ot = mo_pushpop(s, s->dflag);
+ MemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;
int size = 1 << d_ot;
/* Push BP; compute FrameTemp into T1. */
@@ -2482,8 +2482,8 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
static void gen_leave(DisasContext *s)
{
- TCGMemOp d_ot = mo_pushpop(s, s->dflag);
- TCGMemOp a_ot = mo_stacksize(s);
+ MemOp d_ot = mo_pushpop(s, s->dflag);
+ MemOp a_ot = mo_stacksize(s);
gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1);
gen_op_ld_v(s, d_ot, s->T0, s->A0);
@@ -3045,7 +3045,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
SSEFunc_0_eppi sse_fn_eppi;
SSEFunc_0_ppi sse_fn_ppi;
SSEFunc_0_eppt sse_fn_eppt;
- TCGMemOp ot;
+ MemOp ot;
b &= 0xff;
if (s->prefix & PREFIX_DATA)
@@ -4488,7 +4488,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
CPUX86State *env = cpu->env_ptr;
int b, prefixes;
int shift;
- TCGMemOp ot, aflag, dflag;
+ MemOp ot, aflag, dflag;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -5567,8 +5567,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
case 0x1be: /* movsbS Gv, Eb */
case 0x1bf: /* movswS Gv, Eb */
{
- TCGMemOp d_ot;
- TCGMemOp s_ot;
+ MemOp d_ot;
+ MemOp s_ot;
/* d_ot is the size of destination */
d_ot = dflag;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 60bcfb7..24c1dd3 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2414,7 +2414,7 @@ DISAS_INSN(cas)
uint16_t ext;
TCGv load;
TCGv cmp;
- TCGMemOp opc;
+ MemOp opc;
switch ((insn >> 9) & 3) {
case 1:
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 9ce65f3..41d1b8b 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -919,7 +919,7 @@ static void dec_load(DisasContext *dc)
unsigned int size;
bool rev = false, ex = false, ea = false;
int mem_index = cpu_mmu_index(&dc->cpu->env, false);
- TCGMemOp mop;
+ MemOp mop;
mop = dc->opcode & 3;
size = 1 << mop;
@@ -1035,7 +1035,7 @@ static void dec_store(DisasContext *dc)
unsigned int size;
bool rev = false, ex = false, ea = false;
int mem_index = cpu_mmu_index(&dc->cpu->env, false);
- TCGMemOp mop;
+ MemOp mop;
mop = dc->opcode & 3;
size = 1 << mop;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ca62800..59b5d85 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2526,7 +2526,7 @@ typedef struct DisasContext {
int32_t CP0_Config5;
/* Routine used to access memory */
int mem_idx;
- TCGMemOp default_tcg_memop_mask;
+ MemOp default_tcg_memop_mask;
uint32_t hflags, saved_hflags;
target_ulong btarget;
bool ulri;
@@ -3706,7 +3706,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
/* Store conditional */
static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
- TCGMemOp tcg_mo, bool eva)
+ MemOp tcg_mo, bool eva)
{
TCGv addr, t0, val;
TCGLabel *l1 = gen_new_label();
@@ -4546,7 +4546,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
static inline void gen_r6_ld(target_long addr, int reg, int memidx,
- TCGMemOp memop)
+ MemOp memop)
{
TCGv t0 = tcg_const_tl(addr);
tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
@@ -21828,7 +21828,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
extract32(ctx->opcode, 0, 8);
TCGv va = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- TCGMemOp memop = (extract32(ctx->opcode, 8, 3)) ==
+ MemOp memop = (extract32(ctx->opcode, 8, 3)) ==
NM_P_LS_UAWM ? MO_UNALN : 0;
count = (count == 0) ? 8 : count;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 4360ce4..b189c50 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -681,7 +681,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a)
return true;
}
-static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop)
+static void do_load(DisasContext *dc, arg_load *a, MemOp mop)
{
TCGv ea;
@@ -763,7 +763,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
return true;
}
-static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop)
+static void do_store(DisasContext *dc, arg_store *a, MemOp mop)
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[a->a], a->i);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4a5de28..31800ed 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -162,7 +162,7 @@ struct DisasContext {
int mem_idx;
int access_type;
/* Translation flags */
- TCGMemOp default_tcg_memop_mask;
+ MemOp default_tcg_memop_mask;
#if defined(TARGET_PPC64)
bool sf_mode;
bool has_cfar;
@@ -3142,7 +3142,7 @@ static void gen_isync(DisasContext *ctx)
#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
-static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
+static void gen_load_locked(DisasContext *ctx, MemOp memop)
{
TCGv gpr = cpu_gpr[rD(ctx->opcode)];
TCGv t0 = tcg_temp_new();
@@ -3167,7 +3167,7 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
LARX(lharx, DEF_MEMOP(MO_UW))
LARX(lwarx, DEF_MEMOP(MO_UL))
-static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
+static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
TCGv EA, TCGCond cond, int addend)
{
TCGv t = tcg_temp_new();
@@ -3193,7 +3193,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
tcg_temp_free(u);
}
-static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
+static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
{
uint32_t gpr_FC = FC(ctx->opcode);
TCGv EA = tcg_temp_new();
@@ -3306,7 +3306,7 @@ static void gen_ldat(DisasContext *ctx)
}
#endif
-static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
+static void gen_st_atomic(DisasContext *ctx, MemOp memop)
{
uint32_t gpr_FC = FC(ctx->opcode);
TCGv EA = tcg_temp_new();
@@ -3389,7 +3389,7 @@ static void gen_stdat(DisasContext *ctx)
}
#endif
-static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
+static void gen_conditional_store(DisasContext *ctx, MemOp memop)
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
index fadd888..be8a9f0 100644
--- a/target/riscv/insn_trans/trans_rva.inc.c
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -18,7 +18,7 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1 = tcg_temp_new();
/* Put addr in load_res, data in load_val. */
@@ -37,7 +37,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
return true;
}
-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1 = tcg_temp_new();
TCGv src2 = tcg_temp_new();
@@ -82,8 +82,8 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
}
static bool gen_amo(DisasContext *ctx, arg_atomic *a,
- void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),
- TCGMemOp mop)
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
+ MemOp mop)
{
TCGv src1 = tcg_temp_new();
TCGv src2 = tcg_temp_new();
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index ea64731..cf440d1 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -135,7 +135,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
-static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
+static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -174,7 +174,7 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
-static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
+static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index ac0d8b6..2927247 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -152,7 +152,7 @@ static inline int vec_full_reg_offset(uint8_t reg)
return offsetof(CPUS390XState, vregs[reg][0]);
}
-static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)
+static inline int vec_reg_offset(uint8_t reg, uint8_t enr, MemOp es)
{
/* Convert element size (es) - e.g. MO_8 - to bytes */
const uint8_t bytes = 1 << es;
@@ -2262,7 +2262,7 @@ static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
{
- TCGMemOp mop = s->insn->data;
+ MemOp mop = s->insn->data;
TCGv_i64 addr, old, cc;
TCGLabel *lab = gen_new_label();
@@ -3228,7 +3228,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
{
TCGv_i64 a1, a2;
- TCGMemOp mop = s->insn->data;
+ MemOp mop = s->insn->data;
/* In a parallel context, stop the world and single step. */
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 41d5cf8..4c56bbb 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -57,13 +57,13 @@
#define FPF_LONG 3
#define FPF_EXT 4
-static inline bool valid_vec_element(uint8_t enr, TCGMemOp es)
+static inline bool valid_vec_element(uint8_t enr, MemOp es)
{
return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));
}
static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
- TCGMemOp memop)
+ MemOp memop)
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
@@ -96,7 +96,7 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
}
static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
- TCGMemOp memop)
+ MemOp memop)
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
@@ -123,7 +123,7 @@ static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
}
static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
- TCGMemOp memop)
+ MemOp memop)
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
@@ -146,7 +146,7 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,
- TCGMemOp memop)
+ MemOp memop)
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 091bab5..bef9ce6 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2019,7 +2019,7 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
}
static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
- TCGv addr, int mmu_idx, TCGMemOp memop)
+ TCGv addr, int mmu_idx, MemOp memop)
{
gen_address_mask(dc, addr);
tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
@@ -2050,10 +2050,10 @@ typedef struct {
ASIType type;
int asi;
int mem_idx;
- TCGMemOp memop;
+ MemOp memop;
} DisasASI;
-static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
+static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
{
int asi = GET_FIELD(insn, 19, 26);
ASIType type = GET_ASI_HELPER;
@@ -2267,7 +2267,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
}
static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
- int insn, TCGMemOp memop)
+ int insn, MemOp memop)
{
DisasASI da = get_asi(dc, insn, memop);
@@ -2305,7 +2305,7 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
}
static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
- int insn, TCGMemOp memop)
+ int insn, MemOp memop)
{
DisasASI da = get_asi(dc, insn, memop);
@@ -2511,7 +2511,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
case GET_ASI_BLOCK:
/* Valid for lddfa on aligned registers only. */
if (size == 8 && (rd & 7) == 0) {
- TCGMemOp memop;
+ MemOp memop;
TCGv eight;
int i;
@@ -2625,7 +2625,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
case GET_ASI_BLOCK:
/* Valid for stdfa on aligned registers only. */
if (size == 8 && (rd & 7) == 0) {
- TCGMemOp memop;
+ MemOp memop;
TCGv eight;
int i;
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index c46a4ab..68dd4aa 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -290,7 +290,7 @@ static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd)
}
static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
- unsigned srcb, TCGMemOp memop, const char *name)
+ unsigned srcb, MemOp memop, const char *name)
{
if (dest) {
return TILEGX_EXCP_OPCODE_UNKNOWN;
@@ -305,7 +305,7 @@ static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
}
static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
- int imm, TCGMemOp memop, const char *name)
+ int imm, MemOp memop, const char *name)
{
TCGv tsrca = load_gr(dc, srca);
TCGv tsrcb = load_gr(dc, srcb);
@@ -496,7 +496,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
{
TCGv tdest, tsrca;
const char *mnemonic;
- TCGMemOp memop;
+ MemOp memop;
TileExcp ret = TILEGX_EXCP_NONE;
bool prefetch_nofault = false;
@@ -1478,7 +1478,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
TCGv tsrca = load_gr(dc, srca);
bool prefetch_nofault = false;
const char *mnemonic;
- TCGMemOp memop;
+ MemOp memop;
int i2, i3;
TCGv t0;
@@ -2106,7 +2106,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
unsigned srca = get_SrcA_Y2(bundle);
unsigned srcbdest = get_SrcBDest_Y2(bundle);
const char *mnemonic;
- TCGMemOp memop;
+ MemOp memop;
bool prefetch_nofault = false;
switch (OEY2(opc, mode)) {
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index dc2a65f..87a5f50 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -227,7 +227,7 @@ static inline void generate_trap(DisasContext *ctx, int class, int tin);
/* Functions for load/save to/from memory */
static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
- int16_t con, TCGMemOp mop)
+ int16_t con, MemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, con);
@@ -236,7 +236,7 @@ static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
}
static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
- int16_t con, TCGMemOp mop)
+ int16_t con, MemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, con);
@@ -284,7 +284,7 @@ static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
}
static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
- TCGMemOp mop)
+ MemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, off);
@@ -294,7 +294,7 @@ static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
}
static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
- TCGMemOp mop)
+ MemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, off);
diff --git a/tcg/README b/tcg/README
index 21fcdf7..b4382fa 100644
--- a/tcg/README
+++ b/tcg/README
@@ -512,7 +512,7 @@ Both t0 and t1 may be split into little-endian ordered pairs of registers
if dealing with 64-bit quantities on a 32-bit host.
The memidx selects the qemu tlb index to use (e.g. user or kernel access).
-The flags are the TCGMemOp bits, selecting the sign, width, and endianness
+The flags are the MemOp bits, selecting the sign, width, and endianness
of the memory access.
For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 0713448..3f92101 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -1423,7 +1423,7 @@ static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn)
tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn);
}
-static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,
+static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,
TCGReg rd, TCGReg rn)
{
/* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */
@@ -1431,7 +1431,7 @@ static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,
tcg_out_sbfm(s, ext, rd, rn, 0, bits);
}
-static inline void tcg_out_uxt(TCGContext *s, TCGMemOp s_bits,
+static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits,
TCGReg rd, TCGReg rn)
{
/* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */
@@ -1580,8 +1580,8 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
- TCGMemOp size = opc & MO_SIZE;
+ MemOp opc = get_memop(oi);
+ MemOp size = opc & MO_SIZE;
if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
return false;
@@ -1605,8 +1605,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
- TCGMemOp size = opc & MO_SIZE;
+ MemOp opc = get_memop(oi);
+ MemOp size = opc & MO_SIZE;
if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
return false;
@@ -1649,7 +1649,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);
slow path for the failure case, which will be patched later when finalizing
the slow path. Generated code returns the host addend in X1,
clobbers X0,X2,X3,TMP. */
-static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
+static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
tcg_insn_unit **label_ptr, int mem_index,
bool is_read)
{
@@ -1709,11 +1709,11 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
#endif /* CONFIG_SOFTMMU */
-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,
+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
TCGReg data_r, TCGReg addr_r,
TCGType otype, TCGReg off_r)
{
- const TCGMemOp bswap = memop & MO_BSWAP;
+ const MemOp bswap = memop & MO_BSWAP;
switch (memop & MO_SSIZE) {
case MO_UB:
@@ -1765,11 +1765,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,
}
}
-static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,
+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
TCGReg data_r, TCGReg addr_r,
TCGType otype, TCGReg off_r)
{
- const TCGMemOp bswap = memop & MO_BSWAP;
+ const MemOp bswap = memop & MO_BSWAP;
switch (memop & MO_SIZE) {
case MO_8:
@@ -1804,7 +1804,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
TCGMemOpIdx oi, TCGType ext)
{
- TCGMemOp memop = get_memop(oi);
+ MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
@@ -1829,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
TCGMemOpIdx oi)
{
- TCGMemOp memop = get_memop(oi);
+ MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index ece88dc..94d80d7 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1233,7 +1233,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
- TCGMemOp opc, int mem_index, bool is_load)
+ MemOp opc, int mem_index, bool is_load)
{
int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
@@ -1348,7 +1348,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg argreg, datalo, datahi;
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
void *func;
if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
@@ -1412,7 +1412,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg argreg, datalo, datahi;
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
return false;
@@ -1453,11 +1453,11 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
}
#endif /* SOFTMMU */
-static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,
+static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addend)
{
- TCGMemOp bswap = opc & MO_BSWAP;
+ MemOp bswap = opc & MO_BSWAP;
switch (opc & MO_SSIZE) {
case MO_UB:
@@ -1514,11 +1514,11 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,
}
}
-static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc,
+static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo)
{
- TCGMemOp bswap = opc & MO_BSWAP;
+ MemOp bswap = opc & MO_BSWAP;
switch (opc & MO_SSIZE) {
case MO_UB:
@@ -1577,7 +1577,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
TCGReg addend;
@@ -1614,11 +1614,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
#endif
}
-static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,
+static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addend)
{
- TCGMemOp bswap = opc & MO_BSWAP;
+ MemOp bswap = opc & MO_BSWAP;
switch (opc & MO_SIZE) {
case MO_8:
@@ -1659,11 +1659,11 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,
}
}
-static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,
+static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo)
{
- TCGMemOp bswap = opc & MO_BSWAP;
+ MemOp bswap = opc & MO_BSWAP;
switch (opc & MO_SIZE) {
case MO_8:
@@ -1708,7 +1708,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
TCGReg addend;
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 6ddeebf..9d8ed97 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -1697,7 +1697,7 @@ static void * const qemu_st_helpers[16] = {
First argument register is clobbered. */
static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
- int mem_index, TCGMemOp opc,
+ int mem_index, MemOp opc,
tcg_insn_unit **label_ptr, int which)
{
const TCGReg r0 = TCG_REG_L0;
@@ -1810,7 +1810,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
TCGMemOpIdx oi = l->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
TCGReg data_reg;
tcg_insn_unit **label_ptr = &l->label_ptr[0];
int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0);
@@ -1895,8 +1895,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
TCGMemOpIdx oi = l->oi;
- TCGMemOp opc = get_memop(oi);
- TCGMemOp s_bits = opc & MO_SIZE;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
tcg_insn_unit **label_ptr = &l->label_ptr[0];
TCGReg retaddr;
@@ -1995,10 +1995,10 @@ static inline int setup_guest_base_seg(void)
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg base, int index, intptr_t ofs,
- int seg, bool is64, TCGMemOp memop)
+ int seg, bool is64, MemOp memop)
{
- const TCGMemOp real_bswap = memop & MO_BSWAP;
- TCGMemOp bswap = real_bswap;
+ const MemOp real_bswap = memop & MO_BSWAP;
+ MemOp bswap = real_bswap;
int rexw = is64 * P_REXW;
int movop = OPC_MOVL_GvEv;
@@ -2103,7 +2103,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
tcg_insn_unit *label_ptr[2];
@@ -2137,15 +2137,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg base, int index, intptr_t ofs,
- int seg, TCGMemOp memop)
+ int seg, MemOp memop)
{
/* ??? Ideally we wouldn't need a scratch register. For user-only,
we could perform the bswap twice to restore the original value
instead of moving to the scratch. But as it is, the L constraint
means that TCG_REG_L0 is definitely free here. */
const TCGReg scratch = TCG_REG_L0;
- const TCGMemOp real_bswap = memop & MO_BSWAP;
- TCGMemOp bswap = real_bswap;
+ const MemOp real_bswap = memop & MO_BSWAP;
+ MemOp bswap = real_bswap;
int movop = OPC_MOVL_EvGv;
if (have_movbe && real_bswap) {
@@ -2221,7 +2221,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
tcg_insn_unit *label_ptr[2];
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 41bff32..5442167 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -1215,7 +1215,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
TCGReg addrh, TCGMemOpIdx oi,
tcg_insn_unit *label_ptr[2], bool is_load)
{
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
int mem_index = get_mmuidx(oi);
@@ -1313,7 +1313,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
TCGMemOpIdx oi = l->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
TCGReg v0;
int i;
@@ -1363,8 +1363,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
TCGMemOpIdx oi = l->oi;
- TCGMemOp opc = get_memop(oi);
- TCGMemOp s_bits = opc & MO_SIZE;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
int i;
/* resolve label address */
@@ -1413,7 +1413,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
#endif
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, TCGMemOp opc, bool is_64)
+ TCGReg base, MemOp opc, bool is_64)
{
switch (opc & (MO_SSIZE | MO_BSWAP)) {
case MO_UB:
@@ -1521,7 +1521,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
#endif
@@ -1558,7 +1558,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
}
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, TCGMemOp opc)
+ TCGReg base, MemOp opc)
{
/* Don't clutter the code below with checks to avoid bswapping ZERO. */
if ((lo | hi) == 0) {
@@ -1624,7 +1624,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
#endif
diff --git a/tcg/optimize.c b/tcg/optimize.c
index d2424de..a89ffda 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1014,7 +1014,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(qemu_ld):
{
TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
- TCGMemOp mop = get_memop(oi);
+ MemOp mop = get_memop(oi);
if (!(mop & MO_SIGN)) {
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
}
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 852b894..815edac 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -1506,7 +1506,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
in CR7, loads the addend of the TLB into R3, and returns the register
containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
-static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
+static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
TCGReg addrlo, TCGReg addrhi,
int mem_index, bool is_read)
{
@@ -1633,7 +1633,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
TCGReg hi, lo, arg = TCG_REG_R3;
if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
@@ -1680,8 +1680,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
- TCGMemOp s_bits = opc & MO_SIZE;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
TCGReg hi, lo, arg = TCG_REG_R3;
if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
@@ -1744,7 +1744,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
TCGMemOpIdx oi;
- TCGMemOp opc, s_bits;
+ MemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
tcg_insn_unit *label_ptr;
@@ -1819,7 +1819,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
TCGMemOpIdx oi;
- TCGMemOp opc, s_bits;
+ MemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
tcg_insn_unit *label_ptr;
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 3e76bf5..7018509 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -970,7 +970,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
TCGReg addrh, TCGMemOpIdx oi,
tcg_insn_unit **label_ptr, bool is_load)
{
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
tcg_target_long compare_mask;
@@ -1044,7 +1044,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
TCGMemOpIdx oi = l->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
TCGReg a0 = tcg_target_call_iarg_regs[0];
TCGReg a1 = tcg_target_call_iarg_regs[1];
TCGReg a2 = tcg_target_call_iarg_regs[2];
@@ -1077,8 +1077,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
TCGMemOpIdx oi = l->oi;
- TCGMemOp opc = get_memop(oi);
- TCGMemOp s_bits = opc & MO_SIZE;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
TCGReg a0 = tcg_target_call_iarg_regs[0];
TCGReg a1 = tcg_target_call_iarg_regs[1];
TCGReg a2 = tcg_target_call_iarg_regs[2];
@@ -1121,9 +1121,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
#endif /* CONFIG_SOFTMMU */
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, TCGMemOp opc, bool is_64)
+ TCGReg base, MemOp opc, bool is_64)
{
- const TCGMemOp bswap = opc & MO_BSWAP;
+ const MemOp bswap = opc & MO_BSWAP;
/* We don't yet handle byteswapping, assert */
g_assert(!bswap);
@@ -1172,7 +1172,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
#endif
@@ -1208,9 +1208,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
}
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, TCGMemOp opc)
+ TCGReg base, MemOp opc)
{
- const TCGMemOp bswap = opc & MO_BSWAP;
+ const MemOp bswap = opc & MO_BSWAP;
/* We don't yet handle byteswapping, assert */
g_assert(!bswap);
@@ -1243,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
TCGMemOpIdx oi;
- TCGMemOp opc;
+ MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
#endif
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index fe42939..8aaa4ce 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1430,7 +1430,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
}
}
-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp)
{
switch (opc & (MO_SSIZE | MO_BSWAP)) {
@@ -1489,7 +1489,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
}
}
-static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp)
{
switch (opc & (MO_SIZE | MO_BSWAP)) {
@@ -1544,7 +1544,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
addend into R2. Returns a register with the santitized guest address. */
-static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
+static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
int mem_index, bool is_ld)
{
unsigned s_bits = opc & MO_SIZE;
@@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
TCGReg addr_reg = lb->addrlo_reg;
TCGReg data_reg = lb->datalo_reg;
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
(intptr_t)s->code_ptr, 2)) {
@@ -1639,7 +1639,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
TCGReg addr_reg = lb->addrlo_reg;
TCGReg data_reg = lb->datalo_reg;
TCGMemOpIdx oi = lb->oi;
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
(intptr_t)s->code_ptr, 2)) {
@@ -1694,7 +1694,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
TCGMemOpIdx oi)
{
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
@@ -1721,7 +1721,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
TCGMemOpIdx oi)
{
- TCGMemOp opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 10b1cea..d7986cd 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1081,7 +1081,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));
is in the returned register, maybe %o0. The TLB addend is in %o1. */
static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
- TCGMemOp opc, int which)
+ MemOp opc, int which)
{
int fast_off = TLB_MASK_TABLE_OFS(mem_index);
int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
@@ -1164,7 +1164,7 @@ static const int qemu_st_opc[16] = {
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
TCGMemOpIdx oi, bool is_64)
{
- TCGMemOp memop = get_memop(oi);
+ MemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
unsigned memi = get_mmuidx(oi);
TCGReg addrz, param;
@@ -1246,7 +1246,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
TCGMemOpIdx oi)
{
- TCGMemOp memop = get_memop(oi);
+ MemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
unsigned memi = get_mmuidx(oi);
TCGReg addrz, param;
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 587d092..e87c327 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2714,7 +2714,7 @@ void tcg_gen_lookup_and_goto_ptr(void)
}
}
-static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)
+static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
{
/* Trigger the asserts within as early as possible. */
(void)get_alignment_bits(op);
@@ -2743,7 +2743,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)
}
static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
- TCGMemOp memop, TCGArg idx)
+ MemOp memop, TCGArg idx)
{
TCGMemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
@@ -2758,7 +2758,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
}
static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
- TCGMemOp memop, TCGArg idx)
+ MemOp memop, TCGArg idx)
{
TCGMemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
@@ -2788,9 +2788,9 @@ static void tcg_gen_req_mo(TCGBar type)
}
}
-void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
- TCGMemOp orig_memop;
+ MemOp orig_memop;
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
@@ -2825,7 +2825,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
}
-void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i32 swap = NULL;
@@ -2858,9 +2858,9 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
}
-void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
- TCGMemOp orig_memop;
+ MemOp orig_memop;
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
@@ -2911,7 +2911,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
}
-void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i64 swap = NULL;
@@ -2953,7 +2953,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
}
-static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)
+static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc)
{
switch (opc & MO_SSIZE) {
case MO_SB:
@@ -2974,7 +2974,7 @@ static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)
}
}
-static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc)
+static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc)
{
switch (opc & MO_SSIZE) {
case MO_SB:
@@ -3034,7 +3034,7 @@ static void * const table_cmpxchg[16] = {
};
void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
- TCGv_i32 newv, TCGArg idx, TCGMemOp memop)
+ TCGv_i32 newv, TCGArg idx, MemOp memop)
{
memop = tcg_canonicalize_memop(memop, 0, 0);
@@ -3078,7 +3078,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
}
void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
- TCGv_i64 newv, TCGArg idx, TCGMemOp memop)
+ TCGv_i64 newv, TCGArg idx, MemOp memop)
{
memop = tcg_canonicalize_memop(memop, 1, 0);
@@ -3142,7 +3142,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
}
static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
- TCGArg idx, TCGMemOp memop, bool new_val,
+ TCGArg idx, MemOp memop, bool new_val,
void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
{
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -3160,7 +3160,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
}
static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
- TCGArg idx, TCGMemOp memop, void * const table[])
+ TCGArg idx, MemOp memop, void * const table[])
{
gen_atomic_op_i32 gen;
@@ -3185,7 +3185,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
}
static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
- TCGArg idx, TCGMemOp memop, bool new_val,
+ TCGArg idx, MemOp memop, bool new_val,
void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
{
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -3203,7 +3203,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
}
static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
- TCGArg idx, TCGMemOp memop, void * const table[])
+ TCGArg idx, MemOp memop, void * const table[])
{
memop = tcg_canonicalize_memop(memop, 1, 0);
@@ -3257,7 +3257,7 @@ static void * const table_##NAME[16] = { \
WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \
}; \
void tcg_gen_atomic_##NAME##_i32 \
- (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
+ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \
{ \
if (tcg_ctx->tb_cflags & CF_PARALLEL) { \
do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \
@@ -3267,7 +3267,7 @@ void tcg_gen_atomic_##NAME##_i32 \
} \
} \
void tcg_gen_atomic_##NAME##_i64 \
- (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
+ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \
{ \
if (tcg_ctx->tb_cflags & CF_PARALLEL) { \
do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 2d4dd5c..e9cf172 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -851,10 +851,10 @@ void tcg_gen_lookup_and_goto_ptr(void);
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
#endif
-void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
-void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
-void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
-void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
+void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp);
+void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp);
+void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp);
+void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
{
@@ -912,46 +912,46 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
}
void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
- TCGArg, TCGMemOp);
+ TCGArg, MemOp);
void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
- TCGArg, TCGMemOp);
-
-void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-
-void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-
-void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
-void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
-void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
+ TCGArg, MemOp);
+
+void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+
+void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+
+void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
+void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
+void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8d23fb0..0dff196 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2056,7 +2056,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
case INDEX_op_qemu_st_i64:
{
TCGMemOpIdx oi = op->args[k++];
- TCGMemOp op = get_memop(oi);
+ MemOp op = get_memop(oi);
unsigned ix = get_mmuidx(oi);
if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 529acb2..a37181c 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -26,6 +26,7 @@
#define TCG_H
#include "cpu.h"
+#include "exec/memop.h"
#include "exec/tb-context.h"
#include "qemu/bitops.h"
#include "qemu/queue.h"
@@ -309,103 +310,13 @@ typedef enum TCGType {
#endif
} TCGType;
-/* Constants for qemu_ld and qemu_st for the Memory Operation field. */
-typedef enum TCGMemOp {
- MO_8 = 0,
- MO_16 = 1,
- MO_32 = 2,
- MO_64 = 3,
- MO_SIZE = 3, /* Mask for the above. */
-
- MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
-
- MO_BSWAP = 8, /* Host reverse endian. */
-#ifdef HOST_WORDS_BIGENDIAN
- MO_LE = MO_BSWAP,
- MO_BE = 0,
-#else
- MO_LE = 0,
- MO_BE = MO_BSWAP,
-#endif
-#ifdef TARGET_WORDS_BIGENDIAN
- MO_TE = MO_BE,
-#else
- MO_TE = MO_LE,
-#endif
-
- /*
- * MO_UNALN accesses are never checked for alignment.
- * MO_ALIGN accesses will result in a call to the CPU's
- * do_unaligned_access hook if the guest address is not aligned.
- * The default depends on whether the target CPU defines
- * TARGET_ALIGNED_ONLY.
- *
- * Some architectures (e.g. ARMv8) need the address which is aligned
- * to a size more than the size of the memory access.
- * Some architectures (e.g. SPARCv9) need an address which is aligned,
- * but less strictly than the natural alignment.
- *
- * MO_ALIGN supposes the alignment size is the size of a memory access.
- *
- * There are three options:
- * - unaligned access permitted (MO_UNALN).
- * - an alignment to the size of an access (MO_ALIGN);
- * - an alignment to a specified size, which may be more or less than
- * the access size (MO_ALIGN_x where 'x' is a size in bytes);
- */
- MO_ASHIFT = 4,
- MO_AMASK = 7 << MO_ASHIFT,
-#ifdef TARGET_ALIGNED_ONLY
- MO_ALIGN = 0,
- MO_UNALN = MO_AMASK,
-#else
- MO_ALIGN = MO_AMASK,
- MO_UNALN = 0,
-#endif
- MO_ALIGN_2 = 1 << MO_ASHIFT,
- MO_ALIGN_4 = 2 << MO_ASHIFT,
- MO_ALIGN_8 = 3 << MO_ASHIFT,
- MO_ALIGN_16 = 4 << MO_ASHIFT,
- MO_ALIGN_32 = 5 << MO_ASHIFT,
- MO_ALIGN_64 = 6 << MO_ASHIFT,
-
- /* Combinations of the above, for ease of use. */
- MO_UB = MO_8,
- MO_UW = MO_16,
- MO_UL = MO_32,
- MO_SB = MO_SIGN | MO_8,
- MO_SW = MO_SIGN | MO_16,
- MO_SL = MO_SIGN | MO_32,
- MO_Q = MO_64,
-
- MO_LEUW = MO_LE | MO_UW,
- MO_LEUL = MO_LE | MO_UL,
- MO_LESW = MO_LE | MO_SW,
- MO_LESL = MO_LE | MO_SL,
- MO_LEQ = MO_LE | MO_Q,
-
- MO_BEUW = MO_BE | MO_UW,
- MO_BEUL = MO_BE | MO_UL,
- MO_BESW = MO_BE | MO_SW,
- MO_BESL = MO_BE | MO_SL,
- MO_BEQ = MO_BE | MO_Q,
-
- MO_TEUW = MO_TE | MO_UW,
- MO_TEUL = MO_TE | MO_UL,
- MO_TESW = MO_TE | MO_SW,
- MO_TESL = MO_TE | MO_SL,
- MO_TEQ = MO_TE | MO_Q,
-
- MO_SSIZE = MO_SIZE | MO_SIGN,
-} TCGMemOp;
-
/**
* get_alignment_bits
- * @memop: TCGMemOp value
+ * @memop: MemOp value
*
* Extract the alignment size from the memop.
*/
-static inline unsigned get_alignment_bits(TCGMemOp memop)
+static inline unsigned get_alignment_bits(MemOp memop)
{
unsigned a = memop & MO_AMASK;
@@ -1186,7 +1097,7 @@ static inline size_t tcg_current_code_size(TCGContext *s)
return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
}
-/* Combine the TCGMemOp and mmu_idx parameters into a single value. */
+/* Combine the MemOp and mmu_idx parameters into a single value. */
typedef uint32_t TCGMemOpIdx;
/**
@@ -1196,7 +1107,7 @@ typedef uint32_t TCGMemOpIdx;
*
* Encode these values into a single parameter.
*/
-static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
+static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
{
tcg_debug_assert(idx <= 15);
return (op << 4) | idx;
@@ -1208,7 +1119,7 @@ static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
*
* Extract the memory operation from the combined value.
*/
-static inline TCGMemOp get_memop(TCGMemOpIdx oi)
+static inline MemOp get_memop(TCGMemOpIdx oi)
{
return oi >> 4;
}
diff --git a/trace/mem-internal.h b/trace/mem-internal.h
index f6efaf6..3444fbc 100644
--- a/trace/mem-internal.h
+++ b/trace/mem-internal.h
@@ -16,7 +16,7 @@
#define TRACE_MEM_ST (1ULL << 5) /* store (y/n) */
static inline uint8_t trace_mem_build_info(
- int size_shift, bool sign_extend, TCGMemOp endianness, bool store)
+ int size_shift, bool sign_extend, MemOp endianness, bool store)
{
uint8_t res;
@@ -33,7 +33,7 @@ static inline uint8_t trace_mem_build_info(
return res;
}
-static inline uint8_t trace_mem_get_info(TCGMemOp op, bool store)
+static inline uint8_t trace_mem_get_info(MemOp op, bool store)
{
return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN),
op & MO_BSWAP, store);
diff --git a/trace/mem.h b/trace/mem.h
index 2b58196..8cf213d 100644
--- a/trace/mem.h
+++ b/trace/mem.h
@@ -18,7 +18,7 @@
*
* Return a value for the 'info' argument in guest memory access traces.
*/
-static uint8_t trace_mem_get_info(TCGMemOp op, bool store);
+static uint8_t trace_mem_get_info(MemOp op, bool store);
/**
* trace_mem_build_info:
@@ -26,7 +26,7 @@ static uint8_t trace_mem_get_info(TCGMemOp op, bool store);
* Return a value for the 'info' argument in guest memory access traces.
*/
static uint8_t trace_mem_build_info(int size_shift, bool sign_extend,
- TCGMemOp endianness, bool store);
+ MemOp endianness, bool store);
#include "trace/mem-internal.h"
--
1.8.3.1
?
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* [Xen-devel] [Qemu-devel] [PATCH v7 03/42] memory: Introduce size_memop
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
2019-08-16 7:08 ` [Xen-devel] [Qemu-devel] [PATCH v7 01/42] configure: Define TARGET_ALIGNED_ONLY tony.nguyen
2019-08-16 7:26 ` [Xen-devel] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen
@ 2019-08-16 7:27 ` tony.nguyen
2019-08-16 7:27 ` [Xen-devel] [Qemu-devel] [PATCH v7 04/42] target/mips: Access MemoryRegion with MemOp tony.nguyen
` (40 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:27 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1009 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Introduce no-op size_memop to aid preparatory conversion of
interfaces.
Once interfaces are converted, size_memop will be implemented to
return a MemOp from size in bytes.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memop.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 7262ca3..dfd76a1 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -107,4 +107,14 @@ typedef enum MemOp {
MO_SSIZE = MO_SIZE | MO_SIGN,
} MemOp;
+/* Size in bytes to MemOp. */
+static inline unsigned size_memop(unsigned size)
+{
+ /*
+ * FIXME: No-op to aid conversion of memory_region_dispatch_{read|write}
+ * "unsigned size" operand into a "MemOp op".
+ */
+ return size;
+}
+
#endif
--
1.8.3.1
?
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 04/42] target/mips: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (2 preceding siblings ...)
2019-08-16 7:27 ` [Xen-devel] [Qemu-devel] [PATCH v7 03/42] memory: Introduce size_memop tony.nguyen
@ 2019-08-16 7:27 ` tony.nguyen
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 05/42] hw/s390x: " tony.nguyen
` (39 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:27 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1757 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".
As size_memop is a no-op, this patch does not change any behaviour.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 9e2e02f..1c72a00 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -24,6 +24,7 @@
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "exec/memop.h"
#include "sysemu/kvm.h"
/*****************************************************************************/
@@ -4740,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
if (op == 9) {
/* Index Store Tag */
memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
- 8, MEMTXATTRS_UNSPECIFIED);
+ size_memop(8), MEMTXATTRS_UNSPECIFIED);
} else if (op == 5) {
/* Index Load Tag */
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
- 8, MEMTXATTRS_UNSPECIFIED);
+ size_memop(8), MEMTXATTRS_UNSPECIFIED);
}
#endif
}
--
1.8.3.1
?
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 05/42] hw/s390x: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (3 preceding siblings ...)
2019-08-16 7:27 ` [Xen-devel] [Qemu-devel] [PATCH v7 04/42] target/mips: Access MemoryRegion with MemOp tony.nguyen
@ 2019-08-16 7:28 ` tony.nguyen
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 06/42] hw/intc/armv7m_nic: " tony.nguyen
` (38 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:28 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2513 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".
As size_memop is a no-op, this patch does not change any behaviour.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
---
hw/s390x/s390-pci-inst.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0023514..0c958fc 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -15,6 +15,7 @@
#include "cpu.h"
#include "s390-pci-inst.h"
#include "s390-pci-bus.h"
+#include "exec/memop.h"
#include "exec/memory-internal.h"
#include "qemu/error-report.h"
#include "sysemu/hw_accel.h"
@@ -372,7 +373,7 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
mr = pbdev->pdev->io_regions[pcias].memory;
mr = s390_get_subregion(mr, offset, len);
offset -= mr->addr;
- return memory_region_dispatch_read(mr, offset, data, len,
+ return memory_region_dispatch_read(mr, offset, data, size_memop(len),
MEMTXATTRS_UNSPECIFIED);
}
@@ -471,7 +472,7 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
mr = pbdev->pdev->io_regions[pcias].memory;
mr = s390_get_subregion(mr, offset, len);
offset -= mr->addr;
- return memory_region_dispatch_write(mr, offset, data, len,
+ return memory_region_dispatch_write(mr, offset, data, size_memop(len),
MEMTXATTRS_UNSPECIFIED);
}
@@ -780,7 +781,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
for (i = 0; i < len / 8; i++) {
result = memory_region_dispatch_write(mr, offset + i * 8,
- ldq_p(buffer + i * 8), 8,
+ ldq_p(buffer + i * 8),
+ size_memop(8),
MEMTXATTRS_UNSPECIFIED);
if (result != MEMTX_OK) {
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
--
1.8.3.1
?
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 06/42] hw/intc/armv7m_nic: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (4 preceding siblings ...)
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 05/42] hw/s390x: " tony.nguyen
@ 2019-08-16 7:28 ` tony.nguyen
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 07/42] hw/virtio: " tony.nguyen
` (37 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:28 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 3082 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".
As size_memop is a no-op, this patch does not change any behaviour.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/intc/armv7m_nvic.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 9f8f0d3..237ccef 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -18,6 +18,7 @@
#include "hw/intc/armv7m_nvic.h"
#include "target/arm/cpu.h"
#include "exec/exec-all.h"
+#include "exec/memop.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"
@@ -2345,7 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
if (attrs.secure) {
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
- return memory_region_dispatch_write(mr, addr, value, size, attrs);
+ return memory_region_dispatch_write(mr, addr, value, size_memop(size),
+ attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@@ -2364,7 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
if (attrs.secure) {
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
- return memory_region_dispatch_read(mr, addr, data, size, attrs);
+ return memory_region_dispatch_read(mr, addr, data, size_memop(size),
+ attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@@ -2390,7 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
/* Direct the access to the correct systick */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
- return memory_region_dispatch_write(mr, addr, value, size, attrs);
+ return memory_region_dispatch_write(mr, addr, value, size_memop(size),
+ attrs);
}
static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
@@ -2402,7 +2406,7 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
/* Direct the access to the correct systick */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
- return memory_region_dispatch_read(mr, addr, data, size, attrs);
+ return memory_region_dispatch_read(mr, addr, data, size_memop(size), attrs);
}
static const MemoryRegionOps nvic_systick_ops = {
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 5560 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 07/42] hw/virtio: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (5 preceding siblings ...)
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 06/42] hw/intc/armv7m_nic: " tony.nguyen
@ 2019-08-16 7:28 ` tony.nguyen
2019-08-16 7:29 ` [Xen-devel] [Qemu-devel] [PATCH v7 08/42] hw/vfio: " tony.nguyen
` (36 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:28 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1884 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".
As size_memop is a no-op, this patch does not change any behaviour.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
---
hw/virtio/virtio-pci.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index f6d2223..25875c8 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -17,6 +17,7 @@
#include "qemu/osdep.h"
+#include "exec/memop.h"
#include "standard-headers/linux/virtio_pci.h"
#include "hw/virtio/virtio.h"
#include "hw/pci/pci.h"
@@ -550,7 +551,8 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
/* As length is under guest control, handle illegal values. */
return;
}
- memory_region_dispatch_write(mr, addr, val, len, MEMTXATTRS_UNSPECIFIED);
+ memory_region_dispatch_write(mr, addr, val, size_memop(len),
+ MEMTXATTRS_UNSPECIFIED);
}
static void
@@ -573,7 +575,8 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
/* Make sure caller aligned buf properly */
assert(!(((uintptr_t)buf) & (len - 1)));
- memory_region_dispatch_read(mr, addr, &val, len, MEMTXATTRS_UNSPECIFIED);
+ memory_region_dispatch_read(mr, addr, &val, size_memop(len),
+ MEMTXATTRS_UNSPECIFIED);
switch (len) {
case 1:
pci_set_byte(buf, val);
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 3674 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 08/42] hw/vfio: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (6 preceding siblings ...)
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 07/42] hw/virtio: " tony.nguyen
@ 2019-08-16 7:29 ` tony.nguyen
2019-08-16 7:29 ` [Xen-devel] [Qemu-devel] [PATCH v7 09/42] exec: " tony.nguyen
` (35 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:29 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2101 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".
As size_memop is a no-op, this patch does not change any behaviour.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
---
hw/vfio/pci-quirks.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index b35a640..fb3cc33 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -11,6 +11,7 @@
*/
#include "qemu/osdep.h"
+#include "exec/memop.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
@@ -1071,7 +1072,7 @@ static void vfio_rtl8168_quirk_address_write(void *opaque, hwaddr addr,
/* Write to the proper guest MSI-X table instead */
memory_region_dispatch_write(&vdev->pdev.msix_table_mmio,
- offset, val, size,
+ offset, val, size_memop(size),
MEMTXATTRS_UNSPECIFIED);
}
return; /* Do not write guest MSI-X data to hardware */
@@ -1102,7 +1103,8 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *opaque,
if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) {
hwaddr offset = rtl->addr & 0xfff;
memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset,
- &data, size, MEMTXATTRS_UNSPECIFIED);
+ &data, size_memop(size),
+ MEMTXATTRS_UNSPECIFIED);
trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data);
}
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 4419 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 09/42] exec: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (7 preceding siblings ...)
2019-08-16 7:29 ` [Xen-devel] [Qemu-devel] [PATCH v7 08/42] hw/vfio: " tony.nguyen
@ 2019-08-16 7:29 ` tony.nguyen
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 10/42] cputlb: " tony.nguyen
` (34 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:29 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 5872 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".
As size_memop is a no-op, this patch does not change any behaviour.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
exec.c | 6 ++++--
memory_ldst.inc.c | 18 +++++++++---------
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/exec.c b/exec.c
index 3e78de3..9f69197 100644
--- a/exec.c
+++ b/exec.c
@@ -3334,7 +3334,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
/* XXX: could force current_cpu to NULL to avoid
potential bugs */
val = ldn_p(buf, l);
- result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
+ result |= memory_region_dispatch_write(mr, addr1, val,
+ size_memop(l), attrs);
} else {
/* RAM case */
ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
@@ -3395,7 +3396,8 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
/* I/O case */
release_lock |= prepare_mmio_access(mr);
l = memory_access_size(mr, l, addr1);
- result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
+ result |= memory_region_dispatch_read(mr, addr1, &val,
+ size_memop(l), attrs);
stn_p(buf, l, val);
} else {
/* RAM case */
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index acf865b..1e8a2fc 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -38,7 +38,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(4), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
@@ -114,7 +114,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(8), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap64(val);
@@ -188,7 +188,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(1), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -224,7 +224,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(2), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
@@ -300,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
if (l < 4 || !memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(4), attrs);
} else {
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
stl_p(ptr, val);
@@ -346,7 +346,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
val = bswap32(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(4), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -408,7 +408,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (!memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(1), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -451,7 +451,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
val = bswap16(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 2, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(2), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -524,7 +524,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
val = bswap64(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 8, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(8), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 10518 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 10/42] cputlb: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (8 preceding siblings ...)
2019-08-16 7:29 ` [Xen-devel] [Qemu-devel] [PATCH v7 09/42] exec: " tony.nguyen
@ 2019-08-16 7:30 ` tony.nguyen
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 11/42] memory: " tony.nguyen
` (33 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:30 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1901 bytes --]
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".
As size_memop is a no-op, this patch does not change any behaviour.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 523be4c..6c83878 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -906,8 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_read(mr, mr_offset,
- &val, size, iotlbentry->attrs);
+ r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),
+ iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
section->offset_within_address_space -
@@ -947,8 +947,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_write(mr, mr_offset,
- val, size, iotlbentry->attrs);
+ r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
+ iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
section->offset_within_address_space -
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 3861 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 11/42] memory: Access MemoryRegion with MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (9 preceding siblings ...)
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 10/42] cputlb: " tony.nguyen
@ 2019-08-16 7:30 ` tony.nguyen
2019-08-18 21:44 ` Philippe Mathieu-Daudé
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 12/42] hw/s390x: Hard code size with MO_{8|16|32|64} tony.nguyen
` (32 subsequent siblings)
43 siblings, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:30 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 4608 bytes --]
Convert memory_region_dispatch_{read|write} operand "unsigned size"
into a "MemOp op".
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memop.h | 20 ++++++++++++++------
include/exec/memory.h | 9 +++++----
memory.c | 7 +++++--
3 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index dfd76a1..0a610b7 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -12,6 +12,8 @@
#ifndef MEMOP_H
#define MEMOP_H
+#include "qemu/host-utils.h"
+
typedef enum MemOp {
MO_8 = 0,
MO_16 = 1,
@@ -107,14 +109,20 @@ typedef enum MemOp {
MO_SSIZE = MO_SIZE | MO_SIGN,
} MemOp;
+/* MemOp to size in bytes. */
+static inline unsigned memop_size(MemOp op)
+{
+ return 1 << (op & MO_SIZE);
+}
+
/* Size in bytes to MemOp. */
-static inline unsigned size_memop(unsigned size)
+static inline MemOp size_memop(unsigned size)
{
- /*
- * FIXME: No-op to aid conversion of memory_region_dispatch_{read|write}
- * "unsigned size" operand into a "MemOp op".
- */
- return size;
+#ifdef CONFIG_DEBUG_TCG
+ /* Power of 2 up to 8. */
+ assert((size & (size - 1)) == 0 && size >= 1 && size <= 8);
+#endif
+ return ctz32(size);
}
#endif
diff --git a/include/exec/memory.h b/include/exec/memory.h
index bb0961d..975b86a 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -19,6 +19,7 @@
#include "exec/cpu-common.h"
#include "exec/hwaddr.h"
#include "exec/memattrs.h"
+#include "exec/memop.h"
#include "exec/ramlist.h"
#include "qemu/queue.h"
#include "qemu/int128.h"
@@ -1731,13 +1732,13 @@ void mtree_info(bool flatview, bool dispatch_tree, bool owner);
* @mr: #MemoryRegion to access
* @addr: address within that region
* @pval: pointer to uint64_t which the data is written to
- * @size: size of the access in bytes
+ * @op: size, sign, and endianness of the memory operation
* @attrs: memory transaction attributes to use for the access
*/
MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
hwaddr addr,
uint64_t *pval,
- unsigned size,
+ MemOp op,
MemTxAttrs attrs);
/**
* memory_region_dispatch_write: perform a write directly to the specified
@@ -1746,13 +1747,13 @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
* @mr: #MemoryRegion to access
* @addr: address within that region
* @data: data to write
- * @size: size of the access in bytes
+ * @op: size, sign, and endianness of the memory operation
* @attrs: memory transaction attributes to use for the access
*/
MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
hwaddr addr,
uint64_t data,
- unsigned size,
+ MemOp op,
MemTxAttrs attrs);
/**
diff --git a/memory.c b/memory.c
index 5d8c9a9..89ea4fb 100644
--- a/memory.c
+++ b/memory.c
@@ -1439,9 +1439,10 @@ static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
hwaddr addr,
uint64_t *pval,
- unsigned size,
+ MemOp op,
MemTxAttrs attrs)
{
+ unsigned size = memop_size(op);
MemTxResult r;
if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
@@ -1483,9 +1484,11 @@ static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
hwaddr addr,
uint64_t data,
- unsigned size,
+ MemOp op,
MemTxAttrs attrs)
{
+ unsigned size = memop_size(op);
+
if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
unassigned_mem_write(mr, addr, data, size);
return MEMTX_DECODE_ERROR;
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 9630 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 12/42] hw/s390x: Hard code size with MO_{8|16|32|64}
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (10 preceding siblings ...)
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 11/42] memory: " tony.nguyen
@ 2019-08-16 7:30 ` tony.nguyen
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 13/42] target/mips: " tony.nguyen
` (31 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:30 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1334 bytes --]
Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".
Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoids size_memop calls.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
---
hw/s390x/s390-pci-inst.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0c958fc..0e92a37 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -782,8 +782,7 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
for (i = 0; i < len / 8; i++) {
result = memory_region_dispatch_write(mr, offset + i * 8,
ldq_p(buffer + i * 8),
- size_memop(8),
- MEMTXATTRS_UNSPECIFIED);
+ MO_64, MEMTXATTRS_UNSPECIFIED);
if (result != MEMTX_OK) {
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
return 0;
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 3093 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 13/42] target/mips: Hard code size with MO_{8|16|32|64}
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (11 preceding siblings ...)
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 12/42] hw/s390x: Hard code size with MO_{8|16|32|64} tony.nguyen
@ 2019-08-16 7:31 ` tony.nguyen
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 14/42] exec: " tony.nguyen
` (30 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:31 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1345 bytes --]
Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".
Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoids size_memop calls.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 1c72a00..e79f99d 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
if (op == 9) {
/* Index Store Tag */
memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
- size_memop(8), MEMTXATTRS_UNSPECIFIED);
+ MO_64, MEMTXATTRS_UNSPECIFIED);
} else if (op == 5) {
/* Index Load Tag */
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
- size_memop(8), MEMTXATTRS_UNSPECIFIED);
+ MO_64, MEMTXATTRS_UNSPECIFIED);
}
#endif
}
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 2957 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 14/42] exec: Hard code size with MO_{8|16|32|64}
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (12 preceding siblings ...)
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 13/42] target/mips: " tony.nguyen
@ 2019-08-16 7:31 ` tony.nguyen
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 15/42] hw/audio: Declare device little or big endian tony.nguyen
` (29 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:31 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 4509 bytes --]
Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".
Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoids size_memop calls.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
memory_ldst.inc.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index 1e8a2fc..de658c4 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -38,7 +38,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, size_memop(4), attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
@@ -114,7 +114,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, size_memop(8), attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap64(val);
@@ -188,7 +188,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, size_memop(1), attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -224,7 +224,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, size_memop(2), attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
@@ -300,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
if (l < 4 || !memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, size_memop(4), attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
} else {
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
stl_p(ptr, val);
@@ -346,7 +346,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
val = bswap32(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, size_memop(4), attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -408,7 +408,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (!memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, size_memop(1), attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -451,7 +451,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
val = bswap16(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, size_memop(2), attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, MO_16, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -524,7 +524,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
val = bswap64(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, size_memop(8), attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, MO_64, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 8035 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 15/42] hw/audio: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (13 preceding siblings ...)
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 14/42] exec: " tony.nguyen
@ 2019-08-16 7:31 ` tony.nguyen
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 16/42] hw/block: " tony.nguyen
` (28 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:31 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2708 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/audio/cs4231.c | 2 +-
hw/audio/marvell_88w8618.c | 2 +-
hw/audio/milkymist-ac97.c | 2 +-
hw/audio/pl041.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/audio/cs4231.c b/hw/audio/cs4231.c
index 8372299..8946648 100644
--- a/hw/audio/cs4231.c
+++ b/hw/audio/cs4231.c
@@ -132,7 +132,7 @@ static void cs_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps cs_mem_ops = {
.read = cs_mem_read,
.write = cs_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static const VMStateDescription vmstate_cs4231 = {
diff --git a/hw/audio/marvell_88w8618.c b/hw/audio/marvell_88w8618.c
index ff1a0d0..a79e0b1 100644
--- a/hw/audio/marvell_88w8618.c
+++ b/hw/audio/marvell_88w8618.c
@@ -240,7 +240,7 @@ static void mv88w8618_audio_reset(DeviceState *d)
static const MemoryRegionOps mv88w8618_audio_ops = {
.read = mv88w8618_audio_read,
.write = mv88w8618_audio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void mv88w8618_audio_init(Object *obj)
diff --git a/hw/audio/milkymist-ac97.c b/hw/audio/milkymist-ac97.c
index bf6a5a6..56feca2 100644
--- a/hw/audio/milkymist-ac97.c
+++ b/hw/audio/milkymist-ac97.c
@@ -176,7 +176,7 @@ static const MemoryRegionOps ac97_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static void ac97_in_cb(void *opaque, int avail_b)
diff --git a/hw/audio/pl041.c b/hw/audio/pl041.c
index 59c6ce1..b59a4f8 100644
--- a/hw/audio/pl041.c
+++ b/hw/audio/pl041.c
@@ -519,7 +519,7 @@ static void pl041_device_reset(DeviceState *d)
static const MemoryRegionOps pl041_ops = {
.read = pl041_read,
.write = pl041_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl041_init(Object *obj)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 4801 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 16/42] hw/block: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (14 preceding siblings ...)
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 15/42] hw/audio: Declare device little or big endian tony.nguyen
@ 2019-08-16 7:32 ` tony.nguyen
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 17/42] hw/char: " tony.nguyen
` (27 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:32 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1230 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/block/onenand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/onenand.c b/hw/block/onenand.c
index b3644f7..66152e7 100644
--- a/hw/block/onenand.c
+++ b/hw/block/onenand.c
@@ -769,7 +769,7 @@ static void onenand_write(void *opaque, hwaddr addr,
static const MemoryRegionOps onenand_ops = {
.read = onenand_read,
.write = onenand_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void onenand_realize(DeviceState *dev, Error **errp)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 2476 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 17/42] hw/char: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (15 preceding siblings ...)
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 16/42] hw/block: " tony.nguyen
@ 2019-08-16 7:32 ` tony.nguyen
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 18/42] hw/display: " tony.nguyen
` (26 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:32 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 4788 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/char/cadence_uart.c | 2 +-
hw/char/escc.c | 2 +-
hw/char/etraxfs_ser.c | 2 +-
hw/char/grlib_apbuart.c | 2 +-
hw/char/imx_serial.c | 2 +-
hw/char/lm32_uart.c | 2 +-
hw/char/milkymist-uart.c | 2 +-
hw/char/pl011.c | 2 +-
8 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index fa25fe2..6c7b904 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -457,7 +457,7 @@ static uint64_t uart_read(void *opaque, hwaddr offset,
static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void cadence_uart_reset(DeviceState *dev)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 8ddbb4b..36182d9 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -574,7 +574,7 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr,
static const MemoryRegionOps escc_mem_ops = {
.read = escc_mem_read,
.write = escc_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c
index 9745bca..cda687b 100644
--- a/hw/char/etraxfs_ser.c
+++ b/hw/char/etraxfs_ser.c
@@ -155,7 +155,7 @@ ser_write(void *opaque, hwaddr addr,
static const MemoryRegionOps ser_ops = {
.read = ser_read,
.write = ser_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c
index c2bb3ac..119fc84 100644
--- a/hw/char/grlib_apbuart.c
+++ b/hw/char/grlib_apbuart.c
@@ -237,7 +237,7 @@ static void grlib_apbuart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps grlib_apbuart_ops = {
.write = grlib_apbuart_write,
.read = grlib_apbuart_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static void grlib_apbuart_realize(DeviceState *dev, Error **errp)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 0655a95..7c66551 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -332,7 +332,7 @@ static void imx_event(void *opaque, int event)
static const struct MemoryRegionOps imx_serial_ops = {
.read = imx_serial_read,
.write = imx_serial_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void imx_serial_realize(DeviceState *dev, Error **errp)
diff --git a/hw/char/lm32_uart.c b/hw/char/lm32_uart.c
index d047a44..2fe5f60 100644
--- a/hw/char/lm32_uart.c
+++ b/hw/char/lm32_uart.c
@@ -205,7 +205,7 @@ static void uart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
diff --git a/hw/char/milkymist-uart.c b/hw/char/milkymist-uart.c
index 8a78fcc..bdb8282 100644
--- a/hw/char/milkymist-uart.c
+++ b/hw/char/milkymist-uart.c
@@ -156,7 +156,7 @@ static const MemoryRegionOps uart_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index c1ae2f3..5fb95d2 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -287,7 +287,7 @@ static void pl011_event(void *opaque, int event)
static const MemoryRegionOps pl011_ops = {
.read = pl011_read,
.write = pl011_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_pl011 = {
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 8114 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 18/42] hw/display: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (16 preceding siblings ...)
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 17/42] hw/char: " tony.nguyen
@ 2019-08-16 7:32 ` tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 19/42] hw/dma: " tony.nguyen
` (25 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:32 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1823 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/display/pl110.c | 2 +-
hw/display/tc6393xb.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/display/pl110.c b/hw/display/pl110.c
index 2bdfc3c..d0c6317 100644
--- a/hw/display/pl110.c
+++ b/hw/display/pl110.c
@@ -471,7 +471,7 @@ static void pl110_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pl110_ops = {
.read = pl110_read,
.write = pl110_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl110_mux_ctrl_set(void *opaque, int line, int level)
diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c
index 0b7c59c..6bc3360 100644
--- a/hw/display/tc6393xb.c
+++ b/hw/display/tc6393xb.c
@@ -547,7 +547,7 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
static const MemoryRegionOps tc6393xb_ops = {
.read = tc6393xb_readb,
.write = tc6393xb_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 3332 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 19/42] hw/dma: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (17 preceding siblings ...)
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 18/42] hw/display: " tony.nguyen
@ 2019-08-16 7:33 ` tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 20/42] hw/gpio: " tony.nguyen
` (24 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:33 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 4041 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/dma/bcm2835_dma.c | 4 ++--
hw/dma/etraxfs_dma.c | 2 +-
hw/dma/pl080.c | 2 +-
hw/dma/pl330.c | 2 +-
hw/dma/puv3_dma.c | 2 +-
hw/dma/sparc32_dma.c | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c
index a39e8f4..907d25c 100644
--- a/hw/dma/bcm2835_dma.c
+++ b/hw/dma/bcm2835_dma.c
@@ -288,7 +288,7 @@ static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps bcm2835_dma0_ops = {
.read = bcm2835_dma0_read,
.write = bcm2835_dma0_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -296,7 +296,7 @@ static const MemoryRegionOps bcm2835_dma0_ops = {
static const MemoryRegionOps bcm2835_dma15_ops = {
.read = bcm2835_dma15_read,
.write = bcm2835_dma15_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c
index 85783eb..df3ba09 100644
--- a/hw/dma/etraxfs_dma.c
+++ b/hw/dma/etraxfs_dma.c
@@ -697,7 +697,7 @@ dma_write(void *opaque, hwaddr addr,
static const MemoryRegionOps dma_ops = {
.read = dma_read,
.write = dma_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 4
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 7e57624..644eadb 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -346,7 +346,7 @@ static void pl080_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pl080_ops = {
.read = pl080_read,
.write = pl080_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl080_reset(DeviceState *dev)
diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c
index a56a3e7..4c51f2d 100644
--- a/hw/dma/pl330.c
+++ b/hw/dma/pl330.c
@@ -1493,7 +1493,7 @@ static uint64_t pl330_iomem_read(void *opaque, hwaddr offset,
static const MemoryRegionOps pl330_ops = {
.read = pl330_iomem_read,
.write = pl330_iomem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
diff --git a/hw/dma/puv3_dma.c b/hw/dma/puv3_dma.c
index 122f87a..7002373 100644
--- a/hw/dma/puv3_dma.c
+++ b/hw/dma/puv3_dma.c
@@ -75,7 +75,7 @@ static const MemoryRegionOps puv3_dma_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void puv3_dma_realize(DeviceState *dev, Error **errp)
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index 88765d0..6b32372 100644
--- a/hw/dma/sparc32_dma.c
+++ b/hw/dma/sparc32_dma.c
@@ -224,7 +224,7 @@ static void dma_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps dma_mem_ops = {
.read = dma_mem_read,
.write = dma_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 7194 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 20/42] hw/gpio: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (18 preceding siblings ...)
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 19/42] hw/dma: " tony.nguyen
@ 2019-08-16 7:33 ` tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 21/42] hw/i2c: " tony.nguyen
` (23 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:33 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1687 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/gpio/pl061.c | 2 +-
hw/gpio/zaurus.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index 02c01fd..da6ff6a 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -339,7 +339,7 @@ static void pl061_set_irq(void * opaque, int irq, int level)
static const MemoryRegionOps pl061_ops = {
.read = pl061_read,
.write = pl061_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl061_luminary_init(Object *obj)
diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c
index f2f1f67..599d862 100644
--- a/hw/gpio/zaurus.c
+++ b/hw/gpio/zaurus.c
@@ -156,7 +156,7 @@ static void scoop_write(void *opaque, hwaddr addr,
static const MemoryRegionOps scoop_ops = {
.read = scoop_read,
.write = scoop_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void scoop_gpio_set(void *opaque, int line, int level)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 3192 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 21/42] hw/i2c: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (19 preceding siblings ...)
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 20/42] hw/gpio: " tony.nguyen
@ 2019-08-16 7:33 ` tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 22/42] hw/input: " tony.nguyen
` (22 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:33 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2190 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/i2c/imx_i2c.c | 2 +-
hw/i2c/mpc_i2c.c | 2 +-
hw/i2c/versatile_i2c.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index ce7a94c..de1107b 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -276,7 +276,7 @@ static const MemoryRegionOps imx_i2c_ops = {
.write = imx_i2c_write,
.valid.min_access_size = 1,
.valid.max_access_size = 2,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription imx_i2c_vmstate = {
diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c
index e9a1127..181228d 100644
--- a/hw/i2c/mpc_i2c.c
+++ b/hw/i2c/mpc_i2c.c
@@ -304,7 +304,7 @@ static const MemoryRegionOps i2c_ops = {
.read = mpc_i2c_read,
.write = mpc_i2c_write,
.valid.max_access_size = 1,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static const VMStateDescription mpc_i2c_vmstate = {
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index 1ac2a6f..c92d3b1 100644
--- a/hw/i2c/versatile_i2c.c
+++ b/hw/i2c/versatile_i2c.c
@@ -77,7 +77,7 @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
static const MemoryRegionOps versatile_i2c_ops = {
.read = versatile_i2c_read,
.write = versatile_i2c_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void versatile_i2c_init(Object *obj)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 3874 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 22/42] hw/input: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (20 preceding siblings ...)
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 21/42] hw/i2c: " tony.nguyen
@ 2019-08-16 7:33 ` tony.nguyen
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 23/42] hw/intc: " tony.nguyen
` (21 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:33 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1212 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/input/pl050.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/input/pl050.c b/hw/input/pl050.c
index b79bf16..4c0fe0b 100644
--- a/hw/input/pl050.c
+++ b/hw/input/pl050.c
@@ -137,7 +137,7 @@ static void pl050_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pl050_ops = {
.read = pl050_read,
.write = pl050_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl050_realize(DeviceState *dev, Error **errp)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 2458 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 23/42] hw/intc: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (21 preceding siblings ...)
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 22/42] hw/input: " tony.nguyen
@ 2019-08-16 7:34 ` tony.nguyen
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 24/42] hw/isa: " tony.nguyen
` (20 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:34 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 5523 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/intc/arm_gic.c | 12 ++++++------
hw/intc/arm_gicv3.c | 4 ++--
hw/intc/etraxfs_pic.c | 2 +-
hw/intc/imx_avic.c | 2 +-
hw/intc/imx_gpcv2.c | 2 +-
hw/intc/pl190.c | 2 +-
hw/intc/puv3_intc.c | 2 +-
7 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 77427a4..283a63a 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1999,38 +1999,38 @@ static const MemoryRegionOps gic_ops[2] = {
{
.read_with_attrs = gic_dist_read,
.write_with_attrs = gic_dist_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
},
{
.read_with_attrs = gic_thiscpu_read,
.write_with_attrs = gic_thiscpu_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
}
};
static const MemoryRegionOps gic_cpu_ops = {
.read_with_attrs = gic_do_cpu_read,
.write_with_attrs = gic_do_cpu_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps gic_virt_ops[2] = {
{
.read_with_attrs = gic_thiscpu_hyp_read,
.write_with_attrs = gic_thiscpu_hyp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
},
{
.read_with_attrs = gic_thisvcpu_read,
.write_with_attrs = gic_thisvcpu_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
}
};
static const MemoryRegionOps gic_viface_ops = {
.read_with_attrs = gic_do_hyp_read,
.write_with_attrs = gic_do_hyp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void arm_gic_realize(DeviceState *dev, Error **errp)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index 66eaa97..9b4d5ba 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -352,12 +352,12 @@ static const MemoryRegionOps gic_ops[] = {
{
.read_with_attrs = gicv3_dist_read,
.write_with_attrs = gicv3_dist_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
},
{
.read_with_attrs = gicv3_redist_read,
.write_with_attrs = gicv3_redist_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
}
};
diff --git a/hw/intc/etraxfs_pic.c b/hw/intc/etraxfs_pic.c
index 20e1391..d4a27d1 100644
--- a/hw/intc/etraxfs_pic.c
+++ b/hw/intc/etraxfs_pic.c
@@ -111,7 +111,7 @@ static void pic_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pic_ops = {
.read = pic_read,
.write = pic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/intc/imx_avic.c b/hw/intc/imx_avic.c
index 83a4101..4bef842 100644
--- a/hw/intc/imx_avic.c
+++ b/hw/intc/imx_avic.c
@@ -308,7 +308,7 @@ static void imx_avic_write(void *opaque, hwaddr offset,
static const MemoryRegionOps imx_avic_ops = {
.read = imx_avic_read,
.write = imx_avic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void imx_avic_reset(DeviceState *dev)
diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c
index a83333b..f37e6b5 100644
--- a/hw/intc/imx_gpcv2.c
+++ b/hw/intc/imx_gpcv2.c
@@ -64,7 +64,7 @@ static void imx_gpcv2_write(void *opaque, hwaddr offset,
static const struct MemoryRegionOps imx_gpcv2_ops = {
.read = imx_gpcv2_read,
.write = imx_gpcv2_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
/*
* Our device would not work correctly if the guest was doing
diff --git a/hw/intc/pl190.c b/hw/intc/pl190.c
index b4f31ef..e6eab1e 100644
--- a/hw/intc/pl190.c
+++ b/hw/intc/pl190.c
@@ -220,7 +220,7 @@ static void pl190_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pl190_ops = {
.read = pl190_read,
.write = pl190_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl190_reset(DeviceState *d)
diff --git a/hw/intc/puv3_intc.c b/hw/intc/puv3_intc.c
index e2f6d98..97999cc 100644
--- a/hw/intc/puv3_intc.c
+++ b/hw/intc/puv3_intc.c
@@ -100,7 +100,7 @@ static const MemoryRegionOps puv3_intc_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void puv3_intc_realize(DeviceState *dev, Error **errp)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 9764 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 24/42] hw/isa: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (22 preceding siblings ...)
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 23/42] hw/intc: " tony.nguyen
@ 2019-08-16 7:34 ` tony.nguyen
2019-08-16 10:01 ` Philippe Mathieu-Daudé
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 25/42] hw/misc: " tony.nguyen
` (19 subsequent siblings)
43 siblings, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:34 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1280 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/isa/vt82c686.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 12c460590..adf65d3 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -108,7 +108,7 @@ static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
static const MemoryRegionOps superio_ops = {
.read = superio_ioport_readb,
.write = superio_ioport_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 2575 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 25/42] hw/misc: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (23 preceding siblings ...)
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 24/42] hw/isa: " tony.nguyen
@ 2019-08-16 7:34 ` tony.nguyen
2019-08-16 10:04 ` Philippe Mathieu-Daudé
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 26/42] hw/net: " tony.nguyen
` (18 subsequent siblings)
43 siblings, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:34 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 3915 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/misc/a9scu.c | 2 +-
hw/misc/applesmc.c | 6 +++---
hw/misc/arm11scu.c | 2 +-
hw/misc/arm_l2x0.c | 2 +-
hw/misc/puv3_pm.c | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index 4307f00..3de8cd3 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -94,7 +94,7 @@ static void a9_scu_write(void *opaque, hwaddr offset,
static const MemoryRegionOps a9_scu_ops = {
.read = a9_scu_read,
.write = a9_scu_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void a9_scu_reset(DeviceState *dev)
diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c
index 2d7eb3c..6c91f29 100644
--- a/hw/misc/applesmc.c
+++ b/hw/misc/applesmc.c
@@ -285,7 +285,7 @@ static void qdev_applesmc_isa_reset(DeviceState *dev)
static const MemoryRegionOps applesmc_data_io_ops = {
.write = applesmc_io_data_write,
.read = applesmc_io_data_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
@@ -295,7 +295,7 @@ static const MemoryRegionOps applesmc_data_io_ops = {
static const MemoryRegionOps applesmc_cmd_io_ops = {
.write = applesmc_io_cmd_write,
.read = applesmc_io_cmd_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
@@ -305,7 +305,7 @@ static const MemoryRegionOps applesmc_cmd_io_ops = {
static const MemoryRegionOps applesmc_err_io_ops = {
.write = applesmc_io_err_write,
.read = applesmc_io_err_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
diff --git a/hw/misc/arm11scu.c b/hw/misc/arm11scu.c
index 84275df..59fd7c0 100644
--- a/hw/misc/arm11scu.c
+++ b/hw/misc/arm11scu.c
@@ -57,7 +57,7 @@ static void mpcore_scu_write(void *opaque, hwaddr offset,
static const MemoryRegionOps mpcore_scu_ops = {
.read = mpcore_scu_read,
.write = mpcore_scu_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void arm11_scu_realize(DeviceState *dev, Error **errp)
diff --git a/hw/misc/arm_l2x0.c b/hw/misc/arm_l2x0.c
index b88f40a..72ecf46 100644
--- a/hw/misc/arm_l2x0.c
+++ b/hw/misc/arm_l2x0.c
@@ -157,7 +157,7 @@ static void l2x0_priv_reset(DeviceState *dev)
static const MemoryRegionOps l2x0_mem_ops = {
.read = l2x0_priv_read,
.write = l2x0_priv_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void l2x0_priv_init(Object *obj)
diff --git a/hw/misc/puv3_pm.c b/hw/misc/puv3_pm.c
index b538b4a..cd82b69 100644
--- a/hw/misc/puv3_pm.c
+++ b/hw/misc/puv3_pm.c
@@ -118,7 +118,7 @@ static const MemoryRegionOps puv3_pm_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void puv3_pm_realize(DeviceState *dev, Error **errp)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 6733 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 26/42] hw/net: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (24 preceding siblings ...)
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 25/42] hw/misc: " tony.nguyen
@ 2019-08-16 7:35 ` tony.nguyen
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: " tony.nguyen
` (17 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:35 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 4037 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/net/allwinner_emac.c | 2 +-
hw/net/imx_fec.c | 2 +-
hw/net/lan9118.c | 4 ++--
hw/net/lance.c | 2 +-
hw/net/smc91c111.c | 2 +-
hw/net/stellaris_enet.c | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index eecda52..97e22e7 100644
--- a/hw/net/allwinner_emac.c
+++ b/hw/net/allwinner_emac.c
@@ -418,7 +418,7 @@ static void aw_emac_set_link(NetClientState *nc)
static const MemoryRegionOps aw_emac_mem_ops = {
.read = aw_emac_read,
.write = aw_emac_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 404154e..76d42c8 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -1278,7 +1278,7 @@ static const MemoryRegionOps imx_eth_ops = {
.write = imx_eth_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void imx_eth_cleanup(NetClientState *nc)
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index f6120be..bb1bbb3 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -1304,13 +1304,13 @@ static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
static const MemoryRegionOps lan9118_mem_ops = {
.read = lan9118_readl,
.write = lan9118_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps lan9118_16bit_mem_ops = {
.read = lan9118_16bit_mode_read,
.write = lan9118_16bit_mode_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static NetClientInfo net_lan9118_info = {
diff --git a/hw/net/lance.c b/hw/net/lance.c
index 2978c01..d95f170 100644
--- a/hw/net/lance.c
+++ b/hw/net/lance.c
@@ -74,7 +74,7 @@ static uint64_t lance_mem_read(void *opaque, hwaddr addr,
static const MemoryRegionOps lance_mem_ops = {
.read = lance_mem_read,
.write = lance_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 2,
.max_access_size = 2,
diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c
index 4a612ee..49e4bf5 100644
--- a/hw/net/smc91c111.c
+++ b/hw/net/smc91c111.c
@@ -757,7 +757,7 @@ static const MemoryRegionOps smc91c111_mem_ops = {
.write = smc91c111_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static NetClientInfo net_smc91c111_info = {
diff --git a/hw/net/stellaris_enet.c b/hw/net/stellaris_enet.c
index 2f645bf..15ec227 100644
--- a/hw/net/stellaris_enet.c
+++ b/hw/net/stellaris_enet.c
@@ -456,7 +456,7 @@ static void stellaris_enet_write(void *opaque, hwaddr offset,
static const MemoryRegionOps stellaris_enet_ops = {
.read = stellaris_enet_read,
.write = stellaris_enet_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void stellaris_enet_reset(DeviceState *dev)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 6872 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (25 preceding siblings ...)
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 26/42] hw/net: " tony.nguyen
@ 2019-08-16 7:35 ` tony.nguyen
2019-08-16 10:06 ` Philippe Mathieu-Daudé
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 28/42] hw/sd: " tony.nguyen
` (16 subsequent siblings)
43 siblings, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:35 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2220 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/pci-host/q35.c | 2 +-
hw/pci-host/versatile.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 0a010be..fd20f72 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -288,7 +288,7 @@ static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps tseg_blackhole_ops = {
.read = tseg_blackhole_read,
.write = tseg_blackhole_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.impl.min_access_size = 4,
diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
index 791b321..e7017f3 100644
--- a/hw/pci-host/versatile.c
+++ b/hw/pci-host/versatile.c
@@ -240,7 +240,7 @@ static uint64_t pci_vpb_reg_read(void *opaque, hwaddr addr,
static const MemoryRegionOps pci_vpb_reg_ops = {
.read = pci_vpb_reg_read,
.write = pci_vpb_reg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -306,7 +306,7 @@ static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
static const MemoryRegionOps pci_vpb_config_ops = {
.read = pci_vpb_config_read,
.write = pci_vpb_config_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 3865 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 28/42] hw/sd: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (26 preceding siblings ...)
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: " tony.nguyen
@ 2019-08-16 7:35 ` tony.nguyen
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 29/42] hw/ssi: " tony.nguyen
` (15 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:35 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1179 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/sd/pl181.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index 81b406d..f2027aa 100644
--- a/hw/sd/pl181.c
+++ b/hw/sd/pl181.c
@@ -449,7 +449,7 @@ static void pl181_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pl181_ops = {
.read = pl181_read,
.write = pl181_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl181_reset(DeviceState *d)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 2295 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 29/42] hw/ssi: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (27 preceding siblings ...)
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 28/42] hw/sd: " tony.nguyen
@ 2019-08-16 7:35 ` tony.nguyen
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 30/42] hw/timer: " tony.nguyen
` (14 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:35 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2793 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/ssi/mss-spi.c | 2 +-
hw/ssi/pl022.c | 2 +-
hw/ssi/stm32f2xx_spi.c | 2 +-
hw/ssi/xilinx_spips.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
index 4c9da5d..71fd138 100644
--- a/hw/ssi/mss-spi.c
+++ b/hw/ssi/mss-spi.c
@@ -359,7 +359,7 @@ static void spi_write(void *opaque, hwaddr addr,
static const MemoryRegionOps spi_ops = {
.read = spi_read,
.write = spi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 4
diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c
index fec73ca..10d1995 100644
--- a/hw/ssi/pl022.c
+++ b/hw/ssi/pl022.c
@@ -226,7 +226,7 @@ static void pl022_reset(DeviceState *dev)
static const MemoryRegionOps pl022_ops = {
.read = pl022_read,
.write = pl022_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static int pl022_post_load(void *opaque, int version_id)
diff --git a/hw/ssi/stm32f2xx_spi.c b/hw/ssi/stm32f2xx_spi.c
index 4249101..e1e5ab5 100644
--- a/hw/ssi/stm32f2xx_spi.c
+++ b/hw/ssi/stm32f2xx_spi.c
@@ -166,7 +166,7 @@ static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
static const MemoryRegionOps stm32f2xx_spi_ops = {
.read = stm32f2xx_spi_read,
.write = stm32f2xx_spi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_stm32f2xx_spi = {
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index b29e0a4..8cadc4e 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -1238,7 +1238,7 @@ static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps lqspi_ops = {
.read_with_attrs = lqspi_read,
.write_with_attrs = lqspi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 4809 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 30/42] hw/timer: Declare device little or big endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (28 preceding siblings ...)
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 29/42] hw/ssi: " tony.nguyen
@ 2019-08-16 7:36 ` tony.nguyen
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 31/42] build: Correct non-common common-obj-* to obj-* tony.nguyen
` (13 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:36 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 9637 bytes --]
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result in genuinely native endian devices
being incorrectly declared as little or big endian, but should not
introduce regressions for current targets.
These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
has a new target with an opposite endian or 2) someone informed knows
better =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/timer/a9gtimer.c | 4 ++--
hw/timer/arm_mptimer.c | 4 ++--
hw/timer/arm_timer.c | 4 ++--
hw/timer/armv7m_systick.c | 2 +-
hw/timer/aspeed_rtc.c | 2 +-
hw/timer/cadence_ttc.c | 2 +-
hw/timer/grlib_gptimer.c | 2 +-
hw/timer/hpet.c | 2 +-
hw/timer/imx_epit.c | 2 +-
hw/timer/imx_gpt.c | 2 +-
hw/timer/lm32_timer.c | 2 +-
hw/timer/milkymist-sysctl.c | 2 +-
hw/timer/mss-timer.c | 2 +-
hw/timer/pl031.c | 2 +-
hw/timer/stm32f2xx_timer.c | 2 +-
hw/timer/sun4v-rtc.c | 2 +-
16 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c
index 09e2a7b..8bb5f6e 100644
--- a/hw/timer/a9gtimer.c
+++ b/hw/timer/a9gtimer.c
@@ -254,7 +254,7 @@ static const MemoryRegionOps a9_gtimer_this_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps a9_gtimer_ops = {
@@ -264,7 +264,7 @@ static const MemoryRegionOps a9_gtimer_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void a9_gtimer_reset(DeviceState *dev)
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index 93044aa..9397218 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -190,7 +190,7 @@ static const MemoryRegionOps arm_thistimer_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps timerblock_ops = {
@@ -200,7 +200,7 @@ static const MemoryRegionOps timerblock_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void timerblock_reset(TimerBlock *tb)
diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c
index f0a7534..22ce3ff 100644
--- a/hw/timer/arm_timer.c
+++ b/hw/timer/arm_timer.c
@@ -265,7 +265,7 @@ static void sp804_write(void *opaque, hwaddr offset,
static const MemoryRegionOps sp804_ops = {
.read = sp804_read,
.write = sp804_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_sp804 = {
@@ -346,7 +346,7 @@ static void icp_pit_write(void *opaque, hwaddr offset,
static const MemoryRegionOps icp_pit_ops = {
.read = icp_pit_read,
.write = icp_pit_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void icp_pit_init(Object *obj)
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
index 9464074..3c34fd0 100644
--- a/hw/timer/armv7m_systick.c
+++ b/hw/timer/armv7m_systick.c
@@ -191,7 +191,7 @@ static MemTxResult systick_write(void *opaque, hwaddr addr,
static const MemoryRegionOps systick_ops = {
.read_with_attrs = systick_read,
.write_with_attrs = systick_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
diff --git a/hw/timer/aspeed_rtc.c b/hw/timer/aspeed_rtc.c
index 19f061c..c528e47 100644
--- a/hw/timer/aspeed_rtc.c
+++ b/hw/timer/aspeed_rtc.c
@@ -130,7 +130,7 @@ static void aspeed_rtc_reset(DeviceState *d)
static const MemoryRegionOps aspeed_rtc_ops = {
.read = aspeed_rtc_read,
.write = aspeed_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_aspeed_rtc = {
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
index 115d935..d422efe 100644
--- a/hw/timer/cadence_ttc.c
+++ b/hw/timer/cadence_ttc.c
@@ -389,7 +389,7 @@ static void cadence_ttc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps cadence_ttc_ops = {
.read = cadence_ttc_read,
.write = cadence_ttc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void cadence_timer_reset(CadenceTimerState *s)
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
index e45a490..dc3b028 100644
--- a/hw/timer/grlib_gptimer.c
+++ b/hw/timer/grlib_gptimer.c
@@ -313,7 +313,7 @@ static void grlib_gptimer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps grlib_gptimer_ops = {
.read = grlib_gptimer_read,
.write = grlib_gptimer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 41024f3..8268b24 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -675,7 +675,7 @@ static const MemoryRegionOps hpet_ram_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void hpet_reset(DeviceState *d)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 7a88316..a87dc06 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -282,7 +282,7 @@ static void imx_epit_cmp(void *opaque)
static const MemoryRegionOps imx_epit_ops = {
.read = imx_epit_read,
.write = imx_epit_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_imx_timer_epit = {
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 3086c03..4eca249 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -474,7 +474,7 @@ static void imx_gpt_timeout(void *opaque)
static const MemoryRegionOps imx_gpt_ops = {
.read = imx_gpt_read,
.write = imx_gpt_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c
index 6ce876c..88d2ee0 100644
--- a/hw/timer/lm32_timer.c
+++ b/hw/timer/lm32_timer.c
@@ -144,7 +144,7 @@ static void timer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps timer_ops = {
.read = timer_read,
.write = timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
diff --git a/hw/timer/milkymist-sysctl.c b/hw/timer/milkymist-sysctl.c
index a9d2508..c1d715f 100644
--- a/hw/timer/milkymist-sysctl.c
+++ b/hw/timer/milkymist-sysctl.c
@@ -220,7 +220,7 @@ static const MemoryRegionOps sysctl_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static void timer0_hit(void *opaque)
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
index 6add47a..26a51f1 100644
--- a/hw/timer/mss-timer.c
+++ b/hw/timer/mss-timer.c
@@ -197,7 +197,7 @@ timer_write(void *opaque, hwaddr offset,
static const MemoryRegionOps timer_ops = {
.read = timer_read,
.write = timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 4
diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
index 1a7e2ee..62b0fab 100644
--- a/hw/timer/pl031.c
+++ b/hw/timer/pl031.c
@@ -175,7 +175,7 @@ static void pl031_write(void * opaque, hwaddr offset,
static const MemoryRegionOps pl031_ops = {
.read = pl031_read,
.write = pl031_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pl031_init(Object *obj)
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index 4c49dc4..ecfcdad 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -265,7 +265,7 @@ static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
static const MemoryRegionOps stm32f2xx_timer_ops = {
.read = stm32f2xx_timer_read,
.write = stm32f2xx_timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_stm32f2xx_timer = {
diff --git a/hw/timer/sun4v-rtc.c b/hw/timer/sun4v-rtc.c
index ba62adc..6b7ca75 100644
--- a/hw/timer/sun4v-rtc.c
+++ b/hw/timer/sun4v-rtc.c
@@ -48,7 +48,7 @@ static void sun4v_rtc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sun4v_rtc_ops = {
.read = sun4v_rtc_read,
.write = sun4v_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_BIG_ENDIAN,
};
void sun4v_rtc_init(hwaddr addr)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 15851 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 31/42] build: Correct non-common common-obj-* to obj-*
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (29 preceding siblings ...)
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 30/42] hw/timer: " tony.nguyen
@ 2019-08-16 7:36 ` tony.nguyen
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 32/42] exec: Map device_endian onto MemOp tony.nguyen
` (12 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:36 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 13864 bytes --]
Preparation for replacing device_endian with MemOp.
Device realizing code with MemorRegionOps endianness as
DEVICE_NATIVE_ENDIAN is not common code.
Corrected devices were identified by making the declaration of
DEVICE_NATIVE_ENDIAN conditional upon NEED_CPU_H and then listing
what failed to compile.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
hw/audio/Makefile.objs | 3 ++-
hw/block/Makefile.objs | 6 +++---
hw/char/Makefile.objs | 4 ++--
hw/core/Makefile.objs | 2 +-
hw/display/Makefile.objs | 6 +++---
hw/dma/Makefile.objs | 6 +++---
hw/gpio/Makefile.objs | 2 +-
hw/i2c/Makefile.objs | 2 +-
hw/input/Makefile.objs | 2 +-
hw/intc/Makefile.objs | 6 +++---
hw/ipack/Makefile.objs | 2 +-
hw/misc/Makefile.objs | 10 +++++-----
hw/net/Makefile.objs | 2 +-
hw/pci-host/Makefile.objs | 2 +-
hw/scsi/Makefile.objs | 2 +-
hw/ssi/Makefile.objs | 2 +-
hw/timer/Makefile.objs | 6 +++---
hw/virtio/Makefile.objs | 2 +-
18 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/hw/audio/Makefile.objs b/hw/audio/Makefile.objs
index 63db383..13133b4 100644
--- a/hw/audio/Makefile.objs
+++ b/hw/audio/Makefile.objs
@@ -5,7 +5,8 @@ common-obj-$(CONFIG_AC97) += ac97.o
common-obj-$(CONFIG_ADLIB) += fmopl.o adlib.o
common-obj-$(CONFIG_GUS) += gus.o gusemu_hal.o gusemu_mixer.o
common-obj-$(CONFIG_CS4231A) += cs4231a.o
-common-obj-$(CONFIG_HDA) += intel-hda.o hda-codec.o
+common-obj-$(CONFIG_HDA) += hda-codec.o
+obj-$(CONFIG_HDA) += intel-hda.o
common-obj-$(CONFIG_PCSPK) += pcspk.o
common-obj-$(CONFIG_WM8750) += wm8750.o
diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs
index f5f643f..04ed4d7 100644
--- a/hw/block/Makefile.objs
+++ b/hw/block/Makefile.objs
@@ -1,9 +1,9 @@
common-obj-y += block.o cdrom.o hd-geometry.o
-common-obj-$(CONFIG_FDC) += fdc.o
+obj-$(CONFIG_FDC) += fdc.o
common-obj-$(CONFIG_SSI_M25P80) += m25p80.o
common-obj-$(CONFIG_NAND) += nand.o
-common-obj-$(CONFIG_PFLASH_CFI01) += pflash_cfi01.o
-common-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o
+obj-$(CONFIG_PFLASH_CFI01) += pflash_cfi01.o
+obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o
common-obj-$(CONFIG_XEN) += xen-block.o
common-obj-$(CONFIG_ECC) += ecc.o
common-obj-$(CONFIG_ONENAND) += onenand.o
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 02d8a66..215c02b 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -1,7 +1,6 @@
common-obj-$(CONFIG_IPACK) += ipoctal232.o
common-obj-$(CONFIG_ESCC) += escc.o
common-obj-$(CONFIG_NRF51_SOC) += nrf51_uart.o
-common-obj-$(CONFIG_PARALLEL) += parallel.o
common-obj-$(CONFIG_ISA_BUS) += parallel-isa.o
common-obj-$(CONFIG_PL011) += pl011.o
common-obj-$(CONFIG_SERIAL) += serial.o
@@ -9,7 +8,6 @@ common-obj-$(CONFIG_SERIAL_ISA) += serial-isa.o
common-obj-$(CONFIG_SERIAL_PCI) += serial-pci.o
common-obj-$(CONFIG_SERIAL_PCI_MULTI) += serial-pci-multi.o
common-obj-$(CONFIG_VIRTIO_SERIAL) += virtio-console.o
-common-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
common-obj-$(CONFIG_XEN) += xen_console.o
common-obj-$(CONFIG_CADENCE) += cadence_uart.o
@@ -21,6 +19,8 @@ obj-$(CONFIG_PSERIES) += spapr_vty.o
obj-$(CONFIG_DIGIC) += digic-uart.o
obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
obj-$(CONFIG_RASPI) += bcm2835_aux.o
+obj-$(CONFIG_PARALLEL) += parallel.o
+obj-$(CONFIG_XILINX) += xilinx_uartlite.o
common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index f8481d9..1b336c6 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -9,7 +9,7 @@ common-obj-y += hotplug.o
common-obj-$(CONFIG_SOFTMMU) += nmi.o
common-obj-$(CONFIG_SOFTMMU) += vm-change-state-handler.o
-common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
+obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
common-obj-$(CONFIG_XILINX_AXI) += stream.o
common-obj-$(CONFIG_PTIMER) += ptimer.o
common-obj-$(CONFIG_SOFTMMU) += sysbus.o
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index a64998f..facc1d4 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -8,7 +8,7 @@ common-obj-$(CONFIG_ADS7846) += ads7846.o
common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
common-obj-$(call land,$(CONFIG_VGA_CIRRUS),$(CONFIG_VGA_ISA))+=cirrus_vga_isa.o
common-obj-$(CONFIG_G364FB) += g364fb.o
-common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
+obj-$(CONFIG_JAZZ_LED) += jazz_led.o
common-obj-$(CONFIG_PL110) += pl110.o
common-obj-$(CONFIG_SII9022) += sii9022.o
common-obj-$(CONFIG_SSD0303) += ssd0303.o
@@ -17,12 +17,12 @@ common-obj-$(CONFIG_XEN) += xenfb.o
common-obj-$(CONFIG_VGA_PCI) += vga-pci.o
common-obj-$(CONFIG_VGA_ISA) += vga-isa.o
-common-obj-$(CONFIG_VGA_ISA_MM) += vga-isa-mm.o
+obj-$(CONFIG_VGA_ISA_MM) += vga-isa-mm.o
common-obj-$(CONFIG_VMWARE_VGA) += vmware_vga.o
common-obj-$(CONFIG_BOCHS_DISPLAY) += bochs-display.o
common-obj-$(CONFIG_BLIZZARD) += blizzard.o
-common-obj-$(CONFIG_EXYNOS4) += exynos4210_fimd.o
+obj-$(CONFIG_EXYNOS4) += exynos4210_fimd.o
common-obj-$(CONFIG_FRAMEBUFFER) += framebuffer.o
obj-$(CONFIG_MILKYMIST) += milkymist-vgafb.o
common-obj-$(CONFIG_ZAURUS) += tc6393xb.o
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 8b39f9c..fff43e0 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -1,10 +1,10 @@
common-obj-$(CONFIG_PUV3) += puv3_dma.o
-common-obj-$(CONFIG_RC4030) += rc4030.o
+obj-$(CONFIG_RC4030) += rc4030.o
common-obj-$(CONFIG_PL080) += pl080.o
common-obj-$(CONFIG_PL330) += pl330.o
common-obj-$(CONFIG_I82374) += i82374.o
-common-obj-$(CONFIG_I8257) += i8257.o
-common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
+obj-$(CONFIG_I8257) += i8257.o
+obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
common-obj-$(CONFIG_ZYNQ_DEVCFG) += xlnx-zynq-devcfg.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
index e5da0cb..3199288 100644
--- a/hw/gpio/Makefile.objs
+++ b/hw/gpio/Makefile.objs
@@ -1,6 +1,6 @@
common-obj-$(CONFIG_MAX7310) += max7310.o
common-obj-$(CONFIG_PL061) += pl061.o
-common-obj-$(CONFIG_PUV3) += puv3_gpio.o
+obj-$(CONFIG_PUV3) += puv3_gpio.o
common-obj-$(CONFIG_ZAURUS) += zaurus.o
common-obj-$(CONFIG_E500) += mpc8xxx.o
common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index d7073a4..f026949 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -4,7 +4,7 @@ common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
common-obj-$(CONFIG_ACPI_X86_ICH) += smbus_ich9.o
common-obj-$(CONFIG_ACPI_SMBUS) += pm_smbus.o
common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o
-common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
+obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
common-obj-$(CONFIG_IMX_I2C) += imx_i2c.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_i2c.o
common-obj-$(CONFIG_NRF51_SOC) += microbit_i2c.o
diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs
index a1bc502..e28f844 100644
--- a/hw/input/Makefile.objs
+++ b/hw/input/Makefile.objs
@@ -1,7 +1,7 @@
common-obj-$(CONFIG_ADB) += adb.o adb-mouse.o adb-kbd.o
common-obj-y += hid.o
common-obj-$(CONFIG_LM832X) += lm832x.o
-common-obj-$(CONFIG_PCKBD) += pckbd.o
+obj-$(CONFIG_PCKBD) += pckbd.o
common-obj-$(CONFIG_PL050) += pl050.o
common-obj-$(CONFIG_PS2) += ps2.o
common-obj-$(CONFIG_STELLARIS_INPUT) += stellaris_input.o
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 03019b9..650de8b 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -2,14 +2,14 @@ common-obj-$(CONFIG_HEATHROW_PIC) += heathrow_pic.o
common-obj-$(CONFIG_I8259) += i8259_common.o i8259.o
common-obj-$(CONFIG_PL190) += pl190.o
common-obj-$(CONFIG_PUV3) += puv3_intc.o
-common-obj-$(CONFIG_XILINX) += xilinx_intc.o
+obj-$(CONFIG_XILINX) += xilinx_intc.o
common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-intc.o
common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o
common-obj-$(CONFIG_IMX) += imx_avic.o imx_gpcv2.o
common-obj-$(CONFIG_LM32) += lm32_pic.o
common-obj-$(CONFIG_REALVIEW) += realview_gic.o
-common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o
+obj-$(CONFIG_SLAVIO) += slavio_intctl.o
common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
@@ -18,7 +18,7 @@ common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
-common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
+obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
common-obj-$(CONFIG_OPENPIC) += openpic.o
common-obj-y += intc.o
diff --git a/hw/ipack/Makefile.objs b/hw/ipack/Makefile.objs
index 8b9bdcb..a7c5485 100644
--- a/hw/ipack/Makefile.objs
+++ b/hw/ipack/Makefile.objs
@@ -1,2 +1,2 @@
common-obj-$(CONFIG_IPACK) += ipack.o
-common-obj-$(CONFIG_IPACK) += tpci200.o
+obj-$(CONFIG_IPACK) += tpci200.o
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index e9aab51..10932b2 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-$(CONFIG_APPLESMC) += applesmc.o
+ommon-obj-$(CONFIG_APPLESMC) += applesmc.o
common-obj-$(CONFIG_MAX111X) += max111x.o
common-obj-$(CONFIG_TMP105) += tmp105.o
common-obj-$(CONFIG_TMP421) += tmp421.o
@@ -6,20 +6,20 @@ common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
common-obj-$(CONFIG_SGA) += sga.o
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
-common-obj-$(CONFIG_EDU) += edu.o
+obj-$(CONFIG_EDU) += edu.o
common-obj-$(CONFIG_PCA9552) += pca9552.o
-common-obj-y += unimp.o
+obj-y += unimp.o
common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o
# ARM devices
common-obj-$(CONFIG_PL310) += arm_l2x0.o
-common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o
+obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o
common-obj-$(CONFIG_A9SCU) += a9scu.o
common-obj-$(CONFIG_ARM11SCU) += arm11scu.o
# Mac devices
-common-obj-$(CONFIG_MOS6522) += mos6522.o
+obj-$(CONFIG_MOS6522) += mos6522.o
# PKUnity SoC devices
common-obj-$(CONFIG_PUV3) += puv3_pm.o
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
index 9904273..8526611 100644
--- a/hw/net/Makefile.objs
+++ b/hw/net/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-$(CONFIG_DP8393X) += dp8393x.o
+obj-$(CONFIG_DP8393X) += dp8393x.o
common-obj-$(CONFIG_XEN) += xen_nic.o
common-obj-$(CONFIG_NE2000_COMMON) += ne2000.o
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index a9cd3e0..02f286b 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -12,7 +12,7 @@ common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o
common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
common-obj-$(CONFIG_PCI_SABRE) += sabre.o
-common-obj-$(CONFIG_FULONG) += bonito.o
+obj-$(CONFIG_FULONG) += bonito.o
common-obj-$(CONFIG_PCI_PIIX) += piix.o
common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
diff --git a/hw/scsi/Makefile.objs b/hw/scsi/Makefile.objs
index 54b36ed..418af9a 100644
--- a/hw/scsi/Makefile.objs
+++ b/hw/scsi/Makefile.objs
@@ -4,7 +4,7 @@ common-obj-$(CONFIG_LSI_SCSI_PCI) += lsi53c895a.o
common-obj-$(CONFIG_MPTSAS_SCSI_PCI) += mptsas.o mptconfig.o mptendian.o
common-obj-$(CONFIG_MEGASAS_SCSI_PCI) += megasas.o
common-obj-$(CONFIG_VMW_PVSCSI_SCSI_PCI) += vmw_pvscsi.o
-common-obj-$(CONFIG_ESP) += esp.o
+obj-$(CONFIG_ESP) += esp.o
common-obj-$(CONFIG_ESP_PCI) += esp-pci.o
obj-$(CONFIG_SPAPR_VSCSI) += spapr_vscsi.o
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index f5bcc65..54b5542 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -1,6 +1,6 @@
common-obj-$(CONFIG_PL022) += pl022.o
common-obj-$(CONFIG_SSI) += ssi.o
-common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
+obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 123d92c..b27513f 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -12,10 +12,10 @@ ifeq ($(CONFIG_ISA_BUS),y)
common-obj-$(CONFIG_M48T59) += m48t59-isa.o
endif
common-obj-$(CONFIG_PL031) += pl031.o
-common-obj-$(CONFIG_PUV3) += puv3_ost.o
+obj-$(CONFIG_PUV3) += puv3_ost.o
common-obj-$(CONFIG_TWL92230) += twl92230.o
-common-obj-$(CONFIG_XILINX) += xilinx_timer.o
-common-obj-$(CONFIG_SLAVIO) += slavio_timer.o
+obj-$(CONFIG_XILINX) += xilinx_timer.o
+obj-$(CONFIG_SLAVIO) += slavio_timer.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_timer.o
common-obj-$(CONFIG_GRLIB) += grlib_gptimer.o
common-obj-$(CONFIG_IMX) += imx_epit.o
diff --git a/hw/virtio/Makefile.objs b/hw/virtio/Makefile.objs
index 964ce78..573b1a9 100644
--- a/hw/virtio/Makefile.objs
+++ b/hw/virtio/Makefile.objs
@@ -8,7 +8,7 @@ obj-$(CONFIG_VHOST_USER) += vhost-user.o
common-obj-$(CONFIG_VIRTIO_RNG) += virtio-rng.o
common-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
-common-obj-$(CONFIG_VIRTIO_MMIO) += virtio-mmio.o
+obj-$(CONFIG_VIRTIO_MMIO) += virtio-mmio.o
obj-$(CONFIG_VIRTIO_BALLOON) += virtio-balloon.o
obj-$(CONFIG_VIRTIO_CRYPTO) += virtio-crypto.o
obj-$(call land,$(CONFIG_VIRTIO_CRYPTO),$(CONFIG_VIRTIO_PCI)) += virtio-crypto-pci.o
--
1.8.3.1
?
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* [Xen-devel] [Qemu-devel] [PATCH v7 32/42] exec: Map device_endian onto MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (30 preceding siblings ...)
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 31/42] build: Correct non-common common-obj-* to obj-* tony.nguyen
@ 2019-08-16 7:36 ` tony.nguyen
2019-08-16 7:37 ` [Xen-devel] [Qemu-devel] [PATCH v7 34/42] exec: Delete device_endian tony.nguyen
` (11 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:36 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2785 bytes --]
Preparation to replace device_endian with MemOp.
Mapping device_endian onto MemOp limits behaviour changes to this
relatively smaller patch.
The next patch will replace all device_endian usages with the
equivalent MemOp. That patch will be large but have no behaviour
changes.
A subsequent patch will then delete unused device_endian.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/char/serial.c | 18 ++++++------------
include/exec/cpu-common.h | 10 +++++++---
2 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/hw/char/serial.c b/hw/char/serial.c
index 7c42a2a..521c76b 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -1012,22 +1012,15 @@ static void serial_mm_write(void *opaque, hwaddr addr,
serial_ioport_write(s, addr >> s->it_shift, value, 1);
}
-static const MemoryRegionOps serial_mm_ops[3] = {
- [DEVICE_NATIVE_ENDIAN] = {
- .read = serial_mm_read,
- .write = serial_mm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid.max_access_size = 8,
- .impl.max_access_size = 8,
- },
- [DEVICE_LITTLE_ENDIAN] = {
+static const MemoryRegionOps serial_mm_ops[2] = {
+ [0] = {
.read = serial_mm_read,
.write = serial_mm_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.max_access_size = 8,
.impl.max_access_size = 8,
},
- [DEVICE_BIG_ENDIAN] = {
+ [1] = {
.read = serial_mm_read,
.write = serial_mm_write,
.endianness = DEVICE_BIG_ENDIAN,
@@ -1053,8 +1046,9 @@ SerialState *serial_mm_init(MemoryRegion *address_space,
serial_realize_core(s, &error_fatal);
vmstate_register(NULL, base, &vmstate_serial, s);
- memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
- "serial", 8 << it_shift);
+ memory_region_init_io(&s->io, NULL,
+ &serial_mm_ops[end == DEVICE_BIG_ENDIAN],
+ s, "serial", 8 << it_shift);
memory_region_add_subregion(address_space, base, &s->io);
return s;
}
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index f7dbe75..c388453 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -16,10 +16,14 @@ void tcg_flush_softmmu_tlb(CPUState *cs);
#if !defined(CONFIG_USER_ONLY)
+#include "exec/memop.h"
+
enum device_endian {
- DEVICE_NATIVE_ENDIAN,
- DEVICE_BIG_ENDIAN,
- DEVICE_LITTLE_ENDIAN,
+#ifdef NEED_CPU_H
+ DEVICE_NATIVE_ENDIAN = MO_TE,
+#endif
+ DEVICE_BIG_ENDIAN = MO_BE,
+ DEVICE_LITTLE_ENDIAN = MO_LE,
};
#if defined(HOST_WORDS_BIGENDIAN)
--
1.8.3.1
?
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_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 34/42] exec: Delete device_endian
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (31 preceding siblings ...)
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 32/42] exec: Map device_endian onto MemOp tony.nguyen
@ 2019-08-16 7:37 ` tony.nguyen
2019-08-16 7:37 ` [Xen-devel] [Qemu-devel] [PATCH v7 35/42] exec: Delete DEVICE_HOST_ENDIAN tony.nguyen
` (10 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:37 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 765 bytes --]
device_endian has been made redundant by MemOp.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-common.h | 8 --------
1 file changed, 8 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 01a29ba..7eeb78c 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -18,14 +18,6 @@ void tcg_flush_softmmu_tlb(CPUState *cs);
#include "exec/memop.h"
-enum device_endian {
-#ifdef NEED_CPU_H
- DEVICE_NATIVE_ENDIAN = MO_TE,
-#endif
- DEVICE_BIG_ENDIAN = MO_BE,
- DEVICE_LITTLE_ENDIAN = MO_LE,
-};
-
#if defined(HOST_WORDS_BIGENDIAN)
#define DEVICE_HOST_ENDIAN MO_BE
#else
--
1.8.3.1
?
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_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 35/42] exec: Delete DEVICE_HOST_ENDIAN
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (32 preceding siblings ...)
2019-08-16 7:37 ` [Xen-devel] [Qemu-devel] [PATCH v7 34/42] exec: Delete device_endian tony.nguyen
@ 2019-08-16 7:37 ` tony.nguyen
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness tony.nguyen
` (9 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:37 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1434 bytes --]
DEVICE_HOST_ENDIAN is conditional upon HOST_WORDS_BIGENDIAN.
Code is cleaner if the single use of DEVICE_HOST_ENDIAN is instead
directly conditional upon HOST_WORDS_BIGENDIAN.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
include/exec/cpu-common.h | 8 --------
memory.c | 2 +-
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 7eeb78c..b33dc0c 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -16,14 +16,6 @@ void tcg_flush_softmmu_tlb(CPUState *cs);
#if !defined(CONFIG_USER_ONLY)
-#include "exec/memop.h"
-
-#if defined(HOST_WORDS_BIGENDIAN)
-#define DEVICE_HOST_ENDIAN MO_BE
-#else
-#define DEVICE_HOST_ENDIAN MO_LE
-#endif
-
/* address in the RAM (different from a physical address) */
#if defined(CONFIG_XEN_BACKEND)
typedef uint64_t ram_addr_t;
diff --git a/memory.c b/memory.c
index 3cabb52..689390f 100644
--- a/memory.c
+++ b/memory.c
@@ -1362,7 +1362,7 @@ static void memory_region_ram_device_write(void *opaque, hwaddr addr,
static const MemoryRegionOps ram_device_mem_ops = {
.read = memory_region_ram_device_read,
.write = memory_region_ram_device_write,
- .endianness = DEVICE_HOST_ENDIAN,
+ .endianness = 0, /* Host endianness */
.valid = {
.min_access_size = 1,
.max_access_size = 8,
--
1.8.3.1
?
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[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (33 preceding siblings ...)
2019-08-16 7:37 ` [Xen-devel] [Qemu-devel] [PATCH v7 35/42] exec: Delete DEVICE_HOST_ENDIAN tony.nguyen
@ 2019-08-16 7:38 ` tony.nguyen
2019-08-18 12:22 ` Richard Henderson
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp tony.nguyen
` (8 subsequent siblings)
43 siblings, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:38 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 12166 bytes --]
Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.
Call memory_region_dispatch_{read|write} with endianness encoded into
the "MemOp op" operand.
This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.
Once it does handle endianness, callers with byte swaps can collapse
them into adjust_endianness.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
accel/tcg/cputlb.c | 6 ++++--
exec.c | 5 +++--
hw/intc/armv7m_nvic.c | 15 ++++++++-------
hw/s390x/s390-pci-inst.c | 6 ++++--
hw/vfio/pci-quirks.c | 5 +++--
hw/virtio/virtio-pci.c | 6 ++++--
memory_ldst.inc.c | 18 ++++++++++++------
7 files changed, 38 insertions(+), 23 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878..0aff6a3 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),
+ r = memory_region_dispatch_read(mr, mr_offset, &val,
+ size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
@@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
+ r = memory_region_dispatch_write(mr, mr_offset, val,
+ size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
diff --git a/exec.c b/exec.c
index 303f9a7..562fb5b 100644
--- a/exec.c
+++ b/exec.c
@@ -3335,7 +3335,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
potential bugs */
val = ldn_p(buf, l);
result |= memory_region_dispatch_write(mr, addr1, val,
- size_memop(l), attrs);
+ size_memop(l) | MO_TE,
+ attrs);
} else {
/* RAM case */
ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
@@ -3397,7 +3398,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
release_lock |= prepare_mmio_access(mr);
l = memory_access_size(mr, l, addr1);
result |= memory_region_dispatch_read(mr, addr1, &val,
- size_memop(l), attrs);
+ size_memop(l) | MO_TE, attrs);
stn_p(buf, l, val);
} else {
/* RAM case */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 975d7cc..e150f9a 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2346,8 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
if (attrs.secure) {
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
- return memory_region_dispatch_write(mr, addr, value, size_memop(size),
- attrs);
+ return memory_region_dispatch_write(mr, addr, value,
+ size_memop(size) | MO_TE, attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@@ -2366,8 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
if (attrs.secure) {
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
- return memory_region_dispatch_read(mr, addr, data, size_memop(size),
- attrs);
+ return memory_region_dispatch_read(mr, addr, data,
+ size_memop(size) | MO_TE, attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@@ -2393,8 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
/* Direct the access to the correct systick */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
- return memory_region_dispatch_write(mr, addr, value, size_memop(size),
- attrs);
+ return memory_region_dispatch_write(mr, addr, value,
+ size_memop(size) | MO_TE, attrs);
}
static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
@@ -2406,7 +2406,8 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
/* Direct the access to the correct systick */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
- return memory_region_dispatch_read(mr, addr, data, size_memop(size), attrs);
+ return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
+ attrs);
}
static const MemoryRegionOps nvic_systick_ops = {
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0e92a37..272cb28 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -373,7 +373,8 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
mr = pbdev->pdev->io_regions[pcias].memory;
mr = s390_get_subregion(mr, offset, len);
offset -= mr->addr;
- return memory_region_dispatch_read(mr, offset, data, size_memop(len),
+ return memory_region_dispatch_read(mr, offset, data,
+ size_memop(len) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
}
@@ -472,7 +473,8 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
mr = pbdev->pdev->io_regions[pcias].memory;
mr = s390_get_subregion(mr, offset, len);
offset -= mr->addr;
- return memory_region_dispatch_write(mr, offset, data, size_memop(len),
+ return memory_region_dispatch_write(mr, offset, data,
+ size_memop(len) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
}
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index d5c0268..53db1c3 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1072,7 +1072,8 @@ static void vfio_rtl8168_quirk_address_write(void *opaque, hwaddr addr,
/* Write to the proper guest MSI-X table instead */
memory_region_dispatch_write(&vdev->pdev.msix_table_mmio,
- offset, val, size_memop(size),
+ offset, val,
+ size_memop(size) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
}
return; /* Do not write guest MSI-X data to hardware */
@@ -1103,7 +1104,7 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *opaque,
if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) {
hwaddr offset = rtl->addr & 0xfff;
memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset,
- &data, size_memop(size),
+ &data, size_memop(size) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data);
}
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b929e44..ad06c12 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -551,7 +551,8 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
/* As length is under guest control, handle illegal values. */
return;
}
- memory_region_dispatch_write(mr, addr, val, size_memop(len),
+ /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
+ memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
}
@@ -575,7 +576,8 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
/* Make sure caller aligned buf properly */
assert(!(((uintptr_t)buf) & (len - 1)));
- memory_region_dispatch_read(mr, addr, &val, size_memop(len),
+ /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
+ memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
switch (len) {
case 1:
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index d08fc79..482e4b3 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs);
+ /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == MO_LE) {
val = bswap32(val);
@@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs);
+ /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == MO_LE) {
val = bswap64(val);
@@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs);
+ /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian, attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == MO_LE) {
val = bswap16(val);
@@ -342,7 +345,8 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
val = bswap32(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
+ /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
+ r = memory_region_dispatch_write(mr, addr1, val, MO_32 | endian, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -447,7 +451,8 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
val = bswap16(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, MO_16, attrs);
+ /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
+ r = memory_region_dispatch_write(mr, addr1, val, MO_16 | endian, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -520,7 +525,8 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
val = bswap64(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, MO_64, attrs);
+ /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
+ r = memory_region_dispatch_write(mr, addr1, val, MO_64 | endian, attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 22451 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (34 preceding siblings ...)
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness tony.nguyen
@ 2019-08-16 7:38 ` tony.nguyen
2019-08-18 12:37 ` Richard Henderson
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path tony.nguyen
` (7 subsequent siblings)
43 siblings, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:38 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
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kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
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xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 19096 bytes --]
Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
accel/tcg/cputlb.c | 172 +++++++++++++++++++++++++--------------------------
include/exec/memop.h | 6 ++
memory.c | 11 +---
3 files changed, 90 insertions(+), 99 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 0aff6a3..8022c81 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
int mmu_idx, target_ulong addr, uintptr_t retaddr,
- MMUAccessType access_type, int size)
+ MMUAccessType access_type, MemOp op)
{
CPUState *cpu = env_cpu(env);
hwaddr mr_offset;
@@ -906,15 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_read(mr, mr_offset, &val,
- size_memop(size) | MO_TE,
- iotlbentry->attrs);
+ r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
section->offset_within_address_space -
section->offset_within_region;
- cpu_transaction_failed(cpu, physaddr, addr, size, access_type,
+ cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type,
mmu_idx, iotlbentry->attrs, r, retaddr);
}
if (locked) {
@@ -926,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
int mmu_idx, uint64_t val, target_ulong addr,
- uintptr_t retaddr, int size)
+ uintptr_t retaddr, MemOp op)
{
CPUState *cpu = env_cpu(env);
hwaddr mr_offset;
@@ -948,16 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_write(mr, mr_offset, val,
- size_memop(size) | MO_TE,
- iotlbentry->attrs);
+ r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
section->offset_within_address_space -
section->offset_within_region;
- cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE,
- mmu_idx, iotlbentry->attrs, r, retaddr);
+ cpu_transaction_failed(cpu, physaddr, addr, memop_size(op),
+ MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r,
+ retaddr);
}
if (locked) {
qemu_mutex_unlock_iothread();
@@ -1218,14 +1215,15 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
* access type.
*/
-static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endian)
+static inline uint64_t handle_bswap(uint64_t val, MemOp op)
{
- if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) {
- switch (size) {
- case 1: return val;
- case 2: return bswap16(val);
- case 4: return bswap32(val);
- case 8: return bswap64(val);
+ if ((memop_big_endian(op) && NEED_BE_BSWAP) ||
+ (!memop_big_endian(op) && NEED_LE_BSWAP)) {
+ switch (op & MO_SIZE) {
+ case MO_8: return val;
+ case MO_16: return bswap16(val);
+ case MO_32: return bswap32(val);
+ case MO_64: return bswap64(val);
default:
g_assert_not_reached();
}
@@ -1248,7 +1246,7 @@ typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
static inline uint64_t __attribute__((always_inline))
load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
- uintptr_t retaddr, size_t size, bool big_endian, bool code_read,
+ uintptr_t retaddr, MemOp op, bool code_read,
FullLoadHelper *full_load)
{
uintptr_t mmu_idx = get_mmuidx(oi);
@@ -1262,6 +1260,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
unsigned a_bits = get_alignment_bits(get_memop(oi));
void *haddr;
uint64_t res;
+ size_t size = memop_size(op);
/* Handle CPU specific unaligned behaviour */
if (addr & ((1 << a_bits) - 1)) {
@@ -1307,9 +1306,10 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
}
}
+ /* FIXME: io_readx ignores MO_BSWAP. */
res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
- mmu_idx, addr, retaddr, access_type, size);
- return handle_bswap(res, size, big_endian);
+ mmu_idx, addr, retaddr, access_type, op);
+ return handle_bswap(res, op);
}
/* Handle slow unaligned access (it spans two pages or IO). */
@@ -1326,7 +1326,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
r2 = full_load(env, addr2, oi, retaddr);
shift = (addr & (size - 1)) * 8;
- if (big_endian) {
+ if (memop_big_endian(op)) {
/* Big-endian combine. */
res = (r1 << shift) | (r2 >> ((size * 8) - shift));
} else {
@@ -1338,30 +1338,27 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
do_aligned_access:
haddr = (void *)((uintptr_t)addr + entry->addend);
- switch (size) {
- case 1:
+ switch (op) {
+ case MO_UB:
res = ldub_p(haddr);
break;
- case 2:
- if (big_endian) {
- res = lduw_be_p(haddr);
- } else {
- res = lduw_le_p(haddr);
- }
+ case MO_BEUW:
+ res = lduw_be_p(haddr);
break;
- case 4:
- if (big_endian) {
- res = (uint32_t)ldl_be_p(haddr);
- } else {
- res = (uint32_t)ldl_le_p(haddr);
- }
+ case MO_LEUW:
+ res = lduw_le_p(haddr);
break;
- case 8:
- if (big_endian) {
- res = ldq_be_p(haddr);
- } else {
- res = ldq_le_p(haddr);
- }
+ case MO_BEUL:
+ res = (uint32_t)ldl_be_p(haddr);
+ break;
+ case MO_LEUL:
+ res = (uint32_t)ldl_le_p(haddr);
+ break;
+ case MO_BEQ:
+ res = ldq_be_p(haddr);
+ break;
+ case MO_LEQ:
+ res = ldq_le_p(haddr);
break;
default:
g_assert_not_reached();
@@ -1383,8 +1380,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 1, false, false,
- full_ldub_mmu);
+ return load_helper(env, addr, oi, retaddr, MO_8, false, full_ldub_mmu);
}
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
@@ -1396,7 +1392,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 2, false, false,
+ return load_helper(env, addr, oi, retaddr, MO_LEUW, false,
full_le_lduw_mmu);
}
@@ -1409,7 +1405,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 2, true, false,
+ return load_helper(env, addr, oi, retaddr, MO_BEUW, false,
full_be_lduw_mmu);
}
@@ -1422,7 +1418,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 4, false, false,
+ return load_helper(env, addr, oi, retaddr, MO_LEUL, false,
full_le_ldul_mmu);
}
@@ -1435,7 +1431,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 4, true, false,
+ return load_helper(env, addr, oi, retaddr, MO_BEUL, false,
full_be_ldul_mmu);
}
@@ -1448,14 +1444,14 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 8, false, false,
+ return load_helper(env, addr, oi, retaddr, MO_LEQ, false,
helper_le_ldq_mmu);
}
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 8, true, false,
+ return load_helper(env, addr, oi, retaddr, MO_BEQ, false,
helper_be_ldq_mmu);
}
@@ -1501,7 +1497,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
static inline void __attribute__((always_inline))
store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr, size_t size, bool big_endian)
+ TCGMemOpIdx oi, uintptr_t retaddr, MemOp op)
{
uintptr_t mmu_idx = get_mmuidx(oi);
uintptr_t index = tlb_index(env, mmu_idx, addr);
@@ -1510,6 +1506,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
const size_t tlb_off = offsetof(CPUTLBEntry, addr_write);
unsigned a_bits = get_alignment_bits(get_memop(oi));
void *haddr;
+ size_t size = memop_size(op);
/* Handle CPU specific unaligned behaviour */
if (addr & ((1 << a_bits) - 1)) {
@@ -1555,9 +1552,10 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
}
}
+ /* FIXME: io_writex ignores MO_BSWAP. */
io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
- handle_bswap(val, size, big_endian),
- addr, retaddr, size);
+ handle_bswap(val, op),
+ addr, retaddr, op);
return;
}
@@ -1593,7 +1591,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
*/
for (i = 0; i < size; ++i) {
uint8_t val8;
- if (big_endian) {
+ if (memop_big_endian(op)) {
/* Big-endian extract. */
val8 = val >> (((size - 1) * 8) - (i * 8));
} else {
@@ -1607,30 +1605,27 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
do_aligned_access:
haddr = (void *)((uintptr_t)addr + entry->addend);
- switch (size) {
- case 1:
+ switch (op) {
+ case MO_UB:
stb_p(haddr, val);
break;
- case 2:
- if (big_endian) {
- stw_be_p(haddr, val);
- } else {
- stw_le_p(haddr, val);
- }
+ case MO_BEUW:
+ stw_be_p(haddr, val);
break;
- case 4:
- if (big_endian) {
- stl_be_p(haddr, val);
- } else {
- stl_le_p(haddr, val);
- }
+ case MO_LEUW:
+ stw_le_p(haddr, val);
break;
- case 8:
- if (big_endian) {
- stq_be_p(haddr, val);
- } else {
- stq_le_p(haddr, val);
- }
+ case MO_BEUL:
+ stl_be_p(haddr, val);
+ break;
+ case MO_LEUL:
+ stl_le_p(haddr, val);
+ break;
+ case MO_BEQ:
+ stq_be_p(haddr, val);
+ break;
+ case MO_LEQ:
+ stq_le_p(haddr, val);
break;
default:
g_assert_not_reached();
@@ -1641,43 +1636,43 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, 1, false);
+ store_helper(env, addr, val, oi, retaddr, MO_8);
}
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, 2, false);
+ store_helper(env, addr, val, oi, retaddr, MO_LEUW);
}
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, 2, true);
+ store_helper(env, addr, val, oi, retaddr, MO_BEUW);
}
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, 4, false);
+ store_helper(env, addr, val, oi, retaddr, MO_LEUL);
}
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, 4, true);
+ store_helper(env, addr, val, oi, retaddr, MO_BEUL);
}
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, 8, false);
+ store_helper(env, addr, val, oi, retaddr, MO_LEQ);
}
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, 8, true);
+ store_helper(env, addr, val, oi, retaddr, MO_BEQ);
}
/* First set of helpers allows passing in of OI and RETADDR. This makes
@@ -1742,8 +1737,7 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 1, false, true,
- full_ldub_cmmu);
+ return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu);
}
uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
@@ -1755,7 +1749,7 @@ uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 2, false, true,
+ return load_helper(env, addr, oi, retaddr, MO_LEUW, true,
full_le_lduw_cmmu);
}
@@ -1768,7 +1762,7 @@ uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 2, true, true,
+ return load_helper(env, addr, oi, retaddr, MO_BEUW, true,
full_be_lduw_cmmu);
}
@@ -1781,7 +1775,7 @@ uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 4, false, true,
+ return load_helper(env, addr, oi, retaddr, MO_LEUL, true,
full_le_ldul_cmmu);
}
@@ -1794,7 +1788,7 @@ uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 4, true, true,
+ return load_helper(env, addr, oi, retaddr, MO_BEUL, true,
full_be_ldul_cmmu);
}
@@ -1807,13 +1801,13 @@ uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 8, false, true,
+ return load_helper(env, addr, oi, retaddr, MO_LEQ, true,
helper_le_ldq_cmmu);
}
uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr)
{
- return load_helper(env, addr, oi, retaddr, 8, true, true,
+ return load_helper(env, addr, oi, retaddr, MO_BEQ, true,
helper_be_ldq_cmmu);
}
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 0a610b7..529d07b 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -125,4 +125,10 @@ static inline MemOp size_memop(unsigned size)
return ctz32(size);
}
+/* Big endianness from MemOp. */
+static inline bool memop_big_endian(MemOp op)
+{
+ return (op & MO_BSWAP) == MO_BE;
+}
+
#endif
diff --git a/memory.c b/memory.c
index 689390f..01fd29d 100644
--- a/memory.c
+++ b/memory.c
@@ -343,15 +343,6 @@ static void flatview_simplify(FlatView *view)
}
}
-static bool memory_region_big_endian(MemoryRegion *mr)
-{
-#ifdef TARGET_WORDS_BIGENDIAN
- return mr->ops->endianness != MO_LE;
-#else
- return mr->ops->endianness == MO_BE;
-#endif
-}
-
static bool memory_region_wrong_endianness(MemoryRegion *mr)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -564,7 +555,7 @@ static MemTxResult access_with_adjusted_size(hwaddr addr,
/* FIXME: support unaligned access? */
access_size = MAX(MIN(size, access_size_max), access_size_min);
access_mask = MAKE_64BIT_MASK(0, access_size * 8);
- if (memory_region_big_endian(mr)) {
+ if (memop_big_endian(mr->ops->endianness)) {
for (i = 0; i < size; i += access_size) {
r |= access_fn(mr, addr + i, value, access_size,
(size - access_size - i) * 8, access_mask, attrs);
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 34858 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (35 preceding siblings ...)
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp tony.nguyen
@ 2019-08-16 7:38 ` tony.nguyen
2019-08-18 12:46 ` Richard Henderson
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 39/42] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
` (6 subsequent siblings)
43 siblings, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:38 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 10985 bytes --]
Now that MemOp has been pushed down into the memory API, and
callers are encoding endianness, we can collapse byte swaps
along the I/O path into the accelerator and target independent
adjust_endianness.
Collapsing byte swaps along the I/O path enables additional endian
inversion logic, e.g. SPARC64 Invert Endian TTE bit, with redundant
byte swaps cancelling out.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
accel/tcg/cputlb.c | 42 +++------------------------------
hw/virtio/virtio-pci.c | 10 ++++----
memory.c | 33 ++++++++++----------------
memory_ldst.inc.c | 63 --------------------------------------------------
4 files changed, 19 insertions(+), 129 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 8022c81..bb2f55d 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1200,38 +1200,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
cpu_loop_exit_atomic(env_cpu(env), retaddr);
}
-#ifdef TARGET_WORDS_BIGENDIAN
-#define NEED_BE_BSWAP 0
-#define NEED_LE_BSWAP 1
-#else
-#define NEED_BE_BSWAP 1
-#define NEED_LE_BSWAP 0
-#endif
-
-/*
- * Byte Swap Helper
- *
- * This should all dead code away depending on the build host and
- * access type.
- */
-
-static inline uint64_t handle_bswap(uint64_t val, MemOp op)
-{
- if ((memop_big_endian(op) && NEED_BE_BSWAP) ||
- (!memop_big_endian(op) && NEED_LE_BSWAP)) {
- switch (op & MO_SIZE) {
- case MO_8: return val;
- case MO_16: return bswap16(val);
- case MO_32: return bswap32(val);
- case MO_64: return bswap64(val);
- default:
- g_assert_not_reached();
- }
- } else {
- return val;
- }
-}
-
/*
* Load Helpers
*
@@ -1306,10 +1274,8 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
}
}
- /* FIXME: io_readx ignores MO_BSWAP. */
- res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
- mmu_idx, addr, retaddr, access_type, op);
- return handle_bswap(res, op);
+ return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
+ mmu_idx, addr, retaddr, access_type, op);
}
/* Handle slow unaligned access (it spans two pages or IO). */
@@ -1552,10 +1518,8 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
}
}
- /* FIXME: io_writex ignores MO_BSWAP. */
io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
- handle_bswap(val, op),
- addr, retaddr, op);
+ val, addr, retaddr, op);
return;
}
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index ad06c12..84f820d 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -542,16 +542,15 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
val = pci_get_byte(buf);
break;
case 2:
- val = cpu_to_le16(pci_get_word(buf));
+ val = pci_get_word(buf);
break;
case 4:
- val = cpu_to_le32(pci_get_long(buf));
+ val = pci_get_long(buf);
break;
default:
/* As length is under guest control, handle illegal values. */
return;
}
- /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
}
@@ -576,7 +575,6 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
/* Make sure caller aligned buf properly */
assert(!(((uintptr_t)buf) & (len - 1)));
- /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
MEMTXATTRS_UNSPECIFIED);
switch (len) {
@@ -584,10 +582,10 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
pci_set_byte(buf, val);
break;
case 2:
- pci_set_word(buf, le16_to_cpu(val));
+ pci_set_word(buf, val);
break;
case 4:
- pci_set_long(buf, le32_to_cpu(val));
+ pci_set_long(buf, val);
break;
default:
/* As length is under guest control, handle illegal values. */
diff --git a/memory.c b/memory.c
index 01fd29d..ebe0066 100644
--- a/memory.c
+++ b/memory.c
@@ -343,32 +343,23 @@ static void flatview_simplify(FlatView *view)
}
}
-static bool memory_region_wrong_endianness(MemoryRegion *mr)
+static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- return mr->ops->endianness == MO_LE;
-#else
- return mr->ops->endianness == MO_BE;
-#endif
-}
-
-static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
-{
- if (memory_region_wrong_endianness(mr)) {
- switch (size) {
- case 1:
+ if ((op & MO_BSWAP) != mr->ops->endianness) {
+ switch (op & MO_SIZE) {
+ case MO_8:
break;
- case 2:
+ case MO_16:
*data = bswap16(*data);
break;
- case 4:
+ case MO_32:
*data = bswap32(*data);
break;
- case 8:
+ case MO_64:
*data = bswap64(*data);
break;
default:
- abort();
+ g_assert_not_reached();
}
}
}
@@ -1442,7 +1433,7 @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
}
r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
- adjust_endianness(mr, pval, size);
+ adjust_endianness(mr, pval, op);
return r;
}
@@ -1485,7 +1476,7 @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
return MEMTX_DECODE_ERROR;
}
- adjust_endianness(mr, &data, size);
+ adjust_endianness(mr, &data, op);
if ((!kvm_eventfds_enabled()) &&
memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
@@ -2331,7 +2322,7 @@ void memory_region_add_eventfd(MemoryRegion *mr,
}
if (size) {
- adjust_endianness(mr, &mrfd.data, size);
+ adjust_endianness(mr, &mrfd.data, size_memop(size));
}
memory_region_transaction_begin();
for (i = 0; i < mr->ioeventfd_nb; ++i) {
@@ -2366,7 +2357,7 @@ void memory_region_del_eventfd(MemoryRegion *mr,
unsigned i;
if (size) {
- adjust_endianness(mr, &mrfd.data, size);
+ adjust_endianness(mr, &mrfd.data, size_memop(size));
}
memory_region_transaction_begin();
for (i = 0; i < mr->ioeventfd_nb; ++i) {
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index 482e4b3..7b7f0c0 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,17 +37,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
r = memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian, attrs);
-#if defined(TARGET_WORDS_BIGENDIAN)
- if (endian == MO_LE) {
- val = bswap32(val);
- }
-#else
- if (endian == MO_BE) {
- val = bswap32(val);
- }
-#endif
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -113,17 +103,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
r = memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian, attrs);
-#if defined(TARGET_WORDS_BIGENDIAN)
- if (endian == MO_LE) {
- val = bswap64(val);
- }
-#else
- if (endian == MO_BE) {
- val = bswap64(val);
- }
-#endif
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -223,17 +203,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
r = memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian, attrs);
-#if defined(TARGET_WORDS_BIGENDIAN)
- if (endian == MO_LE) {
- val = bswap16(val);
- }
-#else
- if (endian == MO_BE) {
- val = bswap16(val);
- }
-#endif
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -335,17 +305,6 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (l < 4 || !memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
-
-#if defined(TARGET_WORDS_BIGENDIAN)
- if (endian == MO_LE) {
- val = bswap32(val);
- }
-#else
- if (endian == MO_BE) {
- val = bswap32(val);
- }
-#endif
- /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
r = memory_region_dispatch_write(mr, addr1, val, MO_32 | endian, attrs);
} else {
/* RAM case */
@@ -441,17 +400,6 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (l < 2 || !memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
-
-#if defined(TARGET_WORDS_BIGENDIAN)
- if (endian == MO_LE) {
- val = bswap16(val);
- }
-#else
- if (endian == MO_BE) {
- val = bswap16(val);
- }
-#endif
- /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
r = memory_region_dispatch_write(mr, addr1, val, MO_16 | endian, attrs);
} else {
/* RAM case */
@@ -515,17 +463,6 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (l < 8 || !memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
-
-#if defined(TARGET_WORDS_BIGENDIAN)
- if (endian == MO_LE) {
- val = bswap64(val);
- }
-#else
- if (endian == MO_BE) {
- val = bswap64(val);
- }
-#endif
- /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
r = memory_region_dispatch_write(mr, addr1, val, MO_64 | endian, attrs);
} else {
/* RAM case */
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 20295 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 39/42] cpu: TLB_FLAGS_MASK bit to force memory slow path
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (36 preceding siblings ...)
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path tony.nguyen
@ 2019-08-16 7:39 ` tony.nguyen
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 40/42] cputlb: Byte swap memory transaction attribute tony.nguyen
` (5 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:39 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1369 bytes --]
The fast path is taken when TLB_FLAGS_MASK is all zero.
TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,
there are no other side effects.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 536ea58..e496f99 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3))
/* Set if TLB entry must have MMU lookup repeated for every access */
#define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4))
+/* Set if TLB entry must take the slow path. */
+#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS - 5))
/* Use this mask to check interception with an alignment mask
* in a TCG backend.
*/
-#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
- | TLB_RECHECK)
+#define TLB_FLAGS_MASK \
+ (TLB_INVALID_MASK \
+ | TLB_NOTDIRTY \
+ | TLB_MMIO \
+ | TLB_RECHECK \
+ | TLB_FORCE_SLOW)
/**
* tlb_hit_page: return true if page aligned @addr is a hit against the
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 2927 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 40/42] cputlb: Byte swap memory transaction attribute
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (37 preceding siblings ...)
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 39/42] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
@ 2019-08-16 7:39 ` tony.nguyen
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 41/42] target/sparc: Add TLB entry with attributes tony.nguyen
` (4 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:39 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 2334 bytes --]
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 11 +++++++++++
include/exec/memattrs.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index bb2f55d..adfa4f2 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
*/
address |= TLB_RECHECK;
}
+ if (attrs.byte_swap) {
+ address |= TLB_FORCE_SLOW;
+ }
if (!memory_region_is_ram(section->mr) &&
!memory_region_is_romd(section->mr)) {
/* IO memory case */
@@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
@@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477..95f2d20 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
unsigned int user:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
+ /* Invert endianness for this page */
+ unsigned int byte_swap:1;
/*
* The following are target-specific page-table bits. These are not
* related to actual memory transactions at all. However, this structure
--
1.8.3.1
?
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* [Xen-devel] [Qemu-devel] [PATCH v7 41/42] target/sparc: Add TLB entry with attributes
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (38 preceding siblings ...)
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 40/42] cputlb: Byte swap memory transaction attribute tony.nguyen
@ 2019-08-16 7:39 ` tony.nguyen
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 42/42] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
` (3 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:39 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 5289 bytes --]
Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/mmu_helper.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index cbd1e91..826e14b 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -88,7 +88,7 @@ static const int perm_table[2][8] = {
};
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
- int *prot, int *access_index,
+ int *prot, int *access_index, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
@@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
target_ulong vaddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
+ MemTxAttrs attrs = {};
/*
* TODO: If we ever need tlb_vaddr_to_host for this target,
@@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
assert(!probe);
address &= TARGET_PAGE_MASK;
- error_code = get_physical_address(env, &paddr, &prot, &access_index,
+ error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
address, access_type,
mmu_idx, &page_size);
vaddr = address;
@@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
return 0;
}
-static int get_physical_address_data(CPUSPARCState *env,
- hwaddr *physical, int *prot,
+static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
+ int *prot, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx)
{
CPUState *cs = env_cpu(env);
@@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env,
return 1;
}
-static int get_physical_address_code(CPUSPARCState *env,
- hwaddr *physical, int *prot,
+static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
+ int *prot, MemTxAttrs *attrs,
target_ulong address, int mmu_idx)
{
CPUState *cs = env_cpu(env);
@@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env,
}
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
- int *prot, int *access_index,
+ int *prot, int *access_index, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
@@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
}
if (rw == 2) {
- return get_physical_address_code(env, physical, prot, address,
+ return get_physical_address_code(env, physical, prot, attrs, address,
mmu_idx);
} else {
- return get_physical_address_data(env, physical, prot, address, rw,
- mmu_idx);
+ return get_physical_address_data(env, physical, prot, attrs, address,
+ rw, mmu_idx);
}
}
@@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
target_ulong vaddr;
hwaddr paddr;
target_ulong page_size;
+ MemTxAttrs attrs = {};
int error_code = 0, prot, access_index;
address &= TARGET_PAGE_MASK;
- error_code = get_physical_address(env, &paddr, &prot, &access_index,
+ error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
address, access_type,
mmu_idx, &page_size);
if (likely(error_code == 0)) {
@@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context);
- tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
+ page_size);
return true;
}
if (probe) {
@@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
{
target_ulong page_size;
int prot, access_index;
+ MemTxAttrs attrs = {};
- return get_physical_address(env, phys, &prot, &access_index, addr, rw,
- mmu_idx, &page_size);
+ return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
+ rw, mmu_idx, &page_size);
}
#if defined(TARGET_SPARC64)
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 10800 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Xen-devel] [Qemu-devel] [PATCH v7 42/42] target/sparc: sun4u Invert Endian TTE bit
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (39 preceding siblings ...)
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 41/42] target/sparc: Add TLB entry with attributes tony.nguyen
@ 2019-08-16 7:39 ` tony.nguyen
2019-08-16 9:58 ` [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Philippe Mathieu-Daudé
` (2 subsequent siblings)
43 siblings, 0 replies; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 7:39 UTC (permalink / raw)
To: qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, philmd, amarkovic,
peter.chubb, aurelien, pburton, sagark, green, kraxel,
edgar.iglesias, gxt, robh, borntraeger, joel, antonynpavlov,
chouteau, balrogg, Andrew.Baumann, mreitz, walling,
dmitry.fleytman, mst, mark.cave-ayland, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, david,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 3055 bytes --]
This bit configures endianness of PCI MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.
Tested working on OpenBSD.
Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =)
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/sparc/cpu.h | 2 ++
target/sparc/mmu_helper.c | 8 +++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 1406f0b..c6bafa8 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -275,6 +275,7 @@ enum {
#define TTE_VALID_BIT (1ULL << 63)
#define TTE_NFO_BIT (1ULL << 60)
+#define TTE_IE_BIT (1ULL << 59)
#define TTE_USED_BIT (1ULL << 41)
#define TTE_LOCKED_BIT (1ULL << 6)
#define TTE_SIDEEFFECT_BIT (1ULL << 3)
@@ -291,6 +292,7 @@ enum {
#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
+#define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT)
#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 826e14b..77dc86a 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
int do_fault = 0;
+ if (TTE_IS_IE(env->dtlb[i].tte)) {
+ attrs->byte_swap = true;
+ }
+
/* access ok? */
/* multiple bits in SFSR.FT may be set on TT_DFAULT */
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
@@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env)
}
if (TTE_IS_VALID(env->dtlb[i].tte)) {
qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx"
- ", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
+ ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n",
i,
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
TTE_PA(env->dtlb[i].tte),
@@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env)
TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
TTE_IS_LOCKED(env->dtlb[i].tte) ?
"locked" : "unlocked",
+ TTE_IS_IE(env->dtlb[i].tte) ?
+ "yes" : "no",
env->dtlb[i].tag & (uint64_t)0x1fffULL,
TTE_IS_GLOBAL(env->dtlb[i].tte) ?
"global" : "local");
--
1.8.3.1
?
[-- Attachment #1.2: Type: text/html, Size: 6433 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (40 preceding siblings ...)
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 42/42] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
@ 2019-08-16 9:58 ` Philippe Mathieu-Daudé
2019-08-16 11:37 ` tony.nguyen
2019-08-16 11:43 ` David Gibson
[not found] ` <1565941032362.60179@bt.com>
2019-08-18 9:13 ` [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Richard Henderson
43 siblings, 2 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-08-16 9:58 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, balrogg, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, peter.chubb,
aurelien, pburton, sagark, green, kraxel, edgar.iglesias, gxt,
robh, borntraeger, joel, antonynpavlov, chouteau, lersek,
Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
pbonzini, stefanb
Hi Tony,
On 8/16/19 8:28 AM, tony.nguyen@bt.com wrote:
> This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.
>
> v7:
[...]
> - Re-declared many native endian devices as little or big endian. This is why
> v7 has +16 patches.
Why are you doing that? What is the rational?
Anyhow if this not required by your series, you should split it out of
it, and send it on your principal changes are merged.
I'm worried because this these new patches involve many subsystems (thus
maintainers) and reviewing them will now take a fair amount of time.
> For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
> targets from the set of target/hw/*/device.o.
>
> If the set of targets are all little or all big endian, re-declare
> the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
> respectively.
If only little endian targets use a device, that doesn't mean the device
is designed in little endian...
Then if a big endian target plan to use this device, it will require
more work and you might have introduced regressions...
I'm not sure this is a safe move.
> This *naive* deduction may result in genuinely native endian devices
> being incorrectly declared as little or big endian, but should not
> introduce regressions for current targets.
Regards,
Phil.
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 24/42] hw/isa: Declare device little or big endian
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 24/42] hw/isa: " tony.nguyen
@ 2019-08-16 10:01 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-08-16 10:01 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, balrogg, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, peter.chubb,
aurelien, pburton, sagark, green, kraxel, edgar.iglesias, gxt,
robh, borntraeger, joel, antonynpavlov, chouteau, lersek,
Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
pbonzini, stefanb
On 8/16/19 9:34 AM, tony.nguyen@bt.com wrote:
> For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
> targets from the set of target/hw/*/device.o.
>
> If the set of targets are all little or all big endian, re-declare
> the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
> respectively.
>
> This *naive* deduction may result in genuinely native endian devices
> being incorrectly declared as little or big endian, but should not
> introduce regressions for current targets.
>
> These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
> has a new target with an opposite endian or 2) someone informed knows
> better =)
>
> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
> ---
> hw/isa/vt82c686.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
> index 12c460590..adf65d3 100644
> --- a/hw/isa/vt82c686.c
> +++ b/hw/isa/vt82c686.c
> @@ -108,7 +108,7 @@ static uint64_t superio_ioport_readb(void *opaque,
> hwaddr addr, unsigned size)
> static const MemoryRegionOps superio_ops = {
> .read = superio_ioport_readb,
> .write = superio_ioport_writeb,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
Being ioport, one is probably OK.
> .impl = {
> .min_access_size = 1,
> .max_access_size = 1,
> --
> 1.8.3.1
>
>
>
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 25/42] hw/misc: Declare device little or big endian
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 25/42] hw/misc: " tony.nguyen
@ 2019-08-16 10:04 ` Philippe Mathieu-Daudé
2019-08-19 18:26 ` Paolo Bonzini
0 siblings, 1 reply; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-08-16 10:04 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, balrogg, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, peter.chubb,
aurelien, pburton, sagark, green, kraxel, edgar.iglesias, gxt,
robh, borntraeger, joel, antonynpavlov, chouteau, lersek,
Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
pbonzini, stefanb
On 8/16/19 9:34 AM, tony.nguyen@bt.com wrote:
> For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
> targets from the set of target/hw/*/device.o.
>
> If the set of targets are all little or all big endian, re-declare
> the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
> respectively.
>
> This *naive* deduction may result in genuinely native endian devices
> being incorrectly declared as little or big endian, but should not
> introduce regressions for current targets.
>
> These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
> has a new target with an opposite endian or 2) someone informed knows
> better =)
>
> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
> ---
> hw/misc/a9scu.c | 2 +-
> hw/misc/applesmc.c | 6 +++---
> hw/misc/arm11scu.c | 2 +-
> hw/misc/arm_l2x0.c | 2 +-
> hw/misc/puv3_pm.c | 2 +-
> 5 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
> index 4307f00..3de8cd3 100644
> --- a/hw/misc/a9scu.c
> +++ b/hw/misc/a9scu.c
> @@ -94,7 +94,7 @@ static void a9_scu_write(void *opaque, hwaddr offset,
> static const MemoryRegionOps a9_scu_ops = {
> .read = a9_scu_read,
> .write = a9_scu_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
Uh, I doubt that.
> };
>
> static void a9_scu_reset(DeviceState *dev)
> diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c
> index 2d7eb3c..6c91f29 100644
> --- a/hw/misc/applesmc.c
> +++ b/hw/misc/applesmc.c
> @@ -285,7 +285,7 @@ static void qdev_applesmc_isa_reset(DeviceState *dev)
> static const MemoryRegionOps applesmc_data_io_ops = {
> .write = applesmc_io_data_write,
> .read = applesmc_io_data_read,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl = {
> .min_access_size = 1,
> .max_access_size = 1,
> @@ -295,7 +295,7 @@ static const MemoryRegionOps applesmc_data_io_ops = {
> static const MemoryRegionOps applesmc_cmd_io_ops = {
> .write = applesmc_io_cmd_write,
> .read = applesmc_io_cmd_read,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl = {
> .min_access_size = 1,
> .max_access_size = 1,
> @@ -305,7 +305,7 @@ static const MemoryRegionOps applesmc_cmd_io_ops = {
> static const MemoryRegionOps applesmc_err_io_ops = {
> .write = applesmc_io_err_write,
> .read = applesmc_io_err_read,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl = {
> .min_access_size = 1,
> .max_access_size = 1,
Being ioport, this one might be OK.
> diff --git a/hw/misc/arm11scu.c b/hw/misc/arm11scu.c
> index 84275df..59fd7c0 100644
> --- a/hw/misc/arm11scu.c
> +++ b/hw/misc/arm11scu.c
> @@ -57,7 +57,7 @@ static void mpcore_scu_write(void *opaque, hwaddr offset,
> static const MemoryRegionOps mpcore_scu_ops = {
> .read = mpcore_scu_read,
> .write = mpcore_scu_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
I don't think so,
> };
>
> static void arm11_scu_realize(DeviceState *dev, Error **errp)
> diff --git a/hw/misc/arm_l2x0.c b/hw/misc/arm_l2x0.c
> index b88f40a..72ecf46 100644
> --- a/hw/misc/arm_l2x0.c
> +++ b/hw/misc/arm_l2x0.c
> @@ -157,7 +157,7 @@ static void l2x0_priv_reset(DeviceState *dev)
> static const MemoryRegionOps l2x0_mem_ops = {
> .read = l2x0_priv_read,
> .write = l2x0_priv_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
neither here, but Peter will confirm.
> };
>
> static void l2x0_priv_init(Object *obj)
> diff --git a/hw/misc/puv3_pm.c b/hw/misc/puv3_pm.c
> index b538b4a..cd82b69 100644
> --- a/hw/misc/puv3_pm.c
> +++ b/hw/misc/puv3_pm.c
> @@ -118,7 +118,7 @@ static const MemoryRegionOps puv3_pm_ops = {
> .min_access_size = 4,
> .max_access_size = 4,
> },
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
This one I can't tell.
> };
>
> static void puv3_pm_realize(DeviceState *dev, Error **errp)
> --
> 1.8.3.1
>
>
>
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: Declare device little or big endian
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: " tony.nguyen
@ 2019-08-16 10:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-08-16 10:06 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, balrogg, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, peter.chubb,
aurelien, pburton, sagark, green, kraxel, edgar.iglesias, gxt,
robh, borntraeger, joel, antonynpavlov, chouteau, lersek,
Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
pbonzini, stefanb
On 8/16/19 9:35 AM, tony.nguyen@bt.com wrote:
> For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
> targets from the set of target/hw/*/device.o.
>
> If the set of targets are all little or all big endian, re-declare
> the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
> respectively.
>
> This *naive* deduction may result in genuinely native endian devices
> being incorrectly declared as little or big endian, but should not
> introduce regressions for current targets.
>
> These devices should be re-declared as DEVICE_NATIVE_ENDIAN if 1) it
> has a new target with an opposite endian or 2) someone informed knows
> better =)
>
> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
> ---
> hw/pci-host/q35.c | 2 +-
> hw/pci-host/versatile.c | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index 0a010be..fd20f72 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -288,7 +288,7 @@ static void tseg_blackhole_write(void *opaque,
> hwaddr addr, uint64_t val,
> static const MemoryRegionOps tseg_blackhole_ops = {
> .read = tseg_blackhole_read,
> .write = tseg_blackhole_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
OK.
> .valid.min_access_size = 1,
> .valid.max_access_size = 4,
> .impl.min_access_size = 4,
> diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
> index 791b321..e7017f3 100644
> --- a/hw/pci-host/versatile.c
> +++ b/hw/pci-host/versatile.c
> @@ -240,7 +240,7 @@ static uint64_t pci_vpb_reg_read(void *opaque,
> hwaddr addr,
> static const MemoryRegionOps pci_vpb_reg_ops = {
> .read = pci_vpb_reg_read,
> .write = pci_vpb_reg_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4,
> @@ -306,7 +306,7 @@ static uint64_t pci_vpb_config_read(void *opaque,
> hwaddr addr,
> static const MemoryRegionOps pci_vpb_config_ops = {
> .read = pci_vpb_config_read,
> .write = pci_vpb_config_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
Eh hard to say, PCI is not clear about endianess...
> };
>
> static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
> --
> 1.8.3.1
>
>
>
>
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
[not found] ` <1565941032362.60179@bt.com>
@ 2019-08-16 10:12 ` Thomas Huth
2019-08-19 18:28 ` Paolo Bonzini
0 siblings, 1 reply; 60+ messages in thread
From: Thomas Huth @ 2019-08-16 10:12 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, philmd, green, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, peter.chubb, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, jan.kiszka,
aurelien, pburton, sagark, jasowang, kraxel, edgar.iglesias, gxt,
robh, lersek, borntraeger, joel, antonynpavlov, chouteau,
balrogg, Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
pbonzini, stefanb
On 8/16/19 9:37 AM, tony.nguyen@bt.com wrote:
> Simplify endianness comparisons with consistent use of the more
> expressive MemOp.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Acked-by: David Gibson <david@gibson.dropbear.id.au>
This patch is *huge*, more than 800kB. It keeps being stuck in the the
filter of the qemu-s390x list each time you send it. Please:
1) Try to break it up in more digestible pieces, e.g. change only one
subsystem at a time (this is also better reviewable by people who are
interested in one area)
2) Do not send HTML emails to the mailing list.
Thanks,
Thomas
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
2019-08-16 9:58 ` [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Philippe Mathieu-Daudé
@ 2019-08-16 11:37 ` tony.nguyen
2019-08-16 12:02 ` Peter Maydell
2019-08-16 11:43 ` David Gibson
1 sibling, 1 reply; 60+ messages in thread
From: tony.nguyen @ 2019-08-16 11:37 UTC (permalink / raw)
To: philmd, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, balrogg, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, peter.chubb,
aurelien, pburton, sagark, green, kraxel, edgar.iglesias, gxt,
robh, borntraeger, joel, antonynpavlov, chouteau, lersek,
Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
pbonzini, stefanb
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Hi Phillippe,
On 8/16/19 7:58 PM, Philippe Mathieu-Daudé wrote:
>On 8/16/19 8:28 AM, tony.nguyen@bt.com wrote:
>> This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.
>>
>> v7:
>[...]
>> - Re-declared many native endian devices as little or big endian. This is why
>> v7 has +16 patches.
>
>Why are you doing that? What is the rational?
While collapsing the byte swaps, it was suggested in patch #11 of v5 that
consistent use of MemOp simplified endian comparisons. This lead to the
deprecation of enum device_endian by MemOp.
As MO_TE is conditional upon NEED_CPU_H, the s/DEVICE_NATIVE_ENDIAN/MO_TE/
required changing some device object files from common-obj-* to obj-*. In patch
#15 of v6 Paolo noted that most devices should not of been DEVICE_NATIVE_ENDIAN
and hinted at a clean up.
The +16 patches in v7 is the clean up effort.
>Anyhow if this not required by your series, you should split it out of
>it, and send it on your principal changes are merged.
>I'm worried because this these new patches involve many subsystems (thus
>maintainers) and reviewing them will now take a fair amount of time.
Yes, lets split these patches out. They are very much a tangent to the series
purpose.
>> For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
>> targets from the set of target/hw/*/device.o.
>>
>> If the set of targets are all little or all big endian, re-declare
>> the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
>> respectively.
>
>If only little endian targets use a device, that doesn't mean the device
>is designed in little endian...
>
>Then if a big endian target plan to use this device, it will require
>more work and you might have introduced regressions...
>
>I'm not sure this is a safe move.
>
>> This *naive* deduction may result in genuinely native endian devices
>> being incorrectly declared as little or big endian, but should not
>> introduce regressions for current targets.
>
Roger. Evidently too naive. TBH, most devices I've never heard of...
Regards,
Tony
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
2019-08-16 9:58 ` [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Philippe Mathieu-Daudé
2019-08-16 11:37 ` tony.nguyen
@ 2019-08-16 11:43 ` David Gibson
1 sibling, 0 replies; 60+ messages in thread
From: David Gibson @ 2019-08-16 11:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, balrogg, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, peter.chubb, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, jan.kiszka,
aurelien, pburton, sagark, green, kraxel, edgar.iglesias, gxt,
robh, borntraeger, joel, antonynpavlov, chouteau, lersek,
Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, qemu-devel, jslaby, marex, proljc,
marcandre.lureau, alistair, paul.durrant, tony.nguyen,
xiaoguangrong.eric, huth, jcd, pbonzini, stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1614 bytes --]
On Fri, Aug 16, 2019 at 11:58:05AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Tony,
>
> On 8/16/19 8:28 AM, tony.nguyen@bt.com wrote:
> > This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.
> >
> > v7:
> [...]
> > - Re-declared many native endian devices as little or big endian. This is why
> > v7 has +16 patches.
>
> Why are you doing that? What is the rational?
>
> Anyhow if this not required by your series, you should split it out of
> it, and send it on your principal changes are merged.
> I'm worried because this these new patches involve many subsystems (thus
> maintainers) and reviewing them will now take a fair amount of time.
>
> > For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
> > targets from the set of target/hw/*/device.o.
> >
> > If the set of targets are all little or all big endian, re-declare
> > the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
> > respectively.
>
> If only little endian targets use a device, that doesn't mean the device
> is designed in little endian...
>
> Then if a big endian target plan to use this device, it will require
> more work and you might have introduced regressions...
Uh.. only if they make the version of the device on a big endian
target big endian. Which is a terrible idea - if you know a hardware
designer planning to do this, please slap them.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
2019-08-16 11:37 ` tony.nguyen
@ 2019-08-16 12:02 ` Peter Maydell
0 siblings, 0 replies; 60+ messages in thread
From: Peter Maydell @ 2019-08-16 12:02 UTC (permalink / raw)
To: tony.nguyen
Cc: KONRAD Frederic, Alberto Garcia, Qemu-block, Aleksandar Rikalo,
Halil Pasic, Hervé Poussineau, Anthony PERARD,
open list:X86, Laszlo Ersek, Jason Wang,
Jiří Pírko, Eduardo Habkost, Beniamino Galvani,
Eric Auger, Alex Williamson, Stefan Hajnoczi, John Snow,
Richard Henderson, Kevin Wolf, Andrew Jeffery, claudio.fontana,
Chris Wulff, Laurent Vivier, sundeep subbaraya, Michael Walle,
qemu-ppc, Bastian Koppelmann, Igor Mammedov, Fam Zheng,
David Hildenbrand, Palmer Dabbelt, BALATON Zoltan, Keith Busch,
Max Filippov, Hannes Reinecke, Stefano Stabellini,
Andrey Smirnov, Helge Deller, Magnus Damm, Marcel Apfelbaum,
Artyom Tarasenko, Corey Minyard, Stefan Weil, Yuval Shaia,
qemu-s390x, qemu-arm, Jan Kiszka, Cédric Le Goater,
Stafford Horne, open list:RISC-V, Igor Mitsyanko, Cornelia Huck,
Philippe Mathieu-Daudé,
Aleksandar Markovic, Peter Chubb, Aurelien Jarno, Paul Burton,
Sagar Karandikar, Anthony Green, Gerd Hoffmann,
Edgar E. Iglesias, Guan Xuetao, Rob Herring,
Christian Borntraeger, Joel Stanley, Antony Pavlov,
Fabien Chouteau, andrzej zaborowski, Andrew Baumann, Max Reitz,
Collin Walling, Dmitry Fleytman, Michael S. Tsirkin,
Mark Cave-Ayland, QEMU Developers, Jiri Slaby, Marek Vasut,
Jia Liu, Marc-André Lureau, Alistair Francis, Paul Durrant,
David Gibson, Xiao Guangrong, Thomas Huth,
Jean-Christophe DUBOIS, Paolo Bonzini, Stefan Berger
On Fri, 16 Aug 2019 at 12:37, <tony.nguyen@bt.com> wrote:
>
> Hi Phillippe,
>
> On 8/16/19 7:58 PM, Philippe Mathieu-Daudé wrote:
> >On 8/16/19 8:28 AM, tony.nguyen@bt.com wrote:
> >> For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
> >> targets from the set of target/hw/*/device.o.
> >>
> >> If the set of targets are all little or all big endian, re-declare
> >> the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
> >> respectively.
> >
> >If only little endian targets use a device, that doesn't mean the device
> >is designed in little endian...
> >
> >Then if a big endian target plan to use this device, it will require
> >more work and you might have introduced regressions...
> >
> >I'm not sure this is a safe move.
> >
> >> This *naive* deduction may result in genuinely native endian devices
> >> being incorrectly declared as little or big endian, but should not
> >> introduce regressions for current targets.
> >
>
> Roger. Evidently too naive. TBH, most devices I've never heard of...
OTOH it's worth noting that it's quite likely that most of
the implementations of these DEVICE_NATIVE_ENDIAN devices
picked it in an equally naive way, by just copying some other
device's code...
thanks
-- PMM
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
` (42 preceding siblings ...)
[not found] ` <1565941032362.60179@bt.com>
@ 2019-08-18 9:13 ` Richard Henderson
43 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2019-08-18 9:13 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: fam, peter.maydell, walling, cohuck, sagark, david, jasowang,
palmer, mark.cave-ayland, i.mitsyanko, keith.busch, jcmvbkbc,
frederic.konrad, dmitry.fleytman, kraxel, edgar.iglesias, gxt,
pburton, xiaoguangrong.eric, peter.chubb, philmd, robh, hare,
sstabellini, berto, chouteau, qemu-block, arikalo, jslaby,
deller, mst, magnus.damm, jcd, pasic, borntraeger, mreitz,
hpoussin, joel, anthony.perard, xen-devel, david, lersek, green,
atar4qemu, antonynpavlov, marex, jiri, ehabkost, minyard,
qemu-s390x, sw, alistair, yuval.shaia, b.galvani, eric.auger,
alex.williamson, qemu-arm, jan.kiszka, clg, stefanha,
marcandre.lureau, shorne, jsnow, rth, kwolf, qemu-riscv, proljc,
pbonzini, andrew, claudio.fontana, crwulff, laurent,
Andrew.Baumann, sundeep.lkml, andrew.smirnov, michael,
paul.durrant, qemu-ppc, huth, amarkovic, kbastian, imammedo,
aurelien, stefanb
On 8/16/19 7:28 AM, tony.nguyen@bt.com wrote:
> Tony Nguyen (42):
> configure: Define TARGET_ALIGNED_ONLY in configure
> tcg: TCGMemOp is now accelerator independent MemOp
> memory: Introduce size_memop
> target/mips: Access MemoryRegion with MemOp
> hw/s390x: Access MemoryRegion with MemOp
> hw/intc/armv7m_nic: Access MemoryRegion with MemOp
> hw/virtio: Access MemoryRegion with MemOp
> hw/vfio: Access MemoryRegion with MemOp
> exec: Access MemoryRegion with MemOp
> cputlb: Access MemoryRegion with MemOp
> memory: Access MemoryRegion with MemOp
> hw/s390x: Hard code size with MO_{8|16|32|64}
> target/mips: Hard code size with MO_{8|16|32|64}
> exec: Hard code size with MO_{8|16|32|64}
I have queued these 14 patches to tcg-next:
https://github.com/rth7680/qemu/tree/tcg-next
I agree with the downthread conversation with Phil that the middle device
patches should be split out to a different series.
I have some questions on some of the last few patches, and I don't know how
they would interact cherry-picking from those, so I've left them for now.
I had some trouble applying your patches, as they're encoded quoted-printable,
and "git am" doesn't like that. If possible, please use "git send-email" to
post your next patch set.
r~
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness tony.nguyen
@ 2019-08-18 12:22 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2019-08-18 12:22 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: fam, peter.maydell, walling, cohuck, sagark, david, jasowang,
palmer, mark.cave-ayland, i.mitsyanko, keith.busch, jcmvbkbc,
frederic.konrad, dmitry.fleytman, kraxel, edgar.iglesias, gxt,
pburton, xiaoguangrong.eric, peter.chubb, philmd, robh, hare,
sstabellini, berto, chouteau, qemu-block, arikalo, jslaby,
deller, mst, magnus.damm, jcd, pasic, borntraeger, mreitz,
hpoussin, joel, anthony.perard, xen-devel, david, lersek, green,
atar4qemu, antonynpavlov, marex, jiri, ehabkost, minyard,
qemu-s390x, sw, alistair, yuval.shaia, b.galvani, eric.auger,
alex.williamson, qemu-arm, jan.kiszka, clg, stefanha,
marcandre.lureau, shorne, jsnow, rth, kwolf, qemu-riscv, proljc,
pbonzini, andrew, claudio.fontana, crwulff, laurent,
Andrew.Baumann, sundeep.lkml, andrew.smirnov, michael,
paul.durrant, qemu-ppc, huth, amarkovic, kbastian, imammedo,
aurelien, stefanb
On 8/16/19 8:38 AM, tony.nguyen@bt.com wrote:
> Preparation for collapsing the two byte swaps adjust_endianness and
> handle_bswap into the former.
>
> Call memory_region_dispatch_{read|write} with endianness encoded into
> the "MemOp op" operand.
>
> This patch does not change any behaviour as
> memory_region_dispatch_{read|write} is yet to handle the endianness.
>
> Once it does handle endianness, callers with byte swaps can collapse
> them into adjust_endianness.
>
> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
> ---
> accel/tcg/cputlb.c | 6 ++++--
> exec.c | 5 +++--
> hw/intc/armv7m_nvic.c | 15 ++++++++-------
> hw/s390x/s390-pci-inst.c | 6 ++++--
> hw/vfio/pci-quirks.c | 5 +++--
> hw/virtio/virtio-pci.c | 6 ++++--
> memory_ldst.inc.c | 18 ++++++++++++------
> 7 files changed, 38 insertions(+), 23 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 6c83878..0aff6a3 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
> qemu_mutex_lock_iothread();
> locked = true;
> }
> - r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),
> + r = memory_region_dispatch_read(mr, mr_offset, &val,
> + size_memop(size) | MO_TE,
> iotlbentry->attrs);
> if (r != MEMTX_OK) {
> hwaddr physaddr = mr_offset +
> @@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
> qemu_mutex_lock_iothread();
> locked = true;
> }
> - r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
> + r = memory_region_dispatch_write(mr, mr_offset, val,
> + size_memop(size) | MO_TE,
> iotlbentry->attrs);
Ok. Conversion to target-endian via handle_bswap() in the callers.
> diff --git a/exec.c b/exec.c
> index 303f9a7..562fb5b 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -3335,7 +3335,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
> potential bugs */
> val = ldn_p(buf, l);
> result |= memory_region_dispatch_write(mr, addr1, val,
> - size_memop(l), attrs);
> + size_memop(l) | MO_TE,
> + attrs);
> } else {
> /* RAM case */
> ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
> @@ -3397,7 +3398,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
> release_lock |= prepare_mmio_access(mr);
> l = memory_access_size(mr, l, addr1);
> result |= memory_region_dispatch_read(mr, addr1, &val,
> - size_memop(l), attrs);
> + size_memop(l) | MO_TE, attrs);
> stn_p(buf, l, val);
Ok. Please add comments:
/*
* TODO: Merge bswap from ldn_p into memory_region_dispatch_write
* by using ldn_he_p and dropping MO_TE to get a host-endian value.
*/
and similar for the store.
This must be delayed until after patch 38, when the MO_BSWAP component of the
MemOp is operated on by memory_region_dispatch_*.
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2346,8 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
> if (attrs.secure) {
> /* S accesses to the alias act like NS accesses to the real region */
> attrs.secure = 0;
> - return memory_region_dispatch_write(mr, addr, value, size_memop(size),
> - attrs);
> + return memory_region_dispatch_write(mr, addr, value,
> + size_memop(size) | MO_TE, attrs);
> } else {
> /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> if (attrs.user) {
> @@ -2366,8 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
> if (attrs.secure) {
> /* S accesses to the alias act like NS accesses to the real region */
> attrs.secure = 0;
> - return memory_region_dispatch_read(mr, addr, data, size_memop(size),
> - attrs);
> + return memory_region_dispatch_read(mr, addr, data,
> + size_memop(size) | MO_TE, attrs);
> } else {
> /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> if (attrs.user) {
> @@ -2393,8 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
>
> /* Direct the access to the correct systick */
> mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> - return memory_region_dispatch_write(mr, addr, value, size_memop(size),
> - attrs);
> + return memory_region_dispatch_write(mr, addr, value,
> + size_memop(size) | MO_TE, attrs);
> }
>
> static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
> @@ -2406,7 +2406,8 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
>
> /* Direct the access to the correct systick */
> mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> - return memory_region_dispatch_read(mr, addr, data, size_memop(size), attrs);
> + return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
> + attrs);
> }
Ok.
>
> static const MemoryRegionOps nvic_systick_ops = {
> diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
> index 0e92a37..272cb28 100644
> --- a/hw/s390x/s390-pci-inst.c
> +++ b/hw/s390x/s390-pci-inst.c
> @@ -373,7 +373,8 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
> mr = pbdev->pdev->io_regions[pcias].memory;
> mr = s390_get_subregion(mr, offset, len);
> offset -= mr->addr;
> - return memory_region_dispatch_read(mr, offset, data, size_memop(len),
> + return memory_region_dispatch_read(mr, offset, data,
> + size_memop(len) | MO_LE,
> MEMTXATTRS_UNSPECIFIED);
> }
>
> @@ -472,7 +473,8 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
> mr = pbdev->pdev->io_regions[pcias].memory;
> mr = s390_get_subregion(mr, offset, len);
> offset -= mr->addr;
> - return memory_region_dispatch_write(mr, offset, data, size_memop(len),
> + return memory_region_dispatch_write(mr, offset, data,
> + size_memop(len) | MO_LE,
> MEMTXATTRS_UNSPECIFIED);
> }
How did you derive MO_LE here?
I realize that pci tends to imply LE, but this is called from
pcilg_service_call, which is an s390 instruction, Which normally implies BE.
>
> diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
> index d5c0268..53db1c3 100644
> --- a/hw/vfio/pci-quirks.c
> +++ b/hw/vfio/pci-quirks.c
> @@ -1072,7 +1072,8 @@ static void vfio_rtl8168_quirk_address_write(void *opaque, hwaddr addr,
>
> /* Write to the proper guest MSI-X table instead */
> memory_region_dispatch_write(&vdev->pdev.msix_table_mmio,
> - offset, val, size_memop(size),
> + offset, val,
> + size_memop(size) | MO_LE,
> MEMTXATTRS_UNSPECIFIED);
> }
> return; /* Do not write guest MSI-X data to hardware */
> @@ -1103,7 +1104,7 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *opaque,
> if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) {
> hwaddr offset = rtl->addr & 0xfff;
> memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset,
> - &data, size_memop(size),
> + &data, size_memop(size) | MO_LE,
> MEMTXATTRS_UNSPECIFIED);
> trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data);
> }
Hmm. We have .endianness = DEVICE_LITTLE_ENDIAN, so we probably already did
any bswap on input to this function. Surely any further swapping should be
suppressed. I assume MSI-X rtl8168 is only used by x86 guests, and we would
not notice a problem testing this on an x86 host.
> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
> index b929e44..ad06c12 100644
> --- a/hw/virtio/virtio-pci.c
> +++ b/hw/virtio/virtio-pci.c
> @@ -551,7 +551,8 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
> /* As length is under guest control, handle illegal values. */
> return;
> }
> - memory_region_dispatch_write(mr, addr, val, size_memop(len),
> + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
> + memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
> MEMTXATTRS_UNSPECIFIED);
> }
>
> @@ -575,7 +576,8 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
> /* Make sure caller aligned buf properly */
> assert(!(((uintptr_t)buf) & (len - 1)));
>
> - memory_region_dispatch_read(mr, addr, &val, size_memop(len),
> + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
> + memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
> MEMTXATTRS_UNSPECIFIED);
> switch (len) {
> case 1:
Ok, cpu_to_le32 etc above.
> diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
> index d08fc79..482e4b3 100644
> --- a/memory_ldst.inc.c
> +++ b/memory_ldst.inc.c
> @@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
> release_lock |= prepare_mmio_access(mr);
>
> /* I/O case */
> - r = memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs);
> + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
> + r = memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian, attrs);
> #if defined(TARGET_WORDS_BIGENDIAN)
> if (endian == MO_LE) {
> val = bswap32(val);
> @@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
> release_lock |= prepare_mmio_access(mr);
>
> /* I/O case */
> - r = memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs);
> + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
> + r = memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian, attrs);
> #if defined(TARGET_WORDS_BIGENDIAN)
> if (endian == MO_LE) {
> val = bswap64(val);
> @@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
> release_lock |= prepare_mmio_access(mr);
>
> /* I/O case */
> - r = memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs);
> + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */
> + r = memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian, attrs);
> #if defined(TARGET_WORDS_BIGENDIAN)
> if (endian == MO_LE) {
> val = bswap16(val);
> @@ -342,7 +345,8 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
> val = bswap32(val);
> }
> #endif
> - r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
> + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
> + r = memory_region_dispatch_write(mr, addr1, val, MO_32 | endian, attrs);
> } else {
> /* RAM case */
> ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
> @@ -447,7 +451,8 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
> val = bswap16(val);
> }
> #endif
> - r = memory_region_dispatch_write(mr, addr1, val, MO_16, attrs);
> + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
> + r = memory_region_dispatch_write(mr, addr1, val, MO_16 | endian, attrs);
> } else {
> /* RAM case */
> ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
> @@ -520,7 +525,8 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
> val = bswap64(val);
> }
> #endif
> - r = memory_region_dispatch_write(mr, addr1, val, MO_64, attrs);
> + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */
> + r = memory_region_dispatch_write(mr, addr1, val, MO_64 | endian, attrs);
Ok. Since you're splitting out the device changes, you'll need a conversion
function for now:
MemOp devend_memop(enum device_endian end)
{
static MemOp conv[] = {
[DEVICE_LITTLE_ENDIAN] = MO_LE,
[DEVICE_BIG_ENDIAN] = MO_BE,
[DEVICE_NATIVE_ENDIAN] = MO_TE,
[DEVICE_HOST_ENDIAN] = 0,
};
switch (end) {
case DEVICE_LITTLE_ENDIAN:
case DEVICE_BIG_ENDIAN:
case DEVICE_NATIVE_ENDIAN:
case DEVICE_HOST_ENDIAN:
return conv[end];
default:
g_assert_not_reached();
}
}
Probably declared in include/exec/memory.h and implemented in memory.c.
r~
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp tony.nguyen
@ 2019-08-18 12:37 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2019-08-18 12:37 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: fam, peter.maydell, walling, cohuck, sagark, david, jasowang,
palmer, mark.cave-ayland, i.mitsyanko, keith.busch, jcmvbkbc,
frederic.konrad, dmitry.fleytman, kraxel, edgar.iglesias, gxt,
pburton, xiaoguangrong.eric, peter.chubb, philmd, robh, hare,
sstabellini, berto, chouteau, qemu-block, arikalo, jslaby,
deller, mst, magnus.damm, jcd, pasic, borntraeger, mreitz,
hpoussin, joel, anthony.perard, xen-devel, david, lersek, green,
atar4qemu, antonynpavlov, marex, jiri, ehabkost, minyard,
qemu-s390x, sw, alistair, yuval.shaia, b.galvani, eric.auger,
alex.williamson, qemu-arm, jan.kiszka, clg, stefanha,
marcandre.lureau, shorne, jsnow, rth, kwolf, qemu-riscv, proljc,
pbonzini, andrew, claudio.fontana, crwulff, laurent,
Andrew.Baumann, sundeep.lkml, andrew.smirnov, michael,
paul.durrant, qemu-ppc, huth, amarkovic, kbastian, imammedo,
aurelien, stefanb
On 8/16/19 8:38 AM, tony.nguyen@bt.com wrote:
> static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
> TCGMemOpIdx oi, uintptr_t retaddr)
> {
> - return load_helper(env, addr, oi, retaddr, 1, false, false,
> - full_ldub_mmu);
> + return load_helper(env, addr, oi, retaddr, MO_8, false, full_ldub_mmu);
...
> void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
> TCGMemOpIdx oi, uintptr_t retaddr)
> {
> - store_helper(env, addr, val, oi, retaddr, 1, false);
> + store_helper(env, addr, val, oi, retaddr, MO_8);
> }
MO_UB.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path tony.nguyen
@ 2019-08-18 12:46 ` Richard Henderson
0 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2019-08-18 12:46 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: fam, peter.maydell, walling, cohuck, sagark, david, jasowang,
palmer, mark.cave-ayland, i.mitsyanko, keith.busch, jcmvbkbc,
frederic.konrad, dmitry.fleytman, kraxel, edgar.iglesias, gxt,
pburton, xiaoguangrong.eric, peter.chubb, philmd, robh, hare,
sstabellini, berto, chouteau, qemu-block, arikalo, jslaby,
deller, mst, magnus.damm, jcd, pasic, borntraeger, mreitz,
hpoussin, joel, anthony.perard, xen-devel, david, lersek, green,
atar4qemu, antonynpavlov, marex, jiri, ehabkost, minyard,
qemu-s390x, sw, alistair, yuval.shaia, b.galvani, eric.auger,
alex.williamson, qemu-arm, jan.kiszka, clg, stefanha,
marcandre.lureau, shorne, jsnow, rth, kwolf, qemu-riscv, proljc,
pbonzini, andrew, claudio.fontana, crwulff, laurent,
Andrew.Baumann, sundeep.lkml, andrew.smirnov, michael,
paul.durrant, qemu-ppc, huth, amarkovic, kbastian, imammedo,
aurelien, stefanb
On 8/16/19 8:38 AM, tony.nguyen@bt.com wrote:
> +static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
> {
> + if ((op & MO_BSWAP) != mr->ops->endianness) {
> + switch (op & MO_SIZE) {
You'll want to use devend_memop() here, as previously discussed.
> @@ -2331,7 +2322,7 @@ void memory_region_add_eventfd(MemoryRegion *mr,
> }
>
> if (size) {
> - adjust_endianness(mr, &mrfd.data, size);
> + adjust_endianness(mr, &mrfd.data, size_memop(size));
> }
> memory_region_transaction_begin();
> for (i = 0; i < mr->ioeventfd_nb; ++i) {
> @@ -2366,7 +2357,7 @@ void memory_region_del_eventfd(MemoryRegion *mr,
> unsigned i;
>
> if (size) {
> - adjust_endianness(mr, &mrfd.data, size);
> + adjust_endianness(mr, &mrfd.data, size_memop(size));
> }
> memory_region_transaction_begin();
> for (i = 0; i < mr->ioeventfd_nb; ++i) {
To preserve behaviour it would appear that these need MO_TE.
r~
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 11/42] memory: Access MemoryRegion with MemOp
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 11/42] memory: " tony.nguyen
@ 2019-08-18 21:44 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-08-18 21:44 UTC (permalink / raw)
To: tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, balrogg, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, peter.chubb,
aurelien, pburton, sagark, green, kraxel, edgar.iglesias, gxt,
robh, borntraeger, joel, antonynpavlov, chouteau, lersek,
Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
pbonzini, stefanb
On 8/16/19 9:30 AM, tony.nguyen@bt.com wrote:
> Convert memory_region_dispatch_{read|write} operand "unsigned size"
> into a "MemOp op".
>
> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/memop.h | 20 ++++++++++++++------
> include/exec/memory.h | 9 +++++----
> memory.c | 7 +++++--
> 3 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/include/exec/memop.h b/include/exec/memop.h
> index dfd76a1..0a610b7 100644
> --- a/include/exec/memop.h
> +++ b/include/exec/memop.h
> @@ -12,6 +12,8 @@
> #ifndef MEMOP_H
> #define MEMOP_H
>
> +#include "qemu/host-utils.h"
> +
> typedef enum MemOp {
> MO_8 = 0,
> MO_16 = 1,
> @@ -107,14 +109,20 @@ typedef enum MemOp {
> MO_SSIZE = MO_SIZE | MO_SIGN,
> } MemOp;
>
> +/* MemOp to size in bytes. */
> +static inline unsigned memop_size(MemOp op)
> +{
> + return 1 << (op & MO_SIZE);
> +}
> +
> /* Size in bytes to MemOp. */
> -static inline unsigned size_memop(unsigned size)
> +static inline MemOp size_memop(unsigned size)
> {
> - /*
> - * FIXME: No-op to aid conversion of
> memory_region_dispatch_{read|write}
> - * "unsigned size" operand into a "MemOp op".
> - */
> - return size;
> +#ifdef CONFIG_DEBUG_TCG
> + /* Power of 2 up to 8. */
> + assert((size & (size - 1)) == 0 && size >= 1 && size <= 8);
Easier to review as:
assert(is_power_of_2(size) && size <= 8);
(This can be cleaned later).
> +#endif
> + return ctz32(size);
> }
>
> #endif
> diff --git a/include/exec/memory.h b/include/exec/memory.h
> index bb0961d..975b86a 100644
> --- a/include/exec/memory.h
> +++ b/include/exec/memory.h
> @@ -19,6 +19,7 @@
> #include "exec/cpu-common.h"
> #include "exec/hwaddr.h"
> #include "exec/memattrs.h"
> +#include "exec/memop.h"
> #include "exec/ramlist.h"
> #include "qemu/queue.h"
> #include "qemu/int128.h"
> @@ -1731,13 +1732,13 @@ void mtree_info(bool flatview, bool
> dispatch_tree, bool owner);
> * @mr: #MemoryRegion to access
> * @addr: address within that region
> * @pval: pointer to uint64_t which the data is written to
> - * @size: size of the access in bytes
> + * @op: size, sign, and endianness of the memory operation
> * @attrs: memory transaction attributes to use for the access
> */
> MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
> hwaddr addr,
> uint64_t *pval,
> - unsigned size,
> + MemOp op,
> MemTxAttrs attrs);
> /**
> * memory_region_dispatch_write: perform a write directly to the specified
> @@ -1746,13 +1747,13 @@ MemTxResult
> memory_region_dispatch_read(MemoryRegion *mr,
> * @mr: #MemoryRegion to access
> * @addr: address within that region
> * @data: data to write
> - * @size: size of the access in bytes
> + * @op: size, sign, and endianness of the memory operation
> * @attrs: memory transaction attributes to use for the access
> */
> MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
> hwaddr addr,
> uint64_t data,
> - unsigned size,
> + MemOp op,
> MemTxAttrs attrs);
>
> /**
> diff --git a/memory.c b/memory.c
> index 5d8c9a9..89ea4fb 100644
> --- a/memory.c
> +++ b/memory.c
> @@ -1439,9 +1439,10 @@ static MemTxResult
> memory_region_dispatch_read1(MemoryRegion *mr,
> MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
> hwaddr addr,
> uint64_t *pval,
> - unsigned size,
> + MemOp op,
> MemTxAttrs attrs)
> {
> + unsigned size = memop_size(op);
> MemTxResult r;
>
> if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
> @@ -1483,9 +1484,11 @@ static bool
> memory_region_dispatch_write_eventfds(MemoryRegion *mr,
> MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
> hwaddr addr,
> uint64_t data,
> - unsigned size,
> + MemOp op,
> MemTxAttrs attrs)
> {
> + unsigned size = memop_size(op);
> +
> if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
> unassigned_mem_write(mr, addr, data, size);
> return MEMTX_DECODE_ERROR;
> --
> 1.8.3.1
>
>
>
>
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [PATCH v7 25/42] hw/misc: Declare device little or big endian
2019-08-16 10:04 ` Philippe Mathieu-Daudé
@ 2019-08-19 18:26 ` Paolo Bonzini
0 siblings, 0 replies; 60+ messages in thread
From: Paolo Bonzini @ 2019-08-19 18:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, tony.nguyen, qemu-devel
Cc: fam, peter.maydell, walling, dmitry.fleytman, sagark, mst, green,
palmer, mark.cave-ayland, balaton, keith.busch, jcmvbkbc,
frederic.konrad, kraxel, claudio.fontana, edgar.iglesias, mreitz,
pburton, marex, robh, hare, gxt, berto, proljc, qemu-block,
arikalo, jslaby, deller, david, magnus.damm, yuval.shaia, pasic,
borntraeger, hpoussin, joel, marcel.apfelbaum, anthony.perard,
marcandre.lureau, david, balrogg, jasowang, atar4qemu,
antonynpavlov, jiri, ehabkost, minyard, jcd, sw, alistair,
chouteau, b.galvani, eric.auger, alex.williamson, sstabellini,
jan.kiszka, clg, stefanha, imammedo, xen-devel, shorne,
andrew.smirnov, jsnow, rth, kwolf, qemu-s390x, qemu-arm,
xiaoguangrong.eric, qemu-riscv, andrew, lersek, crwulff, laurent,
Andrew.Baumann, sundeep.lkml, i.mitsyanko, michael, paul.durrant,
qemu-ppc, huth, amarkovic, kbastian, cohuck, peter.chubb,
aurelien, stefanb
On 16/08/19 12:04, Philippe Mathieu-Daudé wrote:
>> diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
>> index 4307f00..3de8cd3 100644
>> --- a/hw/misc/a9scu.c
>> +++ b/hw/misc/a9scu.c
>> @@ -94,7 +94,7 @@ static void a9_scu_write(void *opaque, hwaddr offset,
>> static const MemoryRegionOps a9_scu_ops = {
>> .read = a9_scu_read,
>> .write = a9_scu_write,
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> + .endianness = DEVICE_LITTLE_ENDIAN,
> Uh, I doubt that.
>
... why? :)
Remember that BE32 and BE8 ARM OSes still are "natively" little-endian.
Paolo
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
2019-08-16 10:12 ` [Xen-devel] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp Thomas Huth
@ 2019-08-19 18:28 ` Paolo Bonzini
2019-08-19 18:29 ` Paolo Bonzini
0 siblings, 1 reply; 60+ messages in thread
From: Paolo Bonzini @ 2019-08-19 18:28 UTC (permalink / raw)
To: Thomas Huth, tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, philmd, green, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, peter.chubb, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, jan.kiszka,
aurelien, pburton, sagark, jasowang, kraxel, edgar.iglesias, gxt,
robh, lersek, borntraeger, joel, antonynpavlov, chouteau,
balrogg, Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
stefanb
On 16/08/19 12:12, Thomas Huth wrote:
> This patch is *huge*, more than 800kB. It keeps being stuck in the the
> filter of the qemu-s390x list each time you send it. Please:
>
> 1) Try to break it up in more digestible pieces, e.g. change only one
> subsystem at a time (this is also better reviewable by people who are
> interested in one area)
This is not really possible, since the patch is basically a
search-and-replace. You could perhaps use some magic
("DEVICE_MEMOP_ENDIAN" or something like that) to allow a split, but it
would introduce more complication than anything else.
Agreed on the HTML though. :)
Paolo
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
2019-08-19 18:28 ` Paolo Bonzini
@ 2019-08-19 18:29 ` Paolo Bonzini
2019-08-19 21:01 ` [Xen-devel] [Qemu-devel] [qemu-s390x] " Richard Henderson
0 siblings, 1 reply; 60+ messages in thread
From: Paolo Bonzini @ 2019-08-19 18:29 UTC (permalink / raw)
To: Thomas Huth, tony.nguyen, qemu-devel
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, philmd, green, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, balaton, keith.busch, jcmvbkbc, hare, sstabellini,
andrew.smirnov, deller, magnus.damm, marcel.apfelbaum, atar4qemu,
minyard, sw, yuval.shaia, qemu-s390x, qemu-arm, peter.chubb, clg,
shorne, qemu-riscv, i.mitsyanko, cohuck, amarkovic, jan.kiszka,
aurelien, pburton, sagark, jasowang, kraxel, edgar.iglesias, gxt,
robh, lersek, borntraeger, joel, antonynpavlov, chouteau,
balrogg, Andrew.Baumann, mreitz, walling, dmitry.fleytman, mst,
mark.cave-ayland, jslaby, marex, proljc, marcandre.lureau,
alistair, paul.durrant, david, xiaoguangrong.eric, huth, jcd,
stefanb
On 19/08/19 20:28, Paolo Bonzini wrote:
> On 16/08/19 12:12, Thomas Huth wrote:
>> This patch is *huge*, more than 800kB. It keeps being stuck in the the
>> filter of the qemu-s390x list each time you send it. Please:
>>
>> 1) Try to break it up in more digestible pieces, e.g. change only one
>> subsystem at a time (this is also better reviewable by people who are
>> interested in one area)
>
> This is not really possible, since the patch is basically a
> search-and-replace. You could perhaps use some magic
> ("DEVICE_MEMOP_ENDIAN" or something like that) to allow a split, but it
> would introduce more complication than anything else.
I'm stupid, at this point of the series it _would_ be possible to split
the patch by subsystem. Still not sure it would be actually an advantage.
Paolo
> Agreed on the HTML though. :)
>
> Paolo
>
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [qemu-s390x] [PATCH v7 33/42] exec: Replace device_endian with MemOp
2019-08-19 18:29 ` Paolo Bonzini
@ 2019-08-19 21:01 ` Richard Henderson
2019-08-20 3:11 ` Edgar E. Iglesias
0 siblings, 1 reply; 60+ messages in thread
From: Richard Henderson @ 2019-08-19 21:01 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, tony.nguyen, qemu-devel
Cc: fam, peter.maydell, walling, cohuck, jan.kiszka, sagark, david,
green, palmer, mark.cave-ayland, i.mitsyanko, keith.busch,
jcmvbkbc, frederic.konrad, dmitry.fleytman, kraxel,
edgar.iglesias, gxt, pburton, xiaoguangrong.eric, marex, robh,
hare, sstabellini, berto, chouteau, qemu-block, arikalo, jslaby,
deller, mst, magnus.damm, lersek, pasic, borntraeger, mreitz,
hpoussin, joel, anthony.perard, xen-devel, david, philmd,
jasowang, atar4qemu, antonynpavlov, jiri, ehabkost, minyard,
qemu-s390x, sw, alistair, yuval.shaia, b.galvani, eric.auger,
alex.williamson, qemu-arm, peter.chubb, clg, stefanha,
marcandre.lureau, shorne, jsnow, rth, kwolf, qemu-riscv, proljc,
andrew, claudio.fontana, crwulff, laurent, Andrew.Baumann,
sundeep.lkml, andrew.smirnov, michael, paul.durrant, qemu-ppc,
huth, amarkovic, kbastian, imammedo, jcd, aurelien, stefanb
On 8/19/19 11:29 AM, Paolo Bonzini wrote:
> On 19/08/19 20:28, Paolo Bonzini wrote:
>> On 16/08/19 12:12, Thomas Huth wrote:
>>> This patch is *huge*, more than 800kB. It keeps being stuck in the the
>>> filter of the qemu-s390x list each time you send it. Please:
>>>
>>> 1) Try to break it up in more digestible pieces, e.g. change only one
>>> subsystem at a time (this is also better reviewable by people who are
>>> interested in one area)
>>
>> This is not really possible, since the patch is basically a
>> search-and-replace. You could perhaps use some magic
>> ("DEVICE_MEMOP_ENDIAN" or something like that) to allow a split, but it
>> would introduce more complication than anything else.
>
> I'm stupid, at this point of the series it _would_ be possible to split
> the patch by subsystem. Still not sure it would be actually an advantage.
It might be easier to review if we split by symbol, one rename per patch over
the entire code base.
r~
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Xen-devel] [Qemu-devel] [qemu-s390x] [PATCH v7 33/42] exec: Replace device_endian with MemOp
2019-08-19 21:01 ` [Xen-devel] [Qemu-devel] [qemu-s390x] " Richard Henderson
@ 2019-08-20 3:11 ` Edgar E. Iglesias
0 siblings, 0 replies; 60+ messages in thread
From: Edgar E. Iglesias @ 2019-08-20 3:11 UTC (permalink / raw)
To: Richard Henderson
Cc: frederic.konrad, berto, qemu-block, arikalo, pasic, hpoussin,
anthony.perard, xen-devel, lersek, jasowang, jiri, ehabkost,
b.galvani, eric.auger, alex.williamson, stefanha, jsnow, rth,
kwolf, andrew, claudio.fontana, crwulff, laurent, sundeep.lkml,
michael, qemu-ppc, kbastian, imammedo, fam, peter.maydell, david,
palmer, keith.busch, jcmvbkbc, hare, sstabellini, andrew.smirnov,
deller, magnus.damm, atar4qemu, Thomas Huth, minyard, sw,
yuval.shaia, qemu-s390x, qemu-arm, jan.kiszka, clg, shorne,
qemu-riscv, i.mitsyanko, cohuck, amarkovic, peter.chubb,
aurelien, pburton, sagark, green, kraxel, gxt, robh, borntraeger,
joel, antonynpavlov, chouteau, philmd, Andrew.Baumann, mreitz,
walling, dmitry.fleytman, mst, mark.cave-ayland, qemu-devel,
jslaby, marex, proljc, marcandre.lureau, alistair, paul.durrant,
david, tony.nguyen, xiaoguangrong.eric, huth, jcd, Paolo Bonzini,
stefanb
[-- Attachment #1.1: Type: text/plain, Size: 1262 bytes --]
On Mon, 19 Aug. 2019, 23:01 Richard Henderson, <richard.henderson@linaro.org>
wrote:
> On 8/19/19 11:29 AM, Paolo Bonzini wrote:
> > On 19/08/19 20:28, Paolo Bonzini wrote:
> >> On 16/08/19 12:12, Thomas Huth wrote:
> >>> This patch is *huge*, more than 800kB. It keeps being stuck in the the
> >>> filter of the qemu-s390x list each time you send it. Please:
> >>>
> >>> 1) Try to break it up in more digestible pieces, e.g. change only one
> >>> subsystem at a time (this is also better reviewable by people who are
> >>> interested in one area)
> >>
> >> This is not really possible, since the patch is basically a
> >> search-and-replace. You could perhaps use some magic
> >> ("DEVICE_MEMOP_ENDIAN" or something like that) to allow a split, but it
> >> would introduce more complication than anything else.
> >
> > I'm stupid, at this point of the series it _would_ be possible to split
> > the patch by subsystem. Still not sure it would be actually an
> advantage.
>
> It might be easier to review if we split by symbol, one rename per patch
> over
> the entire code base.
>
>
> r~
>
Or if we review your script (I assume this wasn't a manual change). I'm not
sure it's realistic to have review on the entire patch or patches.
Best regards,
Edgar
>
[-- Attachment #1.2: Type: text/html, Size: 2026 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
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^ permalink raw reply [flat|nested] 60+ messages in thread
end of thread, other threads:[~2019-08-20 3:12 UTC | newest]
Thread overview: 60+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-16 6:28 [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
2019-08-16 7:08 ` [Xen-devel] [Qemu-devel] [PATCH v7 01/42] configure: Define TARGET_ALIGNED_ONLY tony.nguyen
2019-08-16 7:26 ` [Xen-devel] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen
2019-08-16 7:27 ` [Xen-devel] [Qemu-devel] [PATCH v7 03/42] memory: Introduce size_memop tony.nguyen
2019-08-16 7:27 ` [Xen-devel] [Qemu-devel] [PATCH v7 04/42] target/mips: Access MemoryRegion with MemOp tony.nguyen
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 05/42] hw/s390x: " tony.nguyen
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 06/42] hw/intc/armv7m_nic: " tony.nguyen
2019-08-16 7:28 ` [Xen-devel] [Qemu-devel] [PATCH v7 07/42] hw/virtio: " tony.nguyen
2019-08-16 7:29 ` [Xen-devel] [Qemu-devel] [PATCH v7 08/42] hw/vfio: " tony.nguyen
2019-08-16 7:29 ` [Xen-devel] [Qemu-devel] [PATCH v7 09/42] exec: " tony.nguyen
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 10/42] cputlb: " tony.nguyen
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 11/42] memory: " tony.nguyen
2019-08-18 21:44 ` Philippe Mathieu-Daudé
2019-08-16 7:30 ` [Xen-devel] [Qemu-devel] [PATCH v7 12/42] hw/s390x: Hard code size with MO_{8|16|32|64} tony.nguyen
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 13/42] target/mips: " tony.nguyen
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 14/42] exec: " tony.nguyen
2019-08-16 7:31 ` [Xen-devel] [Qemu-devel] [PATCH v7 15/42] hw/audio: Declare device little or big endian tony.nguyen
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 16/42] hw/block: " tony.nguyen
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 17/42] hw/char: " tony.nguyen
2019-08-16 7:32 ` [Xen-devel] [Qemu-devel] [PATCH v7 18/42] hw/display: " tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 19/42] hw/dma: " tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 20/42] hw/gpio: " tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 21/42] hw/i2c: " tony.nguyen
2019-08-16 7:33 ` [Xen-devel] [Qemu-devel] [PATCH v7 22/42] hw/input: " tony.nguyen
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 23/42] hw/intc: " tony.nguyen
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 24/42] hw/isa: " tony.nguyen
2019-08-16 10:01 ` Philippe Mathieu-Daudé
2019-08-16 7:34 ` [Xen-devel] [Qemu-devel] [PATCH v7 25/42] hw/misc: " tony.nguyen
2019-08-16 10:04 ` Philippe Mathieu-Daudé
2019-08-19 18:26 ` Paolo Bonzini
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 26/42] hw/net: " tony.nguyen
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: " tony.nguyen
2019-08-16 10:06 ` Philippe Mathieu-Daudé
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 28/42] hw/sd: " tony.nguyen
2019-08-16 7:35 ` [Xen-devel] [Qemu-devel] [PATCH v7 29/42] hw/ssi: " tony.nguyen
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 30/42] hw/timer: " tony.nguyen
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 31/42] build: Correct non-common common-obj-* to obj-* tony.nguyen
2019-08-16 7:36 ` [Xen-devel] [Qemu-devel] [PATCH v7 32/42] exec: Map device_endian onto MemOp tony.nguyen
2019-08-16 7:37 ` [Xen-devel] [Qemu-devel] [PATCH v7 34/42] exec: Delete device_endian tony.nguyen
2019-08-16 7:37 ` [Xen-devel] [Qemu-devel] [PATCH v7 35/42] exec: Delete DEVICE_HOST_ENDIAN tony.nguyen
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness tony.nguyen
2019-08-18 12:22 ` Richard Henderson
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp tony.nguyen
2019-08-18 12:37 ` Richard Henderson
2019-08-16 7:38 ` [Xen-devel] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path tony.nguyen
2019-08-18 12:46 ` Richard Henderson
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 39/42] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 40/42] cputlb: Byte swap memory transaction attribute tony.nguyen
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 41/42] target/sparc: Add TLB entry with attributes tony.nguyen
2019-08-16 7:39 ` [Xen-devel] [Qemu-devel] [PATCH v7 42/42] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
2019-08-16 9:58 ` [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Philippe Mathieu-Daudé
2019-08-16 11:37 ` tony.nguyen
2019-08-16 12:02 ` Peter Maydell
2019-08-16 11:43 ` David Gibson
[not found] ` <1565941032362.60179@bt.com>
2019-08-16 10:12 ` [Xen-devel] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp Thomas Huth
2019-08-19 18:28 ` Paolo Bonzini
2019-08-19 18:29 ` Paolo Bonzini
2019-08-19 21:01 ` [Xen-devel] [Qemu-devel] [qemu-s390x] " Richard Henderson
2019-08-20 3:11 ` Edgar E. Iglesias
2019-08-18 9:13 ` [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Richard Henderson
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