From: "Jan Beulich" <JBeulich@suse.com>
To: Quan Xu <quan.xu@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>, Feng Wu <feng.wu@intel.com>,
George Dunlap <George.Dunlap@eu.citrix.com>,
Liu Jinsong <jinsong.liu@alibaba-inc.com>,
DarioFaggioli <dario.faggioli@citrix.com>,
"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>,
Jun Nakajima <jun.nakajima@intel.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Keir Fraser <keir@xen.org>
Subject: Re: [PATCH 1/2] IOMMU/MMU: Adjust top level functions for VT-d Device-TLB flush error.
Date: Fri, 18 Mar 2016 03:29:34 -0600 [thread overview]
Message-ID: <56EBD88E02000078000DE406@prv-mh.provo.novell.com> (raw)
In-Reply-To: <945CA011AD5F084CBEA3E851C0AB28894B867412@SHSMSX101.ccr.corp.intel.com>
>>> On 18.03.16 at 10:09, <quan.xu@intel.com> wrote:
> On March 18, 2016 4:20pm, <JBeulich@suse.com> wrote:
>> As you can infer form the reply I sent yesterday, you first need to settle on an
>> abstract model: What do failures mean? If, in the flush case, a timeout is going
>> to kill the domain anyway, then error handling can be lighter weight than if you
>> mean to try to keep the domain running. Of course in this context you also
>> should not forget that iommu_map_page() could already return errors prior to
>> your changes (most notably -ENOMEM, but at least the AMD side also produces
>> others, with -EFAULT generally being accompanied by domain_crash()). As
>> mentioned elsewhere - it seems extremely bogus that these errors weren't
>> check for from the beginning.
>>
> Jan, I am not familiar/confident enough to this single point, could you tell
> me more how to fix it?
Not sure what exactly you're asking for: As said, we first need to
settle on an abstract model. Do we want IOMMU mapping failures
to be fatal to the domain (perhaps with the exception of the
hardware one)? I think we do, and for the hardware domain we'd
do things on a best effort basis (always erring on the side of
unmapping). Which would probably mean crashing the domain
could be centralized in iommu_{,un}map_page(). How much roll
back would then still be needed in callers of these functions for
the hardware domain's sake would need to be seen.
So before you start coing, give others (namely but not limited to
VT-d, AMD IOMMU, other x86, and x86/mm maintainers) a chance
to voice differing opinions.
Jan
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next prev parent reply other threads:[~2016-03-18 9:29 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-17 6:54 [PATCH 0/2] Check VT-d Device-TLB flush error Quan Xu
2016-03-17 6:54 ` [PATCH 1/2] IOMMU/MMU: Adjust top level functions for " Quan Xu
2016-03-17 7:32 ` Tian, Kevin
2016-03-17 7:58 ` Jan Beulich
2016-03-17 8:00 ` Tian, Kevin
2016-03-17 12:30 ` George Dunlap
2016-03-17 12:33 ` George Dunlap
2016-03-18 3:19 ` Xu, Quan
2016-03-18 8:09 ` Jan Beulich
2016-03-24 6:45 ` Xu, Quan
2016-03-18 7:54 ` Xu, Quan
2016-03-18 8:19 ` Jan Beulich
2016-03-18 9:09 ` Xu, Quan
2016-03-18 9:29 ` Jan Beulich [this message]
2016-03-18 9:38 ` Dario Faggioli
2016-03-18 9:48 ` Jan Beulich
2016-03-21 6:18 ` Tian, Kevin
2016-03-21 12:22 ` Jan Beulich
2016-03-24 9:02 ` Xu, Quan
2016-03-24 9:58 ` Jan Beulich
2016-03-24 14:12 ` Xu, Quan
2016-03-24 14:37 ` Jan Beulich
2016-03-17 17:14 ` Jan Beulich
2016-03-28 3:33 ` Xu, Quan
2016-03-29 7:20 ` Jan Beulich
2016-03-30 2:28 ` Xu, Quan
2016-03-30 2:35 ` Xu, Quan
2016-03-30 8:05 ` Jan Beulich
2016-03-17 6:54 ` [PATCH 2/2] IOMMU/MMU: Adjust low " Quan Xu
2016-03-17 7:37 ` Tian, Kevin
2016-03-18 2:30 ` Xu, Quan
2016-03-18 8:06 ` Jan Beulich
2016-03-21 5:01 ` Tian, Kevin
2016-03-17 15:31 ` George Dunlap
2016-03-18 6:57 ` Xu, Quan
2016-03-18 10:20 ` Jan Beulich
2016-03-25 9:27 ` Xu, Quan
2016-03-29 7:36 ` Jan Beulich
2016-04-11 3:09 ` Xu, Quan
2016-04-11 3:27 ` Xu, Quan
2016-04-11 16:34 ` Jan Beulich
2016-04-12 1:09 ` Xu, Quan
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