Re: [PATCH 2/2] IOMMU/MMU: Adjust low level functions for VT-d Device-TLB flush error.

From: George Dunlap <George.Dunlap@eu.citrix.com>
To: Quan Xu <quan.xu@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>, Keir Fraser <keir@xen.org>,
	Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	Dario Faggioli <dario.faggioli@citrix.com>,
	"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>,
	Julien Grall <julien.grall@arm.com>,
	Stefano Stabellini <stefano.stabellini@citrix.com>,
	Jun Nakajima <jun.nakajima@intel.com>,
	Feng Wu <feng.wu@intel.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: [PATCH 2/2] IOMMU/MMU: Adjust low level functions for VT-d Device-TLB flush error.
Date: Thu, 17 Mar 2016 15:31:29 +0000	[thread overview]
Message-ID: <CAFLBxZZqY-fkNva-kfhOwsF9SLg2ePSdjEM9TiE40Uy5Lt1bWQ@mail.gmail.com> (raw)
In-Reply-To: <1458197676-60696-3-git-send-email-quan.xu@intel.com>

On Thu, Mar 17, 2016 at 6:54 AM, Quan Xu <quan.xu@intel.com> wrote:
> Current code would be panic(), when VT-d Device-TLB flush timed out.
> the panic() is going to be eliminated, so we must check all kinds of
> error and all the way up the call trees.
>
> Signed-off-by: Quan Xu <quan.xu@intel.com>
>
> CC: Jun Nakajima <jun.nakajima@intel.com>
> CC: Kevin Tian <kevin.tian@intel.com>
> CC: George Dunlap <george.dunlap@eu.citrix.com>
> CC: Keir Fraser <keir@xen.org>
> CC: Jan Beulich <jbeulich@suse.com>
> CC: Andrew Cooper <andrew.cooper3@citrix.com>
> CC: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> CC: Stefano Stabellini <stefano.stabellini@citrix.com>
> CC: Julien Grall <julien.grall@arm.com>
> CC: Feng Wu <feng.wu@intel.com>
> CC: Dario Faggioli <dario.faggioli@citrix.com>
> ---
>  xen/arch/x86/mm/p2m-ept.c                     |   2 +-
>  xen/drivers/passthrough/amd/iommu_init.c      |  12 ++-
>  xen/drivers/passthrough/amd/pci_amd_iommu.c   |   2 +-
>  xen/drivers/passthrough/arm/smmu.c            |  10 ++-
>  xen/drivers/passthrough/iommu.c               |  17 ++--
>  xen/drivers/passthrough/vtd/extern.h          |   2 +-
>  xen/drivers/passthrough/vtd/iommu.c           | 120 ++++++++++++++++++--------
>  xen/drivers/passthrough/vtd/quirks.c          |  26 +++---
>  xen/include/asm-x86/hvm/svm/amd-iommu-proto.h |   2 +-
>  xen/include/asm-x86/iommu.h                   |   2 +-
>  xen/include/xen/iommu.h                       |   6 +-
>  11 files changed, 133 insertions(+), 68 deletions(-)
>
> diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c
> index f9bcce7..fa6c710 100644
> --- a/xen/arch/x86/mm/p2m-ept.c
> +++ b/xen/arch/x86/mm/p2m-ept.c
> @@ -825,7 +825,7 @@ out:
>           need_modify_vtd_table )
>      {
>          if ( iommu_hap_pt_share )
> -            iommu_pte_flush(d, gfn, &ept_entry->epte, order, vtd_pte_present);
> +            rc = iommu_pte_flush(d, gfn, &ept_entry->epte, order, vtd_pte_present);

So this sort changes the meaning of the "rc" check near the end of the
function, when we check whether we want to update altp2m.

As it happens, I *think* it doesn't matter, because you can't have
altp2m and passthrough enabled at the same time, right?

If so, this at least merits a comment above the altp2m check; something like:

"NB that if altp2m is enabled, rc cannot be non-zero here due to
iommu_pte_flush, since you can't have altp2m and pass-through enabled
at the same time."

If you *can* have both altp2m and pass-through, then we need to make
sure that the altp2m gets updated when the hostp2m is updated, even if
the iommu flush fails.

 -George

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