* [PATCH v4 1/4] xen/arm: Change the variable type of cpu_logical_map to register_t
2016-05-31 2:54 [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Wei Chen
@ 2016-05-31 2:54 ` Wei Chen
2016-05-31 2:54 ` [PATCH v4 2/4] xen/arm: Make AFFINITY_MASK generate correct mask for level3 Wei Chen
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Wei Chen @ 2016-05-31 2:54 UTC (permalink / raw)
To: xen-devel; +Cc: julien.grall, sstabellini, Wei Chen, steve.capper
The cpu_logical_map is used to store CPU hardware ID from MPIDR_EL1 or
from CPU node of DT. Currently, the cpu_logical_map is using the u32 as
its variable type. It can work properly while Xen is running on ARM32,
because the hardware ID is 32-bits. While Xen is running on ARM64, the
hardware ID expands to 64-bits and then the cpu_logical_map will overflow.
Change the variable type of cpu_logical_map to register_t will make
cpu_logical_map to store hardware IDs correctly on ARM32 and ARM64.
Signed-off-by: Wei Chen <Wei.Chen@linaro.org>
Acked-by: Julien Grall <julien.grall@arm.com>
---
v3-->v4:
1. Add missed Acked-by tag.
v2-->v3:
1. Update verion number.
v1-->v2:
1. Fix typos in commit messages that were commented by Julien.
2. Add Julien's Acked-by.
---
xen/arch/arm/gic-v3.c | 2 +-
xen/arch/arm/smpboot.c | 13 +++++++------
xen/include/asm-arm/processor.h | 2 +-
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index a095064..9910877 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -674,7 +674,7 @@ static int __init gicv3_populate_rdist(void)
} while ( !(typer & GICR_TYPER_LAST) );
}
- dprintk(XENLOG_ERR, "GICv3: CPU%d: mpidr 0x%x has no re-distributor!\n",
+ dprintk(XENLOG_ERR, "GICv3: CPU%d: mpidr 0x%"PRIregister" has no re-distributor!\n",
smp_processor_id(), cpu_logical_map(smp_processor_id()));
return -ENODEV;
diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
index c5109bf..ba83406 100644
--- a/xen/arch/arm/smpboot.c
+++ b/xen/arch/arm/smpboot.c
@@ -40,7 +40,7 @@ cpumask_t cpu_possible_map;
struct cpuinfo_arm cpu_data[NR_CPUS];
/* CPU logical map: map xen cpuid to an MPIDR */
-u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
+register_t __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
/* Fake one node for now. See also include/asm-arm/numa.h */
nodemask_t __read_mostly node_online_map = { { [0] = 1UL } };
@@ -100,7 +100,7 @@ static void __init dt_smp_init_cpus(void)
struct dt_device_node *cpu;
unsigned int i, j;
unsigned int cpuidx = 1;
- static u32 tmp_map[NR_CPUS] __initdata =
+ static register_t tmp_map[NR_CPUS] __initdata =
{
[0 ... NR_CPUS - 1] = MPIDR_INVALID
};
@@ -120,7 +120,8 @@ static void __init dt_smp_init_cpus(void)
{
const __be32 *prop;
u64 addr;
- u32 reg_len, hwid;
+ u32 reg_len;
+ register_t hwid;
if ( !dt_device_type_is_equal(cpu, "cpu") )
continue;
@@ -160,7 +161,7 @@ static void __init dt_smp_init_cpus(void)
*/
if ( hwid & ~MPIDR_HWID_MASK )
{
- printk(XENLOG_WARNING "cpu node `%s`: invalid hwid value (0x%x)\n",
+ printk(XENLOG_WARNING "cpu node `%s`: invalid hwid value (0x%"PRIregister")\n",
dt_node_full_name(cpu), hwid);
continue;
}
@@ -176,7 +177,7 @@ static void __init dt_smp_init_cpus(void)
if ( tmp_map[j] == hwid )
{
printk(XENLOG_WARNING
- "cpu node `%s`: duplicate /cpu reg properties %"PRIx32" in the DT\n",
+ "cpu node `%s`: duplicate /cpu reg properties %"PRIregister" in the DT\n",
dt_node_full_name(cpu), hwid);
break;
}
@@ -211,7 +212,7 @@ static void __init dt_smp_init_cpus(void)
if ( (rc = arch_cpu_init(i, cpu)) < 0 )
{
- printk("cpu%d init failed (hwid %x): %d\n", i, hwid, rc);
+ printk("cpu%d init failed (hwid %"PRIregister"): %d\n", i, hwid, rc);
tmp_map[i] = MPIDR_INVALID;
}
else
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 6789cd0..7de9c8e 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -348,7 +348,7 @@ extern void identify_cpu(struct cpuinfo_arm *);
extern struct cpuinfo_arm cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
-extern u32 __cpu_logical_map[];
+extern register_t __cpu_logical_map[];
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
/* HSR data abort size definition */
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v4 2/4] xen/arm: Make AFFINITY_MASK generate correct mask for level3
2016-05-31 2:54 [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Wei Chen
2016-05-31 2:54 ` [PATCH v4 1/4] xen/arm: Change the variable type of cpu_logical_map to register_t Wei Chen
@ 2016-05-31 2:54 ` Wei Chen
2016-05-31 2:54 ` [PATCH v4 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64 Wei Chen
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Wei Chen @ 2016-05-31 2:54 UTC (permalink / raw)
To: xen-devel; +Cc: julien.grall, sstabellini, Wei Chen, steve.capper
The original affinity shift bits algorithm in AFFINITY_MASK is buggy,
it could not generate correct affinity shift bits of level3.
The macro MPIDR_LEVEL_SHIFT can calculate level3 affinity shift bits
correctly. We use this macro in AFFINITY_MASK to generate correct
mask for level3.
Signed-off-by: Wei Chen <Wei.Chen@linaro.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
v3-->v4:
Add missed Reviewed-by tag.
v2-->v3:
Update version numnber.
v1-->v2:
Add Julien's reviewed-by.
---
xen/include/asm-arm/processor.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 7de9c8e..b4cce7e 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -21,7 +21,6 @@
#define MPIDR_HWID_MASK _AC(0xffffff,U)
#define MPIDR_INVALID (~MPIDR_HWID_MASK)
#define MPIDR_LEVEL_BITS (8)
-#define AFFINITY_MASK(level) ~((_AC(0x1,U) << ((level) * MPIDR_LEVEL_BITS)) - 1)
/*
@@ -37,6 +36,8 @@
#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
+#define AFFINITY_MASK(level) ~((_AC(0x1,UL) << MPIDR_LEVEL_SHIFT(level)) - 1)
+
/* TTBCR Translation Table Base Control Register */
#define TTBCR_EAE _AC(0x80000000,U)
#define TTBCR_N_MASK _AC(0x07,U)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v4 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64
2016-05-31 2:54 [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Wei Chen
2016-05-31 2:54 ` [PATCH v4 1/4] xen/arm: Change the variable type of cpu_logical_map to register_t Wei Chen
2016-05-31 2:54 ` [PATCH v4 2/4] xen/arm: Make AFFINITY_MASK generate correct mask for level3 Wei Chen
@ 2016-05-31 2:54 ` Wei Chen
2016-05-31 10:01 ` Julien Grall
2016-05-31 2:54 ` [PATCH v4 4/4] xen/arm: arm64: Remove MPIDR multiprocessing extensions check Wei Chen
2016-06-01 9:29 ` [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Stefano Stabellini
4 siblings, 1 reply; 10+ messages in thread
From: Wei Chen @ 2016-05-31 2:54 UTC (permalink / raw)
To: xen-devel; +Cc: julien.grall, sstabellini, Wei Chen, steve.capper
Currently, MPIDR_HWID_MASK is using the bit definition of AArch32
MPIDR register. But from D7.2.67 of ARM ARM (DDI 0487A.i) we can see
there are 4 levels of affinity on AArch64 whilst AArch32 has only 3.
So, this value is not correct when Xen is running on AArch64.
Now, we use the value 0xff00ffffff for this macro on AArch64. But
neither of this value and its bitwise invert value can be used in mov
instruction with the encoding of {imm16:shift} or {imms:immr}. So we
have to use ldr to load the bitwise invert value to register.
The details of mov immediate encoding are listed in C4.2.5 of ARM ARM
(DDI 0487A.i).
Signed-off-by: Wei Chen <Wei.Chen@linaro.org>
---
v3-->v4:
1. Update version number.
v2-->v3:
1. Add version information of mentioned ARM ARM.
v1-->v2: Address Julien's comments
1. Fix typos in commit messages.
2. Explain valid MPIDR_HWID_MASK value in AArch64.
3. Simply explain mov immediate encoding.
---
xen/arch/arm/arm64/head.S | 2 +-
xen/include/asm-arm/processor.h | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index d5831f2..3090beb 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -270,7 +270,7 @@ common_start:
tbz x0, _MPIDR_SMP, 1f /* Multiprocessor extension not supported? */
tbnz x0, _MPIDR_UP, 1f /* Uniprocessor system? */
- mov x13, #(~MPIDR_HWID_MASK)
+ ldr x13, =(~MPIDR_HWID_MASK)
bic x24, x0, x13 /* Mask out flags to get CPU ID */
1:
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index b4cce7e..284ad6a 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -18,7 +18,11 @@
#define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP)
#define MPIDR_AFF0_SHIFT (0)
#define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
+#ifdef CONFIG_ARM_64
+#define MPIDR_HWID_MASK _AC(0xff00ffffff,UL)
+#else
#define MPIDR_HWID_MASK _AC(0xffffff,U)
+#endif
#define MPIDR_INVALID (~MPIDR_HWID_MASK)
#define MPIDR_LEVEL_BITS (8)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v4 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64
2016-05-31 2:54 ` [PATCH v4 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64 Wei Chen
@ 2016-05-31 10:01 ` Julien Grall
0 siblings, 0 replies; 10+ messages in thread
From: Julien Grall @ 2016-05-31 10:01 UTC (permalink / raw)
To: Wei Chen, xen-devel; +Cc: sstabellini, steve.capper
Hi Wei,
On 31/05/16 03:54, Wei Chen wrote:
> Currently, MPIDR_HWID_MASK is using the bit definition of AArch32
> MPIDR register. But from D7.2.67 of ARM ARM (DDI 0487A.i) we can see
> there are 4 levels of affinity on AArch64 whilst AArch32 has only 3.
> So, this value is not correct when Xen is running on AArch64.
>
> Now, we use the value 0xff00ffffff for this macro on AArch64. But
> neither of this value and its bitwise invert value can be used in mov
> instruction with the encoding of {imm16:shift} or {imms:immr}. So we
> have to use ldr to load the bitwise invert value to register.
>
> The details of mov immediate encoding are listed in C4.2.5 of ARM ARM
> (DDI 0487A.i).
>
> Signed-off-by: Wei Chen <Wei.Chen@linaro.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Regards,
> ---
> v3-->v4:
> 1. Update version number.
>
> v2-->v3:
> 1. Add version information of mentioned ARM ARM.
>
> v1-->v2: Address Julien's comments
> 1. Fix typos in commit messages.
> 2. Explain valid MPIDR_HWID_MASK value in AArch64.
> 3. Simply explain mov immediate encoding.
> ---
> xen/arch/arm/arm64/head.S | 2 +-
> xen/include/asm-arm/processor.h | 4 ++++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index d5831f2..3090beb 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -270,7 +270,7 @@ common_start:
> tbz x0, _MPIDR_SMP, 1f /* Multiprocessor extension not supported? */
> tbnz x0, _MPIDR_UP, 1f /* Uniprocessor system? */
>
> - mov x13, #(~MPIDR_HWID_MASK)
> + ldr x13, =(~MPIDR_HWID_MASK)
> bic x24, x0, x13 /* Mask out flags to get CPU ID */
> 1:
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index b4cce7e..284ad6a 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -18,7 +18,11 @@
> #define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP)
> #define MPIDR_AFF0_SHIFT (0)
> #define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
> +#ifdef CONFIG_ARM_64
> +#define MPIDR_HWID_MASK _AC(0xff00ffffff,UL)
> +#else
> #define MPIDR_HWID_MASK _AC(0xffffff,U)
> +#endif
> #define MPIDR_INVALID (~MPIDR_HWID_MASK)
> #define MPIDR_LEVEL_BITS (8)
>
>
--
Julien Grall
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 4/4] xen/arm: arm64: Remove MPIDR multiprocessing extensions check
2016-05-31 2:54 [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Wei Chen
` (2 preceding siblings ...)
2016-05-31 2:54 ` [PATCH v4 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64 Wei Chen
@ 2016-05-31 2:54 ` Wei Chen
2016-06-01 9:29 ` [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Stefano Stabellini
4 siblings, 0 replies; 10+ messages in thread
From: Wei Chen @ 2016-05-31 2:54 UTC (permalink / raw)
To: xen-devel; +Cc: julien.grall, sstabellini, Wei Chen, steve.capper
In AArch32, MPIDR bit 31 is defined as multiprocessing extensions bit.
But in AArch64, this bit is always RES1. So the value check for this
bit is no longer necessary in AArch64.
Signed-off-by: Wei Chen <Wei.Chen@linaro.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
v3-->v4:
1. Add missed Reviewed-by tag.
v2--v3:
1. Fix a typo in commit messages.
2. Add Julien's Reviewed-by.
v1-->v2:
Make clear the status of MPIDR.SMP bit in AArch32 and AArch64.
---
xen/arch/arm/arm64/head.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 3090beb..91e2817 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -267,7 +267,6 @@ common_start:
* find that multiprocessor extensions are
* present and the system is SMP */
mrs x0, mpidr_el1
- tbz x0, _MPIDR_SMP, 1f /* Multiprocessor extension not supported? */
tbnz x0, _MPIDR_UP, 1f /* Uniprocessor system? */
ldr x13, =(~MPIDR_HWID_MASK)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits
2016-05-31 2:54 [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Wei Chen
` (3 preceding siblings ...)
2016-05-31 2:54 ` [PATCH v4 4/4] xen/arm: arm64: Remove MPIDR multiprocessing extensions check Wei Chen
@ 2016-06-01 9:29 ` Stefano Stabellini
2016-06-01 9:37 ` Wei Liu
2016-06-01 10:37 ` Julien Grall
4 siblings, 2 replies; 10+ messages in thread
From: Stefano Stabellini @ 2016-06-01 9:29 UTC (permalink / raw)
To: Wei Chen; +Cc: julien.grall, sstabellini, wei.liu2, steve.capper, xen-devel
Hi Wei Liu, Julien,
this series is a bug fix. I think it should go in Xen 4.7, do you agree?
On Tue, 31 May 2016, Wei Chen wrote:
> bits are expanded to 64-bits. But Xen 64-bit ARM code treats this it
> as 32-bit register.
> We have to provide correct accessing to this register to avoid
> unexpected issues that is caused by incorrect MPIDR value.
>
> Wei Chen (4):
> xen/arm: Change the variable type of cpu_logical_map to register_t
> xen/arm: Make AFFINITY_MASK generate correct mask for level3
> xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64
> xen/arm: arm64: Remove MPIDR multiprocessing extensions check
>
> xen/arch/arm/arm64/head.S | 3 +--
> xen/arch/arm/gic-v3.c | 2 +-
> xen/arch/arm/smpboot.c | 13 +++++++------
> xen/include/asm-arm/processor.h | 9 +++++++--
> 4 files changed, 16 insertions(+), 11 deletions(-)
>
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits
2016-06-01 9:29 ` [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Stefano Stabellini
@ 2016-06-01 9:37 ` Wei Liu
2016-06-01 10:37 ` Julien Grall
1 sibling, 0 replies; 10+ messages in thread
From: Wei Liu @ 2016-06-01 9:37 UTC (permalink / raw)
To: Stefano Stabellini
Cc: julien.grall, xen-devel, wei.liu2, steve.capper, Wei Chen
On Wed, Jun 01, 2016 at 10:29:56AM +0100, Stefano Stabellini wrote:
> Hi Wei Liu, Julien,
>
> this series is a bug fix. I think it should go in Xen 4.7, do you agree?
>
Yes
Release-acked-by: Wei Liu <wei.liu2@citrix.com>
>
> On Tue, 31 May 2016, Wei Chen wrote:
> > bits are expanded to 64-bits. But Xen 64-bit ARM code treats this it
> > as 32-bit register.
> > We have to provide correct accessing to this register to avoid
> > unexpected issues that is caused by incorrect MPIDR value.
> >
> > Wei Chen (4):
> > xen/arm: Change the variable type of cpu_logical_map to register_t
> > xen/arm: Make AFFINITY_MASK generate correct mask for level3
> > xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64
> > xen/arm: arm64: Remove MPIDR multiprocessing extensions check
> >
> > xen/arch/arm/arm64/head.S | 3 +--
> > xen/arch/arm/gic-v3.c | 2 +-
> > xen/arch/arm/smpboot.c | 13 +++++++------
> > xen/include/asm-arm/processor.h | 9 +++++++--
> > 4 files changed, 16 insertions(+), 11 deletions(-)
> >
> > --
> > 2.7.4
> >
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits
2016-06-01 9:29 ` [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Stefano Stabellini
2016-06-01 9:37 ` Wei Liu
@ 2016-06-01 10:37 ` Julien Grall
2016-06-01 11:49 ` Edgar E. Iglesias
1 sibling, 1 reply; 10+ messages in thread
From: Julien Grall @ 2016-06-01 10:37 UTC (permalink / raw)
To: Stefano Stabellini, Wei Chen
Cc: edgar.iglesias, steve.capper, wei.liu2, xen-devel
On 01/06/16 10:29, Stefano Stabellini wrote:
> Hi Wei Liu, Julien,
Hi Stefano,
>
> this series is a bug fix. I think it should go in Xen 4.7, do you agree?
Some changes in this series impact the emulation of PSCI for guest (see
target_affinity_mask in vpsci.c). Looking at the code again, they should
be low risk as Xen only supports AFF0 and AFF1 for the vmpidr.
I think it should be fine to go in Xen 4.7, however osstest will not be
able to catch any possible regression due to lack of ARM64 hardware in
the colo.
I just tested on Juno and I did not find any regression. I think Wei
tested on Overdrive (?). Edgar, can you give it a go on the xilinx board?
Regards,
--
Julien Grall
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits
2016-06-01 10:37 ` Julien Grall
@ 2016-06-01 11:49 ` Edgar E. Iglesias
0 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2016-06-01 11:49 UTC (permalink / raw)
To: Julien Grall
Cc: wei.liu2, Stefano Stabellini, xen-devel, steve.capper, Wei Chen
On Wed, Jun 01, 2016 at 11:37:55AM +0100, Julien Grall wrote:
>
>
> On 01/06/16 10:29, Stefano Stabellini wrote:
> >Hi Wei Liu, Julien,
>
> Hi Stefano,
>
> >
> >this series is a bug fix. I think it should go in Xen 4.7, do you agree?
>
> Some changes in this series impact the emulation of PSCI for guest (see
> target_affinity_mask in vpsci.c). Looking at the code again, they should be
> low risk as Xen only supports AFF0 and AFF1 for the vmpidr.
>
> I think it should be fine to go in Xen 4.7, however osstest will not be able
> to catch any possible regression due to lack of ARM64 hardware in the colo.
>
> I just tested on Juno and I did not find any regression. I think Wei tested
> on Overdrive (?). Edgar, can you give it a go on the xilinx board?
>
Hi Julien,
Yes, I gave it a try on the ZCU102 and things are working fine.
Started dom0 in SMP + a couple of SMP guests.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Best regards,
Edgar
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