* [PATCH] x86/apic: Drop workarounds for Pentium/82489DX erratum
@ 2017-06-01 14:51 Andrew Cooper
2017-06-06 15:18 ` Jan Beulich
2017-06-06 16:01 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Andrew Cooper
0 siblings, 2 replies; 9+ messages in thread
From: Andrew Cooper @ 2017-06-01 14:51 UTC (permalink / raw)
To: Xen-devel; +Cc: Andrew Cooper, Jan Beulich
CONFIG_X86_GOOD_APIC is unconditionally selected for 64bit builds. Drop the
related infrastructure including apic_{read,write}_around(), the former of
which had no effect, and the latter which was an alias of apic_write().
No functional change, as confirmed by diffing the before/after disassembly.
(Three __LINE__ numbers are different, but they are `mov $imm, %reg` as part
of a dprintk() call.)
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
---
xen/arch/x86/apic.c | 72 ++++++++++++++++++-------------------
xen/arch/x86/cpu/mcheck/mce_intel.c | 8 ++---
xen/arch/x86/cpu/vpmu.c | 5 ++-
xen/arch/x86/genapic/delivery.c | 8 ++---
xen/arch/x86/io_apic.c | 14 ++++----
xen/arch/x86/smp.c | 10 +++---
xen/arch/x86/smpboot.c | 3 --
xen/include/asm-x86/apic.h | 19 +---------
xen/include/asm-x86/config.h | 1 -
9 files changed, 58 insertions(+), 82 deletions(-)
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 1dd188a..a5ae4b6 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -157,7 +157,7 @@ void clear_local_APIC(void)
maxlvt = get_maxlvt();
/* Work around AMD Erratum 411. This is a nice thing to do anyway. */
- apic_write_around(APIC_TMICT, 0);
+ apic_write(APIC_TMICT, 0);
/*
* Masking an LVT entry on a P6 can trigger a local APIC error
@@ -165,52 +165,52 @@ void clear_local_APIC(void)
*/
if (maxlvt >= 3) {
v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
- apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
}
/*
* Careful: we have to set masks only first to deassert
* any level-triggered sources.
*/
v = apic_read(APIC_LVTT);
- apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
v = apic_read(APIC_LVT0);
- apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
v = apic_read(APIC_LVT1);
- apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
if (maxlvt >= 4) {
v = apic_read(APIC_LVTPC);
- apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
}
/* lets not touch this if we didn't frob it */
#ifdef CONFIG_X86_MCE_THERMAL
if (maxlvt >= 5) {
v = apic_read(APIC_LVTTHMR);
- apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
}
#endif
if (maxlvt >= 6) {
v = apic_read(APIC_CMCI);
- apic_write_around(APIC_CMCI, v | APIC_LVT_MASKED);
+ apic_write(APIC_CMCI, v | APIC_LVT_MASKED);
}
/*
* Clean APIC state for other OSs:
*/
- apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
- apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
- apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
+ apic_write(APIC_LVTT, APIC_LVT_MASKED);
+ apic_write(APIC_LVT0, APIC_LVT_MASKED);
+ apic_write(APIC_LVT1, APIC_LVT_MASKED);
if (maxlvt >= 3)
- apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
+ apic_write(APIC_LVTERR, APIC_LVT_MASKED);
if (maxlvt >= 4)
- apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
+ apic_write(APIC_LVTPC, APIC_LVT_MASKED);
#ifdef CONFIG_X86_MCE_THERMAL
if (maxlvt >= 5)
- apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
+ apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
#endif
if (maxlvt >= 6)
- apic_write_around(APIC_CMCI, APIC_LVT_MASKED);
+ apic_write(APIC_CMCI, APIC_LVT_MASKED);
if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
apic_write(APIC_ESR, 0);
@@ -259,7 +259,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
value &= ~APIC_VECTOR_MASK;
value |= APIC_SPIV_APIC_ENABLED;
value |= 0xf;
- apic_write_around(APIC_SPIV, value);
+ apic_write(APIC_SPIV, value);
if (!virt_wire_setup) {
/* For LVT0 make it edge triggered, active high, external and enabled */
@@ -269,11 +269,11 @@ void disconnect_bsp_APIC(int virt_wire_setup)
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
- apic_write_around(APIC_LVT0, value);
+ apic_write(APIC_LVT0, value);
}
else {
/* Disable LVT0 */
- apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
+ apic_write(APIC_LVT0, APIC_LVT_MASKED);
}
/* For LVT1 make it edge triggered, active high, nmi and enabled */
@@ -284,7 +284,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
- apic_write_around(APIC_LVT1, value);
+ apic_write(APIC_LVT1, value);
}
}
@@ -296,8 +296,7 @@ void disable_local_APIC(void)
* Disable APIC (implies clearing of registers
* for 82489DX!).
*/
- apic_write_around(APIC_SPIV,
- apic_read(APIC_SPIV) & ~APIC_SPIV_APIC_ENABLED);
+ apic_write(APIC_SPIV, apic_read(APIC_SPIV) & ~APIC_SPIV_APIC_ENABLED);
if (enabled_via_apicbase) {
uint64_t msr_content;
@@ -424,8 +423,7 @@ void __init sync_Arb_IDs(void)
apic_wait_icr_idle();
apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
- apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
- | APIC_DM_INIT);
+ apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
}
/*
@@ -460,13 +458,13 @@ void __init init_bsp_APIC(void)
else
value |= APIC_SPIV_FOCUS_DISABLED;
value |= SPURIOUS_APIC_VECTOR;
- apic_write_around(APIC_SPIV, value);
+ apic_write(APIC_SPIV, value);
/*
* Set up the virtual wire mode.
*/
- apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
- apic_write_around(APIC_LVT1, APIC_DM_NMI);
+ apic_write(APIC_LVT0, APIC_DM_EXTINT);
+ apic_write(APIC_LVT1, APIC_DM_NMI);
}
static void apic_pm_activate(void)
@@ -551,7 +549,7 @@ void setup_local_APIC(void)
/*
* Set Task Priority to reject any interrupts below FIRST_DYNAMIC_VECTOR.
*/
- apic_write_around(APIC_TASKPRI, (FIRST_DYNAMIC_VECTOR & 0xF0) - 0x10);
+ apic_write(APIC_TASKPRI, (FIRST_DYNAMIC_VECTOR & 0xF0) - 0x10);
/*
* After a crash, we no longer service the interrupts and a pending
@@ -623,7 +621,7 @@ void setup_local_APIC(void)
smp_processor_id());
}
- apic_write_around(APIC_SPIV, value);
+ apic_write(APIC_SPIV, value);
/*
* Set up LVT0, LVT1:
@@ -645,7 +643,7 @@ void setup_local_APIC(void)
apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
smp_processor_id());
}
- apic_write_around(APIC_LVT0, value);
+ apic_write(APIC_LVT0, value);
/*
* only the BP should see the LINT1 NMI signal, obviously.
@@ -654,7 +652,7 @@ void setup_local_APIC(void)
value = APIC_DM_NMI;
else
value = APIC_DM_NMI | APIC_LVT_MASKED;
- apic_write_around(APIC_LVT1, value);
+ apic_write(APIC_LVT1, value);
if (!esr_disable) {
maxlvt = get_maxlvt();
@@ -663,7 +661,7 @@ void setup_local_APIC(void)
oldvalue = apic_read(APIC_ESR);
value = ERROR_APIC_VECTOR; // enables sending errors
- apic_write_around(APIC_LVTERR, value);
+ apic_write(APIC_LVTERR, value);
/*
* spec says clear errors after enabling vector.
*/
@@ -1075,12 +1073,12 @@ static void __setup_APIC_LVTT(unsigned int clocks)
lvtt_value |= APIC_TIMER_MODE_TSC_DEADLINE;
}
- apic_write_around(APIC_LVTT, lvtt_value);
+ apic_write(APIC_LVTT, lvtt_value);
tmp_value = apic_read(APIC_TDCR);
- apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
+ apic_write(APIC_TDCR, tmp_value | APIC_TDR_DIV_1);
- apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
+ apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
}
static void setup_APIC_timer(void)
@@ -1206,10 +1204,10 @@ void disable_APIC_timer(void)
unsigned long v;
/* Work around AMD Erratum 411. This is a nice thing to do anyway. */
- apic_write_around(APIC_TMICT, 0);
+ apic_write(APIC_TMICT, 0);
v = apic_read(APIC_LVTT);
- apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
}
}
@@ -1219,7 +1217,7 @@ void enable_APIC_timer(void)
unsigned long v;
v = apic_read(APIC_LVTT);
- apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
+ apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED);
}
}
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index fdf57ce..4e976c4 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -158,7 +158,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
/* The temperature transition interrupt handler setup */
val = thermal_apic_vector; /* our delivery vector */
val |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
- apic_write_around(APIC_LVTTHMR, val);
+ apic_write(APIC_LVTTHMR, val);
rdmsrl(MSR_IA32_THERM_INTERRUPT, msr_content);
wrmsrl(MSR_IA32_THERM_INTERRUPT, msr_content | 0x03);
@@ -166,7 +166,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
rdmsrl(MSR_IA32_MISC_ENABLE, msr_content);
wrmsrl(MSR_IA32_MISC_ENABLE, msr_content | (1ULL<<3));
- apic_write_around(APIC_LVTTHMR, val & ~APIC_LVT_MASKED);
+ apic_write(APIC_LVTTHMR, val & ~APIC_LVT_MASKED);
if (opt_cpu_info)
printk(KERN_INFO "CPU%u: Thermal monitoring enabled (%s)\n",
cpu, tm2 ? "TM2" : "TM1");
@@ -673,10 +673,10 @@ static void intel_init_cmci(struct cpuinfo_x86 *c)
apic = cmci_apic_vector;
apic |= (APIC_DM_FIXED | APIC_LVT_MASKED);
- apic_write_around(APIC_CMCI, apic);
+ apic_write(APIC_CMCI, apic);
l = apic_read(APIC_CMCI);
- apic_write_around(APIC_CMCI, l & ~APIC_LVT_MASKED);
+ apic_write(APIC_CMCI, l & ~APIC_LVT_MASKED);
mce_set_owner();
}
diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index 1f7830b..21383d3 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -441,13 +441,12 @@ int vpmu_load(struct vcpu *v, bool_t from_guest)
{
int ret;
- apic_write_around(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
+ apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
/* Arch code needs to set VPMU_CONTEXT_LOADED */
ret = vpmu->arch_vpmu_ops->arch_vpmu_load(v, from_guest);
if ( ret )
{
- apic_write_around(APIC_LVTPC,
- vpmu->hw_lapic_lvtpc | APIC_LVT_MASKED);
+ apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc | APIC_LVT_MASKED);
return ret;
}
}
diff --git a/xen/arch/x86/genapic/delivery.c b/xen/arch/x86/genapic/delivery.c
index 23ac361..ced92a1 100644
--- a/xen/arch/x86/genapic/delivery.c
+++ b/xen/arch/x86/genapic/delivery.c
@@ -19,10 +19,10 @@ void init_apic_ldr_flat(void)
{
unsigned long val;
- apic_write_around(APIC_DFR, APIC_DFR_FLAT);
+ apic_write(APIC_DFR, APIC_DFR_FLAT);
val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
val |= SET_xAPIC_LOGICAL_ID(1UL << smp_processor_id());
- apic_write_around(APIC_LDR, val);
+ apic_write(APIC_LDR, val);
}
void __init clustered_apic_check_flat(void)
@@ -47,10 +47,10 @@ unsigned int cpu_mask_to_apicid_flat(const cpumask_t *cpumask)
void init_apic_ldr_phys(void)
{
unsigned long val;
- apic_write_around(APIC_DFR, APIC_DFR_FLAT);
+ apic_write(APIC_DFR, APIC_DFR_FLAT);
/* A dummy logical ID should be fine. We only deliver in phys mode. */
val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
- apic_write_around(APIC_LDR, val);
+ apic_write(APIC_LDR, val);
}
void __init clustered_apic_check_phys(void)
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index d180460..bd59e13 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -1062,7 +1062,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
disable_8259A_irq(irq_to_desc(0));
/* mask LVT0 */
- apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
+ apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
/*
* We use logical delivery to get the timer IRQ
@@ -1790,7 +1790,7 @@ static void enable_lapic_irq(struct irq_desc *desc)
unsigned long v;
v = apic_read(APIC_LVT0);
- apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
+ apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
}
static void disable_lapic_irq(struct irq_desc *desc)
@@ -1798,7 +1798,7 @@ static void disable_lapic_irq(struct irq_desc *desc)
unsigned long v;
v = apic_read(APIC_LVT0);
- apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
+ apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
}
static void ack_lapic_irq(struct irq_desc *desc)
@@ -1903,7 +1903,7 @@ static void __init check_timer(void)
* the 8259A which implies the virtual wire has to be
* disabled in the local APIC.
*/
- apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
+ apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
init_8259A(1);
/* XEN: Ripped out the legacy missed-tick logic, so below is not needed. */
/*timer_ack = 1;*/
@@ -1963,7 +1963,7 @@ static void __init check_timer(void)
disable_8259A_irq(irq_to_desc(0));
irq_desc[0].handler = &lapic_irq_type;
- apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
+ apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
enable_8259A_irq(irq_to_desc(0));
if (timer_irq_works()) {
@@ -1971,7 +1971,7 @@ static void __init check_timer(void)
printk(" works.\n");
return;
}
- apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
+ apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
printk(" failed.\n");
printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
@@ -1979,7 +1979,7 @@ static void __init check_timer(void)
/*timer_ack = 0;*/
init_8259A(0);
make_8259A_irq(0);
- apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
+ apic_write(APIC_LVT0, APIC_DM_EXTINT);
unlock_ExtINT_logic();
diff --git a/xen/arch/x86/smp.c b/xen/arch/x86/smp.c
index 70de53d..fd6d254 100644
--- a/xen/arch/x86/smp.c
+++ b/xen/arch/x86/smp.c
@@ -115,7 +115,7 @@ static void __default_send_IPI_shortcut(unsigned int shortcut, int vector,
/*
* Send the IPI. The write to APIC_ICR fires this off.
*/
- apic_write_around(APIC_ICR, cfg);
+ apic_write(APIC_ICR, cfg);
}
void send_IPI_self_legacy(uint8_t vector)
@@ -145,7 +145,7 @@ void send_IPI_mask_flat(const cpumask_t *cpumask, int vector)
* prepare target chip field
*/
cfg = __prepare_ICR2(mask);
- apic_write_around(APIC_ICR2, cfg);
+ apic_write(APIC_ICR2, cfg);
/*
* program the ICR
@@ -155,7 +155,7 @@ void send_IPI_mask_flat(const cpumask_t *cpumask, int vector)
/*
* Send the IPI. The write to APIC_ICR fires this off.
*/
- apic_write_around(APIC_ICR, cfg);
+ apic_write(APIC_ICR, cfg);
local_irq_restore(flags);
}
@@ -181,7 +181,7 @@ void send_IPI_mask_phys(const cpumask_t *mask, int vector)
* prepare target chip field
*/
cfg = __prepare_ICR2(cpu_physical_id(query_cpu));
- apic_write_around(APIC_ICR2, cfg);
+ apic_write(APIC_ICR2, cfg);
/*
* program the ICR
@@ -191,7 +191,7 @@ void send_IPI_mask_phys(const cpumask_t *mask, int vector)
/*
* Send the IPI. The write to APIC_ICR fires this off.
*/
- apic_write_around(APIC_ICR, cfg);
+ apic_write(APIC_ICR, cfg);
}
local_irq_restore(flags);
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 92fe4f2..f375eb6 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -385,7 +385,6 @@ static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
/*
* Be paranoid about clearing APIC errors.
*/
- apic_read_around(APIC_SPIV);
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
@@ -439,7 +438,6 @@ static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
for ( i = 0; i < 2; i++ )
{
Dprintk("Sending STARTUP #%d.\n", i+1);
- apic_read_around(APIC_SPIV);
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
Dprintk("After apic_write.\n");
@@ -472,7 +470,6 @@ static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
/* Due to the Pentium erratum 3AP. */
if ( maxlvt > 3 )
{
- apic_read_around(APIC_SPIV);
apic_write(APIC_ESR, 0);
}
accept_status = (apic_read(APIC_ESR) & 0xEF);
diff --git a/xen/include/asm-x86/apic.h b/xen/include/asm-x86/apic.h
index 9952039..d840ee5 100644
--- a/xen/include/asm-x86/apic.h
+++ b/xen/include/asm-x86/apic.h
@@ -161,27 +161,10 @@ void apic_wait_icr_idle(void);
int get_physical_broadcast(void);
-#ifdef CONFIG_X86_GOOD_APIC
-# define FORCE_READ_AROUND_WRITE 0
-# define apic_read_around(x)
-# define apic_write_around(x,y) apic_write((x),(y))
-#else
-# define FORCE_READ_AROUND_WRITE 1
-# define apic_read_around(x) apic_read(x)
-# define apic_write_around(x,y) apic_write_atomic((x),(y))
-#endif
-
static inline void ack_APIC_irq(void)
{
- /*
- * ack_APIC_irq() actually gets compiled as a single instruction:
- * - a single rmw on Pentium/82489DX
- * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
- * ... yummie.
- */
-
/* Docs say use 0 for future compatibility */
- apic_write_around(APIC_EOI, 0);
+ apic_write(APIC_EOI, 0);
}
extern int get_maxlvt(void);
diff --git a/xen/include/asm-x86/config.h b/xen/include/asm-x86/config.h
index a199c3a..ba486d5 100644
--- a/xen/include/asm-x86/config.h
+++ b/xen/include/asm-x86/config.h
@@ -19,7 +19,6 @@
#define CONFIG_PAGING_ASSISTANCE 1
#define CONFIG_X86_LOCAL_APIC 1
-#define CONFIG_X86_GOOD_APIC 1
#define CONFIG_X86_IO_APIC 1
#define CONFIG_X86_PM_TIMER 1
#define CONFIG_HPET_TIMER 1
--
2.1.4
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] x86/apic: Drop workarounds for Pentium/82489DX erratum
2017-06-01 14:51 [PATCH] x86/apic: Drop workarounds for Pentium/82489DX erratum Andrew Cooper
@ 2017-06-06 15:18 ` Jan Beulich
2017-06-06 16:01 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Andrew Cooper
1 sibling, 0 replies; 9+ messages in thread
From: Jan Beulich @ 2017-06-06 15:18 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Xen-devel
>>> On 01.06.17 at 16:51, <andrew.cooper3@citrix.com> wrote:
> CONFIG_X86_GOOD_APIC is unconditionally selected for 64bit builds. Drop the
> related infrastructure including apic_{read,write}_around(), the former of
> which had no effect, and the latter which was an alias of apic_write().
>
> No functional change, as confirmed by diffing the before/after disassembly.
> (Three __LINE__ numbers are different, but they are `mov $imm, %reg` as part
> of a dprintk() call.)
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/4] x86/apic: Drop the unused struct local_apic
2017-06-01 14:51 [PATCH] x86/apic: Drop workarounds for Pentium/82489DX erratum Andrew Cooper
2017-06-06 15:18 ` Jan Beulich
@ 2017-06-06 16:01 ` Andrew Cooper
2017-06-06 16:01 ` [PATCH 3/4] x86/apic: Drop CONFIG_LOCAL_APIC Andrew Cooper
` (2 more replies)
1 sibling, 3 replies; 9+ messages in thread
From: Andrew Cooper @ 2017-06-06 16:01 UTC (permalink / raw)
To: Xen-devel; +Cc: Andrew Cooper, Jan Beulich
It is not suitable for Xen's use (being xapic and x2apic compatible), and the
comment doesn't inspire much confidence in its correctness.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
---
xen/include/asm-x86/apicdef.h | 262 ------------------------------------------
1 file changed, 262 deletions(-)
diff --git a/xen/include/asm-x86/apicdef.h b/xen/include/asm-x86/apicdef.h
index 1b2c452..eed504a 100644
--- a/xen/include/asm-x86/apicdef.h
+++ b/xen/include/asm-x86/apicdef.h
@@ -126,266 +126,4 @@
#define MAX_IO_APICS 128
-/*
- * the local APIC register structure, memory mapped. Not terribly well
- * tested, but we might eventually use this one in the future - the
- * problem why we cannot use it right now is the P5 APIC, it has an
- * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
- */
-#define u32 unsigned int
-
-#define lapic ((volatile struct local_apic *)APIC_BASE)
-
-#ifndef __ASSEMBLY__
-struct __packed local_apic {
-
-/*000*/ struct { u32 __reserved[4]; } __reserved_01;
-
-/*010*/ struct { u32 __reserved[4]; } __reserved_02;
-
-/*020*/ struct { /* APIC ID Register */
- u32 __reserved_1 : 24,
- phys_apic_id : 4,
- __reserved_2 : 4;
- u32 __reserved[3];
- } id;
-
-/*030*/ const
- struct { /* APIC Version Register */
- u32 version : 8,
- __reserved_1 : 8,
- max_lvt : 8,
- __reserved_2 : 8;
- u32 __reserved[3];
- } version;
-
-/*040*/ struct { u32 __reserved[4]; } __reserved_03;
-
-/*050*/ struct { u32 __reserved[4]; } __reserved_04;
-
-/*060*/ struct { u32 __reserved[4]; } __reserved_05;
-
-/*070*/ struct { u32 __reserved[4]; } __reserved_06;
-
-/*080*/ struct { /* Task Priority Register */
- u32 priority : 8,
- __reserved_1 : 24;
- u32 __reserved_2[3];
- } tpr;
-
-/*090*/ const
- struct { /* Arbitration Priority Register */
- u32 priority : 8,
- __reserved_1 : 24;
- u32 __reserved_2[3];
- } apr;
-
-/*0A0*/ const
- struct { /* Processor Priority Register */
- u32 priority : 8,
- __reserved_1 : 24;
- u32 __reserved_2[3];
- } ppr;
-
-/*0B0*/ struct { /* End Of Interrupt Register */
- u32 eoi;
- u32 __reserved[3];
- } eoi;
-
-/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
-
-/*0D0*/ struct { /* Logical Destination Register */
- u32 __reserved_1 : 24,
- logical_dest : 8;
- u32 __reserved_2[3];
- } ldr;
-
-/*0E0*/ struct { /* Destination Format Register */
- u32 __reserved_1 : 28,
- model : 4;
- u32 __reserved_2[3];
- } dfr;
-
-/*0F0*/ struct { /* Spurious Interrupt Vector Register */
- u32 spurious_vector : 8,
- apic_enabled : 1,
- focus_cpu : 1,
- __reserved_2 : 22;
- u32 __reserved_3[3];
- } svr;
-
-/*100*/ struct { /* In Service Register */
-/*170*/ u32 bitfield;
- u32 __reserved[3];
- } isr [8];
-
-/*180*/ struct { /* Trigger Mode Register */
-/*1F0*/ u32 bitfield;
- u32 __reserved[3];
- } tmr [8];
-
-/*200*/ struct { /* Interrupt Request Register */
-/*270*/ u32 bitfield;
- u32 __reserved[3];
- } irr [8];
-
-/*280*/ union { /* Error Status Register */
- struct {
- u32 send_cs_error : 1,
- receive_cs_error : 1,
- send_accept_error : 1,
- receive_accept_error : 1,
- __reserved_1 : 1,
- send_illegal_vector : 1,
- receive_illegal_vector : 1,
- illegal_register_address : 1,
- __reserved_2 : 24;
- u32 __reserved_3[3];
- } error_bits;
- struct {
- u32 errors;
- u32 __reserved_3[3];
- } all_errors;
- } esr;
-
-/*290*/ struct { u32 __reserved[4]; } __reserved_08;
-
-/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
-
-/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
-
-/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
-
-/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
-
-/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
-
-/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
-
-/*300*/ struct { /* Interrupt Command Register 1 */
- u32 vector : 8,
- delivery_mode : 3,
- destination_mode : 1,
- delivery_status : 1,
- __reserved_1 : 1,
- level : 1,
- trigger : 1,
- __reserved_2 : 2,
- shorthand : 2,
- __reserved_3 : 12;
- u32 __reserved_4[3];
- } icr1;
-
-/*310*/ struct { /* Interrupt Command Register 2 */
- union {
- u32 __reserved_1 : 24,
- phys_dest : 4,
- __reserved_2 : 4;
- u32 __reserved_3 : 24,
- logical_dest : 8;
- } dest;
- u32 __reserved_4[3];
- } icr2;
-
-/*320*/ struct { /* LVT - Timer */
- u32 vector : 8,
- __reserved_1 : 4,
- delivery_status : 1,
- __reserved_2 : 3,
- mask : 1,
- timer_mode : 1,
- __reserved_3 : 14;
- u32 __reserved_4[3];
- } lvt_timer;
-
-/*330*/ struct { /* LVT - Thermal Sensor */
- u32 vector : 8,
- delivery_mode : 3,
- __reserved_1 : 1,
- delivery_status : 1,
- __reserved_2 : 3,
- mask : 1,
- __reserved_3 : 15;
- u32 __reserved_4[3];
- } lvt_thermal;
-
-/*340*/ struct { /* LVT - Performance Counter */
- u32 vector : 8,
- delivery_mode : 3,
- __reserved_1 : 1,
- delivery_status : 1,
- __reserved_2 : 3,
- mask : 1,
- __reserved_3 : 15;
- u32 __reserved_4[3];
- } lvt_pc;
-
-/*350*/ struct { /* LVT - LINT0 */
- u32 vector : 8,
- delivery_mode : 3,
- __reserved_1 : 1,
- delivery_status : 1,
- polarity : 1,
- remote_irr : 1,
- trigger : 1,
- mask : 1,
- __reserved_2 : 15;
- u32 __reserved_3[3];
- } lvt_lint0;
-
-/*360*/ struct { /* LVT - LINT1 */
- u32 vector : 8,
- delivery_mode : 3,
- __reserved_1 : 1,
- delivery_status : 1,
- polarity : 1,
- remote_irr : 1,
- trigger : 1,
- mask : 1,
- __reserved_2 : 15;
- u32 __reserved_3[3];
- } lvt_lint1;
-
-/*370*/ struct { /* LVT - Error */
- u32 vector : 8,
- __reserved_1 : 4,
- delivery_status : 1,
- __reserved_2 : 3,
- mask : 1,
- __reserved_3 : 15;
- u32 __reserved_4[3];
- } lvt_error;
-
-/*380*/ struct { /* Timer Initial Count Register */
- u32 initial_count;
- u32 __reserved_2[3];
- } timer_icr;
-
-/*390*/ const
- struct { /* Timer Current Count Register */
- u32 curr_count;
- u32 __reserved_2[3];
- } timer_ccr;
-
-/*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
-
-/*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
-
-/*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
-
-/*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
-
-/*3E0*/ struct { /* Timer Divide Configuration Register */
- u32 divisor : 4,
- __reserved_1 : 28;
- u32 __reserved_2[3];
- } timer_dcr;
-
-/*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
-
-};
-#endif /* !__ASSEMBLY__ */
-
-#undef u32
-
#endif
--
2.1.4
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] x86/apic: Drop CONFIG_LOCAL_APIC
2017-06-06 16:01 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Andrew Cooper
@ 2017-06-06 16:01 ` Andrew Cooper
2017-06-07 12:47 ` Jan Beulich
2017-06-06 16:01 ` [PATCH 4/4] x86/apic: Drop CONFIG_IO_APIC Andrew Cooper
2017-06-07 12:44 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Jan Beulich
2 siblings, 1 reply; 9+ messages in thread
From: Andrew Cooper @ 2017-06-06 16:01 UTC (permalink / raw)
To: Xen-devel; +Cc: Andrew Cooper, Jan Beulich
It is unconditionally selected, and all 64bit processors have local APICs.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
---
xen/arch/x86/acpi/boot.c | 10 ----------
xen/include/asm-x86/apic.h | 8 --------
xen/include/asm-x86/config.h | 1 -
3 files changed, 19 deletions(-)
diff --git a/xen/arch/x86/acpi/boot.c b/xen/arch/x86/acpi/boot.c
index 33c9133..6e6d338 100644
--- a/xen/arch/x86/acpi/boot.c
+++ b/xen/arch/x86/acpi/boot.c
@@ -54,15 +54,12 @@ bool_t __initdata acpi_ioapic;
static bool_t acpi_skip_timer_override __initdata;
boolean_param("acpi_skip_timer_override", acpi_skip_timer_override);
-#ifdef CONFIG_X86_LOCAL_APIC
static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
-#endif
/* --------------------------------------------------------------------------
Boot-time Configuration
-------------------------------------------------------------------------- */
-#ifdef CONFIG_X86_LOCAL_APIC
static int __init acpi_parse_madt(struct acpi_table_header *table)
{
struct acpi_table_madt *madt;
@@ -207,8 +204,6 @@ acpi_parse_lapic_nmi(struct acpi_subtable_header * header, const unsigned long e
return 0;
}
-#endif /*CONFIG_X86_LOCAL_APIC */
-
#if defined(CONFIG_X86_IO_APIC) /*&& defined(CONFIG_ACPI_INTERPRETER)*/
static int __init
@@ -510,7 +505,6 @@ static int __init acpi_parse_fadt(struct acpi_table_header *table)
return 0;
}
-#ifdef CONFIG_X86_LOCAL_APIC
/*
* Parse LAPIC entries in MADT
* returns 0 on success, < 0 on error
@@ -566,7 +560,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
}
return 0;
}
-#endif /* CONFIG_X86_LOCAL_APIC */
#ifdef CONFIG_X86_IO_APIC
/*
@@ -644,7 +637,6 @@ static inline int acpi_parse_madt_ioapic_entries(void)
static void __init acpi_process_madt(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
int error;
if (!acpi_table_parse(ACPI_SIG_MADT, acpi_parse_madt)) {
@@ -677,8 +669,6 @@ static void __init acpi_process_madt(void)
disable_acpi();
}
}
-#endif
- return;
}
/*
diff --git a/xen/include/asm-x86/apic.h b/xen/include/asm-x86/apic.h
index d840ee5..342db73 100644
--- a/xen/include/asm-x86/apic.h
+++ b/xen/include/asm-x86/apic.h
@@ -49,8 +49,6 @@ const struct genapic *apic_x2apic_probe(void);
} while (0)
-#ifdef CONFIG_X86_LOCAL_APIC
-
/*
* Basic functions accessing APICs.
*/
@@ -205,10 +203,4 @@ extern unsigned int nmi_watchdog;
#define NMI_IO_APIC 1
#define NMI_LOCAL_APIC 2
-#else /* !CONFIG_X86_LOCAL_APIC */
-static inline int lapic_suspend(void) {return 0;}
-static inline int lapic_resume(void) {return 0;}
-
-#endif /* !CONFIG_X86_LOCAL_APIC */
-
#endif /* __ASM_APIC_H */
diff --git a/xen/include/asm-x86/config.h b/xen/include/asm-x86/config.h
index ba486d5..7587112 100644
--- a/xen/include/asm-x86/config.h
+++ b/xen/include/asm-x86/config.h
@@ -18,7 +18,6 @@
#define BITS_PER_XEN_ULONG BITS_PER_LONG
#define CONFIG_PAGING_ASSISTANCE 1
-#define CONFIG_X86_LOCAL_APIC 1
#define CONFIG_X86_IO_APIC 1
#define CONFIG_X86_PM_TIMER 1
#define CONFIG_HPET_TIMER 1
--
2.1.4
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] x86/apic: Drop CONFIG_IO_APIC
2017-06-06 16:01 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Andrew Cooper
2017-06-06 16:01 ` [PATCH 3/4] x86/apic: Drop CONFIG_LOCAL_APIC Andrew Cooper
@ 2017-06-06 16:01 ` Andrew Cooper
2017-06-07 12:49 ` Jan Beulich
2017-06-07 12:44 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Jan Beulich
2 siblings, 1 reply; 9+ messages in thread
From: Andrew Cooper @ 2017-06-06 16:01 UTC (permalink / raw)
To: Xen-devel; +Cc: Andrew Cooper, Jan Beulich
It is unconditionally selected, and compiling out IO-APIC support is not a
useful think to do these days.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
---
xen/arch/x86/acpi/boot.c | 12 ------------
xen/arch/x86/apic.c | 4 ++--
xen/arch/x86/mpparse.c | 3 ---
xen/include/asm-x86/config.h | 1 -
xen/include/asm-x86/io_apic.h | 8 --------
5 files changed, 2 insertions(+), 26 deletions(-)
diff --git a/xen/arch/x86/acpi/boot.c b/xen/arch/x86/acpi/boot.c
index 6e6d338..83cbff9 100644
--- a/xen/arch/x86/acpi/boot.c
+++ b/xen/arch/x86/acpi/boot.c
@@ -204,8 +204,6 @@ acpi_parse_lapic_nmi(struct acpi_subtable_header * header, const unsigned long e
return 0;
}
-#if defined(CONFIG_X86_IO_APIC) /*&& defined(CONFIG_ACPI_INTERPRETER)*/
-
static int __init
acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end)
{
@@ -266,8 +264,6 @@ acpi_parse_nmi_src(struct acpi_subtable_header * header, const unsigned long end
return 0;
}
-#endif /* CONFIG_X86_IO_APIC */
-
#ifdef CONFIG_HPET_TIMER
static int __init acpi_parse_hpet(struct acpi_table_header *table)
@@ -561,7 +557,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
return 0;
}
-#ifdef CONFIG_X86_IO_APIC
/*
* Parse IOAPIC related entries in MADT
* returns 0 on success, < 0 on error
@@ -627,13 +622,6 @@ static int __init acpi_parse_madt_ioapic_entries(void)
return 0;
}
-#else
-static inline int acpi_parse_madt_ioapic_entries(void)
-{
- return -1;
-}
-#endif /* !CONFIG_X86_IO_APIC */
-
static void __init acpi_process_madt(void)
{
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index a5ae4b6..8c6c2f5 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -1379,11 +1379,11 @@ int __init APIC_init_uniprocessor (void)
if (nmi_watchdog == NMI_LOCAL_APIC)
check_nmi_watchdog();
-#ifdef CONFIG_X86_IO_APIC
+
if (smp_found_config)
if (!skip_ioapic_setup && nr_ioapics)
setup_IO_APIC();
-#endif
+
setup_boot_APIC_clock();
return 0;
diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c
index efcbc61..efccde2 100644
--- a/xen/arch/x86/mpparse.c
+++ b/xen/arch/x86/mpparse.c
@@ -819,8 +819,6 @@ void mp_unregister_lapic(uint32_t apic_id, uint32_t cpu)
cpumask_clear_cpu(cpu, &cpu_present_map);
}
-#ifdef CONFIG_X86_IO_APIC
-
#define MP_ISA_BUS 0
#define MP_MAX_IOAPIC_PIN 127
@@ -1101,5 +1099,4 @@ int mp_register_gsi (u32 gsi, int triggering, int polarity)
triggering, polarity);
}
-#endif /* CONFIG_X86_IO_APIC */
#endif /* CONFIG_ACPI */
diff --git a/xen/include/asm-x86/config.h b/xen/include/asm-x86/config.h
index 7587112..dc424f9 100644
--- a/xen/include/asm-x86/config.h
+++ b/xen/include/asm-x86/config.h
@@ -18,7 +18,6 @@
#define BITS_PER_XEN_ULONG BITS_PER_LONG
#define CONFIG_PAGING_ASSISTANCE 1
-#define CONFIG_X86_IO_APIC 1
#define CONFIG_X86_PM_TIMER 1
#define CONFIG_HPET_TIMER 1
#define CONFIG_X86_MCE_THERMAL 1
diff --git a/xen/include/asm-x86/io_apic.h b/xen/include/asm-x86/io_apic.h
index 8029c8f..1706969 100644
--- a/xen/include/asm-x86/io_apic.h
+++ b/xen/include/asm-x86/io_apic.h
@@ -13,8 +13,6 @@
* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
*/
-#ifdef CONFIG_X86_IO_APIC
-
#define IO_APIC_BASE(idx) \
((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
@@ -199,12 +197,6 @@ extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
-#else /* !CONFIG_X86_IO_APIC */
-static inline void init_ioapic_mappings(void) {}
-static inline void ioapic_suspend(void) {}
-static inline void ioapic_resume(void) {}
-#endif
-
unsigned highest_gsi(void);
int ioapic_guest_read( unsigned long physbase, unsigned int reg, u32 *pval);
--
2.1.4
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] x86/apic: Drop the unused struct local_apic
2017-06-06 16:01 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Andrew Cooper
2017-06-06 16:01 ` [PATCH 3/4] x86/apic: Drop CONFIG_LOCAL_APIC Andrew Cooper
2017-06-06 16:01 ` [PATCH 4/4] x86/apic: Drop CONFIG_IO_APIC Andrew Cooper
@ 2017-06-07 12:44 ` Jan Beulich
2 siblings, 0 replies; 9+ messages in thread
From: Jan Beulich @ 2017-06-07 12:44 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Xen-devel
>>> On 06.06.17 at 18:01, <andrew.cooper3@citrix.com> wrote:
> It is not suitable for Xen's use (being xapic and x2apic compatible), and the
> comment doesn't inspire much confidence in its correctness.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] x86/apic: Drop CONFIG_LOCAL_APIC
2017-06-06 16:01 ` [PATCH 3/4] x86/apic: Drop CONFIG_LOCAL_APIC Andrew Cooper
@ 2017-06-07 12:47 ` Jan Beulich
0 siblings, 0 replies; 9+ messages in thread
From: Jan Beulich @ 2017-06-07 12:47 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Xen-devel
>>> On 06.06.17 at 18:01, <andrew.cooper3@citrix.com> wrote:
> It is unconditionally selected, and all 64bit processors have local APICs.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] x86/apic: Drop CONFIG_IO_APIC
2017-06-06 16:01 ` [PATCH 4/4] x86/apic: Drop CONFIG_IO_APIC Andrew Cooper
@ 2017-06-07 12:49 ` Jan Beulich
2017-06-07 12:51 ` Andrew Cooper
0 siblings, 1 reply; 9+ messages in thread
From: Jan Beulich @ 2017-06-07 12:49 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Xen-devel
>>> On 06.06.17 at 18:01, <andrew.cooper3@citrix.com> wrote:
> It is unconditionally selected, and compiling out IO-APIC support is not a
> useful think to do these days.
thing?
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] x86/apic: Drop CONFIG_IO_APIC
2017-06-07 12:49 ` Jan Beulich
@ 2017-06-07 12:51 ` Andrew Cooper
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Cooper @ 2017-06-07 12:51 UTC (permalink / raw)
To: Jan Beulich; +Cc: Xen-devel
On 07/06/17 13:49, Jan Beulich wrote:
>>>> On 06.06.17 at 18:01, <andrew.cooper3@citrix.com> wrote:
>> It is unconditionally selected, and compiling out IO-APIC support is not a
>> useful think to do these days.
> thing?
Yes - I already noticed and fixed.
>
>> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
> Reviewed-by: Jan Beulich <jbeulich@suse.com>
Thanks.
~Andrew
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-06-07 12:51 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-01 14:51 [PATCH] x86/apic: Drop workarounds for Pentium/82489DX erratum Andrew Cooper
2017-06-06 15:18 ` Jan Beulich
2017-06-06 16:01 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Andrew Cooper
2017-06-06 16:01 ` [PATCH 3/4] x86/apic: Drop CONFIG_LOCAL_APIC Andrew Cooper
2017-06-07 12:47 ` Jan Beulich
2017-06-06 16:01 ` [PATCH 4/4] x86/apic: Drop CONFIG_IO_APIC Andrew Cooper
2017-06-07 12:49 ` Jan Beulich
2017-06-07 12:51 ` Andrew Cooper
2017-06-07 12:44 ` [PATCH 2/4] x86/apic: Drop the unused struct local_apic Jan Beulich
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).