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From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Cc: Wei Liu <wl@xen.org>, Ian Jackson <iwj@xenproject.org>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH 2/2] x86/cpuid: support LFENCE always serializing CPUID bit
Date: Wed, 14 Apr 2021 14:45:21 +0200	[thread overview]
Message-ID: <63738788-c7ed-13f7-acaa-c1ad102442a3@suse.com> (raw)
In-Reply-To: <97d443b0-f5c2-0183-74c1-ab16d3cf1e7d@citrix.com>

On 14.04.2021 14:33, Andrew Cooper wrote:
> On 14/04/2021 12:04, Roger Pau Monne wrote:
>> --- a/tools/misc/xen-cpuid.c
>> +++ b/tools/misc/xen-cpuid.c
>> @@ -178,6 +178,11 @@ static const char *const str_7a1[32] =
>>      [ 4] = "avx-vnni",      [ 5] = "avx512-bf16",
>>  };
>>  
>> +static const char *const str_e21a[32] =
>> +{
>> +    [ 2] = "lfence-always-serializing",
> 
> This is a bit of a mouthful.  One problem is the fact that "serialising"
> is an ambiguous term, because neither Intel nor AMD formally specify
> what it means in the architecture.
> 
> There is a description of what "architecturally serialising" does, which
> does occasionally move over time, and the name of this CPUID bit in the
> PPR confusing at best, because it very much isn't "architecturally
> serialising", and the term "dispatch serialising" isn't actually defined
> anywhere.
> 
> Intel have now started referring to LFENCE as a "speculative execution
> barrier", but this still doesn't have a precise definition.
> 
> I'm afraid I don't have a useful suggestion for something short and
> concise, which also conveys the precise meaning.

How about "lfence+" or some such?

Jan


  reply	other threads:[~2021-04-14 12:45 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14 11:04 [PATCH 0/2] x86/amd: LFENCE always serializing CPUID bit Roger Pau Monne
2021-04-14 11:04 ` [PATCH 1/2] x86/amd: split LFENCE dispatch serializing setup logic into helper Roger Pau Monne
2021-04-14 11:11   ` Andrew Cooper
2021-04-14 11:04 ` [PATCH 2/2] x86/cpuid: support LFENCE always serializing CPUID bit Roger Pau Monne
2021-04-14 12:33   ` Andrew Cooper
2021-04-14 12:45     ` Jan Beulich [this message]
2021-04-14 12:49       ` Andrew Cooper
2021-04-14 12:57   ` Jan Beulich
2021-04-14 13:05     ` Andrew Cooper
2021-04-14 13:24       ` Jan Beulich
2021-04-14 13:41         ` Andrew Cooper
2021-04-14 13:25       ` Andrew Cooper
2021-04-14 13:57         ` Jan Beulich
2021-04-15 13:31           ` Roger Pau Monné

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