[PATCH] xen: x86: remove duplicated MSR_IA32_FEATURE_CONTROL definition

* [PATCH] xen: x86: remove duplicated MSR_IA32_FEATURE_CONTROL definition
@ 2016-06-22 10:17 kaih.linux
  2016-06-22 11:44 ` Jan Beulich
  0 siblings, 1 reply; 3+ messages in thread
From: kaih.linux @ 2016-06-22 10:17 UTC (permalink / raw)
  To: jbeulich, andrew.cooper3, xen-devel; +Cc: Kai Huang

From: Kai Huang <kai.huang@linux.intel.com>

MSR_IA32_FEATURE_CONTROL was introduced in below commit. Actually this MSR has
already been defined as IA32_FEATURE_CONTROL_MSR. Remove it as a duplication.

Also introduce a new macro for SGX_ENABLE bit in this MSR for better code and
further use. The code of below commit is changed accordingly.

commit 5a211704e8813c4890c8ce8dc4189d1dfb35ecd0
Author: Len Brown <len.brown@intel.com>
Date:   Fri Apr 8 22:31:47 2016 +0200

    mwait-idle: prevent SKL-H boot failure when C8+C9+C10 enabled

    Some SKL-H configurations require "max_cstate=7" to boot.
    While that is an effective workaround, it disables C10.

    ......

One more thinking: actually the SDM says 'Software is considered to have opted
into Intel SGX if and only if IA32_FEATURE_CONTROL.SGX_ENABLE and
IA32_FEATURE_CONTRORL.LOCK are set to 1', therefore maybe below change with the
lock bit checked is more reasonable, but existing code is safe anyway (and I
don't have machine to test).

        /* if SGX is enabled */
        if ((msr & IA32_FEATURE_CONTROL_SGX_ENABLE) &&
		    (msr & IA32_FEATURE_CONTROL_MSR_LOCK))
	            return;

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
---
 xen/arch/x86/cpu/mwait-idle.c   | 4 ++--
 xen/include/asm-x86/msr-index.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index e062e21..946d598 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -1003,10 +1003,10 @@ static void __init sklh_idle_state_table_update(void)
 
 	/* if SGX is present */
 	if (boot_cpu_has(X86_FEATURE_SGX)) {
-		rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
+		rdmsrl(IA32_FEATURE_CONTROL_MSR, msr);
 
 		/* if SGX is enabled */
-		if (msr & (1 << 18))
+		if (msr & IA32_FEATURE_CONTROL_SGX_ENABLE)
 			return;
 	}
 
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index e0f7f8d..f539e24 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -139,6 +139,7 @@
 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004
 #define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL         0x7f00
 #define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER            0x8000
+#define IA32_FEATURE_CONTROL_SGX_ENABLE         0x40000
 
 /* K7/K8 MSRs. Not complete. See the architecture manual for a more
    complete list. */
@@ -288,7 +289,6 @@
 #define MSR_IA32_PLATFORM_ID		0x00000017
 #define MSR_IA32_EBL_CR_POWERON		0x0000002a
 #define MSR_IA32_EBC_FREQUENCY_ID	0x0000002c
-#define MSR_IA32_FEATURE_CONTROL	0x0000003a
 #define MSR_IA32_TSC_ADJUST		0x0000003b
 
 #define MSR_IA32_APICBASE		0x0000001b
-- 
2.7.4


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