From: Tamas K Lengyel <tamas@tklengyel.com>
To: Julien Grall <julien.grall@arm.com>
Cc: Xen-devel <xen-devel@lists.xenproject.org>,
Stefano Stabellini <sstabellini@kernel.org>,
Razvan Cojocaru <rcojocaru@bitdefender.com>,
Jan Beulich <JBeulich@suse.com>
Subject: Re: [PATCH v4 5/8] arm/vm_event: get/set registers
Date: Wed, 1 Jun 2016 12:21:20 -0600 [thread overview]
Message-ID: <CABfawhkAJosKkdMH+qigZtgy8u-+6jaQex5_T201K1djcTQftg@mail.gmail.com> (raw)
In-Reply-To: <574EC5E3.10600@arm.com>
On Wed, Jun 1, 2016 at 5:24 AM, Julien Grall <julien.grall@arm.com> wrote:
> Hi,
>
>
> On 01/06/16 09:41, Jan Beulich wrote:
>>>>>
>>>>> On 31.05.16 at 18:28, <tamas@tklengyel.com> wrote:
>>>
>>> On May 31, 2016 01:48, "Jan Beulich" <JBeulich@suse.com> wrote:
>>>>
>>>>
>>>>>>> On 30.05.16 at 21:47, <tamas@tklengyel.com> wrote:
>>>>>
>>>>> On Mon, May 30, 2016 at 5:50 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>>>>
>>>>>>>>> On 30.05.16 at 00:37, <tamas@tklengyel.com> wrote:
>>>>>>>
>>>>>>> +struct vm_event_regs_arm32 {
>>>>>>> + uint32_t r0_usr;
>>>>>>> + uint32_t r1_usr;
>>>>>>> + uint32_t r2_usr;
>>>>>>> + uint32_t r3_usr;
>>>>>>> + uint32_t r4_usr;
>>>>>>> + uint32_t r5_usr;
>>>>>>> + uint32_t r6_usr;
>>>>>>> + uint32_t r7_usr;
>>>>>>> + uint32_t r8_usr;
>>>>>>> + uint32_t r9_usr;
>>>>>>> + uint32_t r10_usr;
>>>>>>> + uint32_t r12_usr;
>>>>>>> + uint32_t lr_usr;
>>>>>>> + uint32_t fp;
>>>>>>> + uint32_t pc;
>>>>>>> + uint32_t sp_usr;
>>>>>>> + uint32_t sp_svc;
>>>>>>> + uint32_t spsr_svc;
>>>>>>> +};
>>>>>>
>>>>>>
>>>>>> It would seem more natural for the "ordinary" registers to be
>>>>>> arranged in the numerical sequence, i.e. fp, r12, sp, lr, pc.
>>>>>
>>>>>
>>>>> Not sure I follow.
>>>>
>>>>
>>>> For one it is quite natural for someone looking at a sequence of
>>>> register values to assume / expect them to be in natural order.
>>>> And then, having them in natural (numeric) order allows e.g.
>>>> extracting the register identifying bits from an instruction to use
>>>> them as an array index into (part of) this structure.
>>>>
>>>> (For some background: I've been bitten a number of times by
>>>> people sorting x86 registers alphabetically instead or naturally,
>>>> i.e. EAX, EBX, ECX, EDX instead of EAX, ECX, EDX, EBX).
>>>
>>>
>>> I see, however I believe that would be a very careless use of this struct
>>> from the user as the register sizes are not even necessarily match the
>>> architecture. For example we only define the 64bit x86 registers, so
>>> trying
>>> to access it as an array of 32bit registers wouldn't work at all. Plus we
>>> are not doing a full set of registers, and I rather not imply that every
>>> element in the "natural sequence" is present. It may be, it may be not.
>>
>>
>> Once an ABI is set in stone, and if that ABI allows for optimizations
>> (by consumers) like the one mentioned, I don't think this would be
>> careless use. The resulting code is very clearly much more efficient
>> than e.g. a switch() statement with a case label for each and every
>> register. Well, yes, I already hear the "memory is cheap and hence
>> code size doesn't matter" argument, but as said elsewhere quite
>> recently I don't buy this.
>
>
> I agree with Jan here.
>
> ARM64 has 31 general purposes registers (x0-x30). The switch to find a
> register based on the index will be quite big.
>
> If you order the register and provide all the general purposes registers (x0
> - x30), you will be able to replace by a single line (for instance see
> select_user_reg in arch/arm/traps.c).
The issue is that the x86 vm_event struct right now has 32*uint64_t
size. So if we would want to transmit all ARM64 GPRs + cpsr, PC and
TTBR0/1 we would end up growing this structure beyond what it is
currently. I want to avoid that as it affects both ARM32 and x86
introspection applications as well as now we can hold fewer events on
the ring. I would say it is better to avoid that then potentially
saving some on a switch in ARM64 introspection applications.
>
> This will also likely speed up your introspection application.
Win some, lose some. I would prefer if these changes had no
cross-architectural effect unless absolutely required. Razvan, what do
you think?
Tamas
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next prev parent reply other threads:[~2016-06-01 18:21 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-29 22:37 [PATCH v4 1/8] monitor: Rename vm_event_monitor_get_capabilities Tamas K Lengyel
2016-05-29 22:37 ` [PATCH v4 2/8] monitor: Rename vm_event_monitor_guest_request Tamas K Lengyel
2016-05-30 7:05 ` Razvan Cojocaru
2016-05-30 13:51 ` Jan Beulich
2016-05-29 22:37 ` [PATCH v4 3/8] monitor: Rename hvm/event to hvm/monitor Tamas K Lengyel
2016-05-30 7:08 ` Razvan Cojocaru
2016-05-30 13:53 ` Jan Beulich
2016-05-29 22:37 ` [PATCH v4 4/8] monitor: ARM SMC events Tamas K Lengyel
2016-06-01 11:37 ` Julien Grall
[not found] ` <CABfawhmO9tUG3-OcorfwqdOgZTkjoUk+u=dHySGonBDvobqyKw@mail.gmail.com>
[not found] ` <CABfawhmK2GAmQqZMhrgjYzeUZ_XaoyRUPuJxyPK5LJEHwsp5SA@mail.gmail.com>
[not found] ` <CABfawh=J1fwinTYKGvJNrFPOsGLSXz6U3GE8fxPz3-KsXSWfbQ@mail.gmail.com>
[not found] ` <CABfawhn7zvE=hn0hq1ryH+sW-jdkAXgZM1C2KxwZVUE8pbp8cQ@mail.gmail.com>
2016-06-01 15:41 ` Tamas K Lengyel
2016-06-02 14:23 ` Julien Grall
2016-06-02 22:31 ` Tamas K Lengyel
2016-07-04 19:13 ` Tamas K Lengyel
2016-07-04 20:02 ` Julien Grall
2016-07-04 21:05 ` Tamas K Lengyel
2016-07-05 9:58 ` Julien Grall
2016-05-29 22:37 ` [PATCH v4 5/8] arm/vm_event: get/set registers Tamas K Lengyel
2016-05-30 7:09 ` Razvan Cojocaru
2016-05-30 11:50 ` Jan Beulich
2016-05-30 19:47 ` Tamas K Lengyel
2016-05-30 20:20 ` Julien Grall
2016-05-30 20:37 ` Tamas K Lengyel
2016-05-30 20:46 ` Razvan Cojocaru
2016-05-30 20:53 ` Tamas K Lengyel
2016-05-30 21:35 ` Julien Grall
2016-05-30 21:41 ` Tamas K Lengyel
2016-05-31 7:54 ` Jan Beulich
2016-05-31 8:06 ` Razvan Cojocaru
2016-05-31 8:30 ` Jan Beulich
2016-05-31 16:20 ` Tamas K Lengyel
2016-05-31 7:48 ` Jan Beulich
2016-05-31 16:28 ` Tamas K Lengyel
2016-06-01 8:41 ` Jan Beulich
2016-06-01 11:24 ` Julien Grall
2016-06-01 18:21 ` Tamas K Lengyel [this message]
2016-06-01 19:34 ` Razvan Cojocaru
2016-06-01 19:43 ` Julien Grall
2016-06-02 7:35 ` Jan Beulich
2016-06-02 8:26 ` Razvan Cojocaru
2016-06-02 9:38 ` Jan Beulich
2016-06-02 9:42 ` Razvan Cojocaru
2016-06-01 19:38 ` Julien Grall
2016-06-01 19:49 ` Julien Grall
2016-06-01 19:50 ` Tamas K Lengyel
2016-05-29 22:37 ` [PATCH v4 6/8] tools/libxc: add xc_monitor_privileged_call Tamas K Lengyel
2016-05-29 22:37 ` [PATCH v4 7/8] tools/xen-access: add test-case for ARM SMC Tamas K Lengyel
2016-05-30 9:56 ` Wei Liu
2016-05-29 22:37 ` [PATCH v4 8/8] x86/vm_event: Add HVM debug exception vm_events Tamas K Lengyel
2016-05-30 7:29 ` Razvan Cojocaru
2016-05-30 14:16 ` Jan Beulich
2016-05-30 20:13 ` Tamas K Lengyel
2016-05-30 20:58 ` Andrew Cooper
2016-05-31 7:59 ` Jan Beulich
2016-06-01 21:46 ` Tamas K Lengyel
2016-06-01 22:17 ` Andrew Cooper
2016-06-02 0:01 ` Tamas K Lengyel
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