From: "Tian, Kevin" <kevin.tian@intel.com>
To: Igor Druzhinin <igor.druzhinin@citrix.com>,
"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: "Nakajima, Jun" <jun.nakajima@intel.com>,
"jbeulich@suse.com" <jbeulich@suse.com>,
"Cooper, Andrew" <andrew.cooper3@citrix.com>,
"roger.pau@citrix.com" <roger.pau@citrix.com>,
"wl@xen.org" <wl@xen.org>
Subject: RE: [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs
Date: Sun, 25 Apr 2021 01:07:24 +0000 [thread overview]
Message-ID: <MWHPR11MB1886B4AEB0921371EF676A6F8C439@MWHPR11MB1886.namprd11.prod.outlook.com> (raw)
In-Reply-To: <1618481062-16094-1-git-send-email-igor.druzhinin@citrix.com>
> From: Igor Druzhinin <igor.druzhinin@citrix.com>
> Sent: Thursday, April 15, 2021 6:04 PM
>
> This MSR exists since Nehalem / Silvermont and is actively used by Linux,
> for instance, to improve sampling efficiency.
>
> Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
> ---
> Changes in v5:
> - added Silvermont+ LBR_SELECT support
>
> New patch in v4 as suggested by Andrew.
> ---
> xen/arch/x86/hvm/vmx/vmx.c | 20 ++++++++++++++++----
> xen/include/asm-x86/msr-index.h | 10 ++++++++--
> 2 files changed, 24 insertions(+), 6 deletions(-)
>
> diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
> index 835b905..30c6a57 100644
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2915,14 +2915,16 @@ static const struct lbr_info {
> }, nh_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_C2_LASTBRANCH_TOS, 1 },
> + { MSR_NHL_LBR_SELECT, 1 },
> + { MSR_NHL_LASTBRANCH_TOS, 1 },
> { MSR_P4_LASTBRANCH_0_FROM_LIP,
> NUM_MSR_P4_LASTBRANCH_FROM_TO },
> { MSR_P4_LASTBRANCH_0_TO_LIP,
> NUM_MSR_P4_LASTBRANCH_FROM_TO },
> { 0, 0 }
> }, sk_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_SKL_LASTBRANCH_TOS, 1 },
> + { MSR_NHL_LBR_SELECT, 1 },
> + { MSR_NHL_LASTBRANCH_TOS, 1 },
> { MSR_SKL_LASTBRANCH_0_FROM_IP, NUM_MSR_SKL_LASTBRANCH },
> { MSR_SKL_LASTBRANCH_0_TO_IP, NUM_MSR_SKL_LASTBRANCH },
> { MSR_SKL_LASTBRANCH_0_INFO, NUM_MSR_SKL_LASTBRANCH },
> @@ -2934,10 +2936,19 @@ static const struct lbr_info {
> { MSR_C2_LASTBRANCH_0_FROM_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> { MSR_C2_LASTBRANCH_0_TO_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> { 0, 0 }
> +}, sm_lbr[] = {
> + { MSR_IA32_LASTINTFROMIP, 1 },
> + { MSR_IA32_LASTINTTOIP, 1 },
> + { MSR_SM_LBR_SELECT, 1 },
> + { MSR_SM_LASTBRANCH_TOS, 1 },
> + { MSR_C2_LASTBRANCH_0_FROM_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> + { MSR_C2_LASTBRANCH_0_TO_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> + { 0, 0 }
> }, gm_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_GM_LASTBRANCH_TOS, 1 },
> + { MSR_SM_LBR_SELECT, 1 },
> + { MSR_SM_LASTBRANCH_TOS, 1 },
> { MSR_GM_LASTBRANCH_0_FROM_IP,
> NUM_MSR_GM_LASTBRANCH_FROM_TO },
> { MSR_GM_LASTBRANCH_0_TO_IP,
> NUM_MSR_GM_LASTBRANCH_FROM_TO },
> { 0, 0 }
> @@ -2991,6 +3002,7 @@ static const struct lbr_info
> *last_branch_msr_get(void)
> return sk_lbr;
> /* Atom */
> case 0x1c: case 0x26: case 0x27: case 0x35: case 0x36:
> + return at_lbr;
> /* Silvermont */
> case 0x37: case 0x4a: case 0x4d: case 0x5a: case 0x5d:
> /* Xeon Phi Knights Landing */
> @@ -2999,7 +3011,7 @@ static const struct lbr_info
> *last_branch_msr_get(void)
> case 0x85:
> /* Airmont */
> case 0x4c:
> - return at_lbr;
> + return sm_lbr;
> /* Goldmont */
> case 0x5c: case 0x5f:
> return gm_lbr;
> diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-
> index.h
> index 43d26ef..020908f 100644
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -606,15 +606,21 @@
> #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
> #define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
>
> +/* Nehalem (and newer) last-branch recording */
> +#define MSR_NHL_LBR_SELECT 0x000001c8
> +#define MSR_NHL_LASTBRANCH_TOS 0x000001c9
> +
> /* Skylake (and newer) last-branch recording */
> -#define MSR_SKL_LASTBRANCH_TOS 0x000001c9
> #define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680
> #define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0
> #define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0
> #define NUM_MSR_SKL_LASTBRANCH 32
>
> +/* Silvermont (and newer) last-branch recording */
> +#define MSR_SM_LBR_SELECT 0x000001c8
> +#define MSR_SM_LASTBRANCH_TOS 0x000001c9
> +
> /* Goldmont last-branch recording */
> -#define MSR_GM_LASTBRANCH_TOS 0x000001c9
> #define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680
> #define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0
> #define NUM_MSR_GM_LASTBRANCH_FROM_TO 32
> --
> 2.7.4
prev parent reply other threads:[~2021-04-25 1:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-15 10:04 [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Igor Druzhinin
2021-04-15 10:04 ` [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers Igor Druzhinin
2021-04-25 1:07 ` Tian, Kevin
2021-04-15 11:50 ` [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Jan Beulich
2021-04-25 1:07 ` Tian, Kevin [this message]
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