* [Xen-devel] [PATCH v6 1/6] x86/hvm: allow ASID flush when v != current
2020-03-03 17:20 [Xen-devel] [PATCH v6 0/6] x86: improve assisted tlb flush and use it in guest mode Roger Pau Monne
@ 2020-03-03 17:20 ` Roger Pau Monne
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks Roger Pau Monne
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Roger Pau Monne @ 2020-03-03 17:20 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Wei Liu, Jan Beulich, Roger Pau Monne
Current implementation of hvm_asid_flush_vcpu is not safe to use
unless the target vCPU is either paused or the currently running one,
as it modifies the generation without any locking.
Fix this by using atomic operations when accessing the generation
field, both in hvm_asid_flush_vcpu_asid and other ASID functions. This
allows to safely flush the current ASID generation. Note that for the
flush to take effect if the vCPU is currently running a vmexit is
required.
Compilers will normally do such writes and reads as a single
instruction, so the usage of atomic operations is mostly used as a
safety measure.
Note the same could be achieved by introducing an extra field to
hvm_vcpu_asid that signals hvm_asid_handle_vmenter the need to call
hvm_asid_flush_vcpu on the given vCPU before vmentry, this however
seems unnecessary as hvm_asid_flush_vcpu itself only sets two vCPU
fields to 0, so there's no need to delay this to the vmentry ASID
helper.
This is not a bugfix as no callers that would violate the assumptions
listed in the first paragraph have been found, but a preparatory
change in order to allow remote flushing of HVM vCPUs.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
xen/arch/x86/hvm/asid.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/hvm/asid.c b/xen/arch/x86/hvm/asid.c
index 8e00a28443..63ce462d56 100644
--- a/xen/arch/x86/hvm/asid.c
+++ b/xen/arch/x86/hvm/asid.c
@@ -83,7 +83,7 @@ void hvm_asid_init(int nasids)
void hvm_asid_flush_vcpu_asid(struct hvm_vcpu_asid *asid)
{
- asid->generation = 0;
+ write_atomic(&asid->generation, 0);
}
void hvm_asid_flush_vcpu(struct vcpu *v)
@@ -121,7 +121,7 @@ bool_t hvm_asid_handle_vmenter(struct hvm_vcpu_asid *asid)
goto disabled;
/* Test if VCPU has valid ASID. */
- if ( asid->generation == data->core_asid_generation )
+ if ( read_atomic(&asid->generation) == data->core_asid_generation )
return 0;
/* If there are no free ASIDs, need to go to a new generation */
@@ -135,7 +135,7 @@ bool_t hvm_asid_handle_vmenter(struct hvm_vcpu_asid *asid)
/* Now guaranteed to be a free ASID. */
asid->asid = data->next_asid++;
- asid->generation = data->core_asid_generation;
+ write_atomic(&asid->generation, data->core_asid_generation);
/*
* When we assign ASID 1, flush all TLB entries as we are starting a new
--
2.25.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks
2020-03-03 17:20 [Xen-devel] [PATCH v6 0/6] x86: improve assisted tlb flush and use it in guest mode Roger Pau Monne
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 1/6] x86/hvm: allow ASID flush when v != current Roger Pau Monne
@ 2020-03-03 17:20 ` Roger Pau Monne
2020-03-03 17:26 ` Durrant, Paul
2020-03-05 15:37 ` Jan Beulich
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 3/6] x86/hap: improve hypervisor assisted guest TLB flush Roger Pau Monne
` (3 subsequent siblings)
5 siblings, 2 replies; 13+ messages in thread
From: Roger Pau Monne @ 2020-03-03 17:20 UTC (permalink / raw)
To: xen-devel
Cc: Wei Liu, Andrew Cooper, Paul Durrant, Tim Deegan, George Dunlap,
Jan Beulich, Roger Pau Monne
Add shadow and hap implementation specific helpers to perform guest
TLB flushes. Note that the code for both is exactly the same at the
moment, and is copied from hvm_flush_vcpu_tlb. This will be changed by
further patches that will add implementation specific optimizations to
them.
No functional change intended.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
Acked-by: Tim Deegan <tim@xen.org>
---
Changes since v5:
- Make the flush tlb operation a paging_mode hook.
Changes since v3:
- Fix stray newline removal.
- Fix return of shadow_flush_tlb dummy function.
---
xen/arch/x86/hvm/hvm.c | 56 +--------------------------
xen/arch/x86/hvm/viridian/viridian.c | 2 +-
xen/arch/x86/mm/hap/hap.c | 58 ++++++++++++++++++++++++++++
xen/arch/x86/mm/shadow/common.c | 55 ++++++++++++++++++++++++++
xen/arch/x86/mm/shadow/multi.c | 1 +
xen/arch/x86/mm/shadow/private.h | 4 ++
xen/include/asm-x86/hvm/hvm.h | 3 --
xen/include/asm-x86/paging.h | 10 +++++
8 files changed, 130 insertions(+), 59 deletions(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index db5d7b4d30..a2abad9f76 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3988,60 +3988,6 @@ static void hvm_s3_resume(struct domain *d)
}
}
-bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
- void *ctxt)
-{
- static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
- cpumask_t *mask = &this_cpu(flush_cpumask);
- struct domain *d = current->domain;
- struct vcpu *v;
-
- /* Avoid deadlock if more than one vcpu tries this at the same time. */
- if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
- return false;
-
- /* Pause all other vcpus. */
- for_each_vcpu ( d, v )
- if ( v != current && flush_vcpu(ctxt, v) )
- vcpu_pause_nosync(v);
-
- /* Now that all VCPUs are signalled to deschedule, we wait... */
- for_each_vcpu ( d, v )
- if ( v != current && flush_vcpu(ctxt, v) )
- while ( !vcpu_runnable(v) && v->is_running )
- cpu_relax();
-
- /* All other vcpus are paused, safe to unlock now. */
- spin_unlock(&d->hypercall_deadlock_mutex);
-
- cpumask_clear(mask);
-
- /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
- for_each_vcpu ( d, v )
- {
- unsigned int cpu;
-
- if ( !flush_vcpu(ctxt, v) )
- continue;
-
- paging_update_cr3(v, false);
-
- cpu = read_atomic(&v->dirty_cpu);
- if ( is_vcpu_dirty_cpu(cpu) )
- __cpumask_set_cpu(cpu, mask);
- }
-
- /* Flush TLBs on all CPUs with dirty vcpu state. */
- flush_tlb_mask(mask);
-
- /* Done. */
- for_each_vcpu ( d, v )
- if ( v != current && flush_vcpu(ctxt, v) )
- vcpu_unpause(v);
-
- return true;
-}
-
static bool always_flush(void *ctxt, struct vcpu *v)
{
return true;
@@ -4052,7 +3998,7 @@ static int hvmop_flush_tlb_all(void)
if ( !is_hvm_domain(current->domain) )
return -EINVAL;
- return hvm_flush_vcpu_tlb(always_flush, NULL) ? 0 : -ERESTART;
+ return paging_flush_tlb(always_flush, NULL) ? 0 : -ERESTART;
}
static int hvmop_set_evtchn_upcall_vector(
diff --git a/xen/arch/x86/hvm/viridian/viridian.c b/xen/arch/x86/hvm/viridian/viridian.c
index cd8f210198..977c1bc54f 100644
--- a/xen/arch/x86/hvm/viridian/viridian.c
+++ b/xen/arch/x86/hvm/viridian/viridian.c
@@ -609,7 +609,7 @@ int viridian_hypercall(struct cpu_user_regs *regs)
* A false return means that another vcpu is currently trying
* a similar operation, so back off.
*/
- if ( !hvm_flush_vcpu_tlb(need_flush, &input_params.vcpu_mask) )
+ if ( !paging_flush_tlb(need_flush, &input_params.vcpu_mask) )
return HVM_HCALL_preempted;
output.rep_complete = input.rep_count;
diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c
index 3d93f3451c..5616235bd8 100644
--- a/xen/arch/x86/mm/hap/hap.c
+++ b/xen/arch/x86/mm/hap/hap.c
@@ -669,6 +669,60 @@ static void hap_update_cr3(struct vcpu *v, int do_locking, bool noflush)
hvm_update_guest_cr3(v, noflush);
}
+static bool flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
+ void *ctxt)
+{
+ static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
+ cpumask_t *mask = &this_cpu(flush_cpumask);
+ struct domain *d = current->domain;
+ struct vcpu *v;
+
+ /* Avoid deadlock if more than one vcpu tries this at the same time. */
+ if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
+ return false;
+
+ /* Pause all other vcpus. */
+ for_each_vcpu ( d, v )
+ if ( v != current && flush_vcpu(ctxt, v) )
+ vcpu_pause_nosync(v);
+
+ /* Now that all VCPUs are signalled to deschedule, we wait... */
+ for_each_vcpu ( d, v )
+ if ( v != current && flush_vcpu(ctxt, v) )
+ while ( !vcpu_runnable(v) && v->is_running )
+ cpu_relax();
+
+ /* All other vcpus are paused, safe to unlock now. */
+ spin_unlock(&d->hypercall_deadlock_mutex);
+
+ cpumask_clear(mask);
+
+ /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
+ for_each_vcpu ( d, v )
+ {
+ unsigned int cpu;
+
+ if ( !flush_vcpu(ctxt, v) )
+ continue;
+
+ paging_update_cr3(v, false);
+
+ cpu = read_atomic(&v->dirty_cpu);
+ if ( is_vcpu_dirty_cpu(cpu) )
+ __cpumask_set_cpu(cpu, mask);
+ }
+
+ /* Flush TLBs on all CPUs with dirty vcpu state. */
+ flush_tlb_mask(mask);
+
+ /* Done. */
+ for_each_vcpu ( d, v )
+ if ( v != current && flush_vcpu(ctxt, v) )
+ vcpu_unpause(v);
+
+ return true;
+}
+
const struct paging_mode *
hap_paging_get_mode(struct vcpu *v)
{
@@ -781,6 +835,7 @@ static const struct paging_mode hap_paging_real_mode = {
.update_cr3 = hap_update_cr3,
.update_paging_modes = hap_update_paging_modes,
.write_p2m_entry = hap_write_p2m_entry,
+ .flush_tlb = flush_tlb,
.guest_levels = 1
};
@@ -792,6 +847,7 @@ static const struct paging_mode hap_paging_protected_mode = {
.update_cr3 = hap_update_cr3,
.update_paging_modes = hap_update_paging_modes,
.write_p2m_entry = hap_write_p2m_entry,
+ .flush_tlb = flush_tlb,
.guest_levels = 2
};
@@ -803,6 +859,7 @@ static const struct paging_mode hap_paging_pae_mode = {
.update_cr3 = hap_update_cr3,
.update_paging_modes = hap_update_paging_modes,
.write_p2m_entry = hap_write_p2m_entry,
+ .flush_tlb = flush_tlb,
.guest_levels = 3
};
@@ -814,6 +871,7 @@ static const struct paging_mode hap_paging_long_mode = {
.update_cr3 = hap_update_cr3,
.update_paging_modes = hap_update_paging_modes,
.write_p2m_entry = hap_write_p2m_entry,
+ .flush_tlb = flush_tlb,
.guest_levels = 4
};
diff --git a/xen/arch/x86/mm/shadow/common.c b/xen/arch/x86/mm/shadow/common.c
index cba3ab1eba..121ddf1255 100644
--- a/xen/arch/x86/mm/shadow/common.c
+++ b/xen/arch/x86/mm/shadow/common.c
@@ -3357,6 +3357,61 @@ out:
return rc;
}
+/* Fluhs TLB of selected vCPUs. */
+bool shadow_flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
+ void *ctxt)
+{
+ static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
+ cpumask_t *mask = &this_cpu(flush_cpumask);
+ struct domain *d = current->domain;
+ struct vcpu *v;
+
+ /* Avoid deadlock if more than one vcpu tries this at the same time. */
+ if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
+ return false;
+
+ /* Pause all other vcpus. */
+ for_each_vcpu ( d, v )
+ if ( v != current && flush_vcpu(ctxt, v) )
+ vcpu_pause_nosync(v);
+
+ /* Now that all VCPUs are signalled to deschedule, we wait... */
+ for_each_vcpu ( d, v )
+ if ( v != current && flush_vcpu(ctxt, v) )
+ while ( !vcpu_runnable(v) && v->is_running )
+ cpu_relax();
+
+ /* All other vcpus are paused, safe to unlock now. */
+ spin_unlock(&d->hypercall_deadlock_mutex);
+
+ cpumask_clear(mask);
+
+ /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
+ for_each_vcpu ( d, v )
+ {
+ unsigned int cpu;
+
+ if ( !flush_vcpu(ctxt, v) )
+ continue;
+
+ paging_update_cr3(v, false);
+
+ cpu = read_atomic(&v->dirty_cpu);
+ if ( is_vcpu_dirty_cpu(cpu) )
+ __cpumask_set_cpu(cpu, mask);
+ }
+
+ /* Flush TLBs on all CPUs with dirty vcpu state. */
+ flush_tlb_mask(mask);
+
+ /* Done. */
+ for_each_vcpu ( d, v )
+ if ( v != current && flush_vcpu(ctxt, v) )
+ vcpu_unpause(v);
+
+ return true;
+}
+
/**************************************************************************/
/* Shadow-control XEN_DOMCTL dispatcher */
diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c
index 26798b317c..b6afc0fba4 100644
--- a/xen/arch/x86/mm/shadow/multi.c
+++ b/xen/arch/x86/mm/shadow/multi.c
@@ -4873,6 +4873,7 @@ const struct paging_mode sh_paging_mode = {
.update_cr3 = sh_update_cr3,
.update_paging_modes = shadow_update_paging_modes,
.write_p2m_entry = shadow_write_p2m_entry,
+ .flush_tlb = shadow_flush_tlb,
.guest_levels = GUEST_PAGING_LEVELS,
.shadow.detach_old_tables = sh_detach_old_tables,
#ifdef CONFIG_PV
diff --git a/xen/arch/x86/mm/shadow/private.h b/xen/arch/x86/mm/shadow/private.h
index 3217777921..e8b028a365 100644
--- a/xen/arch/x86/mm/shadow/private.h
+++ b/xen/arch/x86/mm/shadow/private.h
@@ -814,6 +814,10 @@ static inline int sh_check_page_has_no_refs(struct page_info *page)
((count & PGC_allocated) ? 1 : 0) );
}
+/* Flush the TLB of the selected vCPUs. */
+bool shadow_flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
+ void *ctxt);
+
#endif /* _XEN_SHADOW_PRIVATE_H */
/*
diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h
index 24da824cbf..aae00a7860 100644
--- a/xen/include/asm-x86/hvm/hvm.h
+++ b/xen/include/asm-x86/hvm/hvm.h
@@ -334,9 +334,6 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value,
signed int cr0_pg);
unsigned long hvm_cr4_guest_valid_bits(const struct domain *d, bool restore);
-bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
- void *ctxt);
-
int hvm_copy_context_and_params(struct domain *src, struct domain *dst);
#ifdef CONFIG_HVM
diff --git a/xen/include/asm-x86/paging.h b/xen/include/asm-x86/paging.h
index 7544f73121..051161481c 100644
--- a/xen/include/asm-x86/paging.h
+++ b/xen/include/asm-x86/paging.h
@@ -140,6 +140,9 @@ struct paging_mode {
unsigned long gfn,
l1_pgentry_t *p, l1_pgentry_t new,
unsigned int level);
+ bool (*flush_tlb )(bool (*flush_vcpu)(void *ctxt,
+ struct vcpu *v),
+ void *ctxt);
unsigned int guest_levels;
@@ -397,6 +400,13 @@ static always_inline unsigned int paging_max_paddr_bits(const struct domain *d)
return bits;
}
+static inline bool paging_flush_tlb(bool (*flush_vcpu)(void *ctxt,
+ struct vcpu *v),
+ void *ctxt)
+{
+ return paging_get_hostmode(current)->flush_tlb(flush_vcpu, ctxt);
+}
+
#endif /* XEN_PAGING_H */
/*
--
2.25.0
_______________________________________________
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Xen-devel@lists.xenproject.org
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks Roger Pau Monne
@ 2020-03-03 17:26 ` Durrant, Paul
2020-03-05 15:37 ` Jan Beulich
1 sibling, 0 replies; 13+ messages in thread
From: Durrant, Paul @ 2020-03-03 17:26 UTC (permalink / raw)
To: Roger Pau Monne, xen-devel
Cc: Andrew Cooper, Jan Beulich, Tim Deegan, George Dunlap, Wei Liu
> -----Original Message-----
> From: Xen-devel <xen-devel-bounces@lists.xenproject.org> On Behalf Of Roger Pau Monne
> Sent: 03 March 2020 17:21
> To: xen-devel@lists.xenproject.org
> Cc: Wei Liu <wl@xen.org>; Andrew Cooper <andrew.cooper3@citrix.com>; Durrant, Paul
> <pdurrant@amazon.co.uk>; Tim Deegan <tim@xen.org>; George Dunlap <george.dunlap@citrix.com>; Jan
> Beulich <jbeulich@suse.com>; Roger Pau Monne <roger.pau@citrix.com>
> Subject: [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks
>
> Add shadow and hap implementation specific helpers to perform guest
> TLB flushes. Note that the code for both is exactly the same at the
> moment, and is copied from hvm_flush_vcpu_tlb. This will be changed by
> further patches that will add implementation specific optimizations to
> them.
>
> No functional change intended.
>
> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Viridian part...
Reviewed-by: Paul Durrant <pdurrant@amzn.com>
> Reviewed-by: Wei Liu <wl@xen.org>
> Acked-by: Tim Deegan <tim@xen.org>
> ---
> Changes since v5:
> - Make the flush tlb operation a paging_mode hook.
>
> Changes since v3:
> - Fix stray newline removal.
> - Fix return of shadow_flush_tlb dummy function.
> ---
> xen/arch/x86/hvm/hvm.c | 56 +--------------------------
> xen/arch/x86/hvm/viridian/viridian.c | 2 +-
> xen/arch/x86/mm/hap/hap.c | 58 ++++++++++++++++++++++++++++
> xen/arch/x86/mm/shadow/common.c | 55 ++++++++++++++++++++++++++
> xen/arch/x86/mm/shadow/multi.c | 1 +
> xen/arch/x86/mm/shadow/private.h | 4 ++
> xen/include/asm-x86/hvm/hvm.h | 3 --
> xen/include/asm-x86/paging.h | 10 +++++
> 8 files changed, 130 insertions(+), 59 deletions(-)
>
> diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
> index db5d7b4d30..a2abad9f76 100644
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -3988,60 +3988,6 @@ static void hvm_s3_resume(struct domain *d)
> }
> }
>
> -bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
> - void *ctxt)
> -{
> - static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
> - cpumask_t *mask = &this_cpu(flush_cpumask);
> - struct domain *d = current->domain;
> - struct vcpu *v;
> -
> - /* Avoid deadlock if more than one vcpu tries this at the same time. */
> - if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
> - return false;
> -
> - /* Pause all other vcpus. */
> - for_each_vcpu ( d, v )
> - if ( v != current && flush_vcpu(ctxt, v) )
> - vcpu_pause_nosync(v);
> -
> - /* Now that all VCPUs are signalled to deschedule, we wait... */
> - for_each_vcpu ( d, v )
> - if ( v != current && flush_vcpu(ctxt, v) )
> - while ( !vcpu_runnable(v) && v->is_running )
> - cpu_relax();
> -
> - /* All other vcpus are paused, safe to unlock now. */
> - spin_unlock(&d->hypercall_deadlock_mutex);
> -
> - cpumask_clear(mask);
> -
> - /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
> - for_each_vcpu ( d, v )
> - {
> - unsigned int cpu;
> -
> - if ( !flush_vcpu(ctxt, v) )
> - continue;
> -
> - paging_update_cr3(v, false);
> -
> - cpu = read_atomic(&v->dirty_cpu);
> - if ( is_vcpu_dirty_cpu(cpu) )
> - __cpumask_set_cpu(cpu, mask);
> - }
> -
> - /* Flush TLBs on all CPUs with dirty vcpu state. */
> - flush_tlb_mask(mask);
> -
> - /* Done. */
> - for_each_vcpu ( d, v )
> - if ( v != current && flush_vcpu(ctxt, v) )
> - vcpu_unpause(v);
> -
> - return true;
> -}
> -
> static bool always_flush(void *ctxt, struct vcpu *v)
> {
> return true;
> @@ -4052,7 +3998,7 @@ static int hvmop_flush_tlb_all(void)
> if ( !is_hvm_domain(current->domain) )
> return -EINVAL;
>
> - return hvm_flush_vcpu_tlb(always_flush, NULL) ? 0 : -ERESTART;
> + return paging_flush_tlb(always_flush, NULL) ? 0 : -ERESTART;
> }
>
> static int hvmop_set_evtchn_upcall_vector(
> diff --git a/xen/arch/x86/hvm/viridian/viridian.c b/xen/arch/x86/hvm/viridian/viridian.c
> index cd8f210198..977c1bc54f 100644
> --- a/xen/arch/x86/hvm/viridian/viridian.c
> +++ b/xen/arch/x86/hvm/viridian/viridian.c
> @@ -609,7 +609,7 @@ int viridian_hypercall(struct cpu_user_regs *regs)
> * A false return means that another vcpu is currently trying
> * a similar operation, so back off.
> */
> - if ( !hvm_flush_vcpu_tlb(need_flush, &input_params.vcpu_mask) )
> + if ( !paging_flush_tlb(need_flush, &input_params.vcpu_mask) )
> return HVM_HCALL_preempted;
>
> output.rep_complete = input.rep_count;
> diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c
> index 3d93f3451c..5616235bd8 100644
> --- a/xen/arch/x86/mm/hap/hap.c
> +++ b/xen/arch/x86/mm/hap/hap.c
> @@ -669,6 +669,60 @@ static void hap_update_cr3(struct vcpu *v, int do_locking, bool noflush)
> hvm_update_guest_cr3(v, noflush);
> }
>
> +static bool flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
> + void *ctxt)
> +{
> + static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
> + cpumask_t *mask = &this_cpu(flush_cpumask);
> + struct domain *d = current->domain;
> + struct vcpu *v;
> +
> + /* Avoid deadlock if more than one vcpu tries this at the same time. */
> + if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
> + return false;
> +
> + /* Pause all other vcpus. */
> + for_each_vcpu ( d, v )
> + if ( v != current && flush_vcpu(ctxt, v) )
> + vcpu_pause_nosync(v);
> +
> + /* Now that all VCPUs are signalled to deschedule, we wait... */
> + for_each_vcpu ( d, v )
> + if ( v != current && flush_vcpu(ctxt, v) )
> + while ( !vcpu_runnable(v) && v->is_running )
> + cpu_relax();
> +
> + /* All other vcpus are paused, safe to unlock now. */
> + spin_unlock(&d->hypercall_deadlock_mutex);
> +
> + cpumask_clear(mask);
> +
> + /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
> + for_each_vcpu ( d, v )
> + {
> + unsigned int cpu;
> +
> + if ( !flush_vcpu(ctxt, v) )
> + continue;
> +
> + paging_update_cr3(v, false);
> +
> + cpu = read_atomic(&v->dirty_cpu);
> + if ( is_vcpu_dirty_cpu(cpu) )
> + __cpumask_set_cpu(cpu, mask);
> + }
> +
> + /* Flush TLBs on all CPUs with dirty vcpu state. */
> + flush_tlb_mask(mask);
> +
> + /* Done. */
> + for_each_vcpu ( d, v )
> + if ( v != current && flush_vcpu(ctxt, v) )
> + vcpu_unpause(v);
> +
> + return true;
> +}
> +
> const struct paging_mode *
> hap_paging_get_mode(struct vcpu *v)
> {
> @@ -781,6 +835,7 @@ static const struct paging_mode hap_paging_real_mode = {
> .update_cr3 = hap_update_cr3,
> .update_paging_modes = hap_update_paging_modes,
> .write_p2m_entry = hap_write_p2m_entry,
> + .flush_tlb = flush_tlb,
> .guest_levels = 1
> };
>
> @@ -792,6 +847,7 @@ static const struct paging_mode hap_paging_protected_mode = {
> .update_cr3 = hap_update_cr3,
> .update_paging_modes = hap_update_paging_modes,
> .write_p2m_entry = hap_write_p2m_entry,
> + .flush_tlb = flush_tlb,
> .guest_levels = 2
> };
>
> @@ -803,6 +859,7 @@ static const struct paging_mode hap_paging_pae_mode = {
> .update_cr3 = hap_update_cr3,
> .update_paging_modes = hap_update_paging_modes,
> .write_p2m_entry = hap_write_p2m_entry,
> + .flush_tlb = flush_tlb,
> .guest_levels = 3
> };
>
> @@ -814,6 +871,7 @@ static const struct paging_mode hap_paging_long_mode = {
> .update_cr3 = hap_update_cr3,
> .update_paging_modes = hap_update_paging_modes,
> .write_p2m_entry = hap_write_p2m_entry,
> + .flush_tlb = flush_tlb,
> .guest_levels = 4
> };
>
> diff --git a/xen/arch/x86/mm/shadow/common.c b/xen/arch/x86/mm/shadow/common.c
> index cba3ab1eba..121ddf1255 100644
> --- a/xen/arch/x86/mm/shadow/common.c
> +++ b/xen/arch/x86/mm/shadow/common.c
> @@ -3357,6 +3357,61 @@ out:
> return rc;
> }
>
> +/* Fluhs TLB of selected vCPUs. */
> +bool shadow_flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
> + void *ctxt)
> +{
> + static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
> + cpumask_t *mask = &this_cpu(flush_cpumask);
> + struct domain *d = current->domain;
> + struct vcpu *v;
> +
> + /* Avoid deadlock if more than one vcpu tries this at the same time. */
> + if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
> + return false;
> +
> + /* Pause all other vcpus. */
> + for_each_vcpu ( d, v )
> + if ( v != current && flush_vcpu(ctxt, v) )
> + vcpu_pause_nosync(v);
> +
> + /* Now that all VCPUs are signalled to deschedule, we wait... */
> + for_each_vcpu ( d, v )
> + if ( v != current && flush_vcpu(ctxt, v) )
> + while ( !vcpu_runnable(v) && v->is_running )
> + cpu_relax();
> +
> + /* All other vcpus are paused, safe to unlock now. */
> + spin_unlock(&d->hypercall_deadlock_mutex);
> +
> + cpumask_clear(mask);
> +
> + /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
> + for_each_vcpu ( d, v )
> + {
> + unsigned int cpu;
> +
> + if ( !flush_vcpu(ctxt, v) )
> + continue;
> +
> + paging_update_cr3(v, false);
> +
> + cpu = read_atomic(&v->dirty_cpu);
> + if ( is_vcpu_dirty_cpu(cpu) )
> + __cpumask_set_cpu(cpu, mask);
> + }
> +
> + /* Flush TLBs on all CPUs with dirty vcpu state. */
> + flush_tlb_mask(mask);
> +
> + /* Done. */
> + for_each_vcpu ( d, v )
> + if ( v != current && flush_vcpu(ctxt, v) )
> + vcpu_unpause(v);
> +
> + return true;
> +}
> +
> /**************************************************************************/
> /* Shadow-control XEN_DOMCTL dispatcher */
>
> diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c
> index 26798b317c..b6afc0fba4 100644
> --- a/xen/arch/x86/mm/shadow/multi.c
> +++ b/xen/arch/x86/mm/shadow/multi.c
> @@ -4873,6 +4873,7 @@ const struct paging_mode sh_paging_mode = {
> .update_cr3 = sh_update_cr3,
> .update_paging_modes = shadow_update_paging_modes,
> .write_p2m_entry = shadow_write_p2m_entry,
> + .flush_tlb = shadow_flush_tlb,
> .guest_levels = GUEST_PAGING_LEVELS,
> .shadow.detach_old_tables = sh_detach_old_tables,
> #ifdef CONFIG_PV
> diff --git a/xen/arch/x86/mm/shadow/private.h b/xen/arch/x86/mm/shadow/private.h
> index 3217777921..e8b028a365 100644
> --- a/xen/arch/x86/mm/shadow/private.h
> +++ b/xen/arch/x86/mm/shadow/private.h
> @@ -814,6 +814,10 @@ static inline int sh_check_page_has_no_refs(struct page_info *page)
> ((count & PGC_allocated) ? 1 : 0) );
> }
>
> +/* Flush the TLB of the selected vCPUs. */
> +bool shadow_flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
> + void *ctxt);
> +
> #endif /* _XEN_SHADOW_PRIVATE_H */
>
> /*
> diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h
> index 24da824cbf..aae00a7860 100644
> --- a/xen/include/asm-x86/hvm/hvm.h
> +++ b/xen/include/asm-x86/hvm/hvm.h
> @@ -334,9 +334,6 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value,
> signed int cr0_pg);
> unsigned long hvm_cr4_guest_valid_bits(const struct domain *d, bool restore);
>
> -bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
> - void *ctxt);
> -
> int hvm_copy_context_and_params(struct domain *src, struct domain *dst);
>
> #ifdef CONFIG_HVM
> diff --git a/xen/include/asm-x86/paging.h b/xen/include/asm-x86/paging.h
> index 7544f73121..051161481c 100644
> --- a/xen/include/asm-x86/paging.h
> +++ b/xen/include/asm-x86/paging.h
> @@ -140,6 +140,9 @@ struct paging_mode {
> unsigned long gfn,
> l1_pgentry_t *p, l1_pgentry_t new,
> unsigned int level);
> + bool (*flush_tlb )(bool (*flush_vcpu)(void *ctxt,
> + struct vcpu *v),
> + void *ctxt);
>
> unsigned int guest_levels;
>
> @@ -397,6 +400,13 @@ static always_inline unsigned int paging_max_paddr_bits(const struct domain *d)
> return bits;
> }
>
> +static inline bool paging_flush_tlb(bool (*flush_vcpu)(void *ctxt,
> + struct vcpu *v),
> + void *ctxt)
> +{
> + return paging_get_hostmode(current)->flush_tlb(flush_vcpu, ctxt);
> +}
> +
> #endif /* XEN_PAGING_H */
>
> /*
> --
> 2.25.0
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xenproject.org
> https://lists.xenproject.org/mailman/listinfo/xen-devel
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks Roger Pau Monne
2020-03-03 17:26 ` Durrant, Paul
@ 2020-03-05 15:37 ` Jan Beulich
1 sibling, 0 replies; 13+ messages in thread
From: Jan Beulich @ 2020-03-05 15:37 UTC (permalink / raw)
To: Roger Pau Monne
Cc: Wei Liu, Andrew Cooper, Paul Durrant, Tim Deegan, George Dunlap,
xen-devel
On 03.03.2020 18:20, Roger Pau Monne wrote:
> Add shadow and hap implementation specific helpers to perform guest
> TLB flushes. Note that the code for both is exactly the same at the
> moment, and is copied from hvm_flush_vcpu_tlb. This will be changed by
> further patches that will add implementation specific optimizations to
> them.
>
> No functional change intended.
>
> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
> Reviewed-by: Wei Liu <wl@xen.org>
> Acked-by: Tim Deegan <tim@xen.org>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
_______________________________________________
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [Xen-devel] [PATCH v6 3/6] x86/hap: improve hypervisor assisted guest TLB flush
2020-03-03 17:20 [Xen-devel] [PATCH v6 0/6] x86: improve assisted tlb flush and use it in guest mode Roger Pau Monne
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 1/6] x86/hvm: allow ASID flush when v != current Roger Pau Monne
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 2/6] x86/paging: add TLB flush hooks Roger Pau Monne
@ 2020-03-03 17:20 ` Roger Pau Monne
2020-03-05 15:38 ` Jan Beulich
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 4/6] x86/tlb: introduce a flush guests TLB flag Roger Pau Monne
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Roger Pau Monne @ 2020-03-03 17:20 UTC (permalink / raw)
To: xen-devel
Cc: Andrew Cooper, Wei Liu, George Dunlap, Jan Beulich, Roger Pau Monne
The current implementation of the hypervisor assisted flush for HAP is
extremely inefficient.
First of all there's no need to call paging_update_cr3, as the only
relevant part of that function when doing a flush is the ASID vCPU
flush, so just call that function directly.
Since hvm_asid_flush_vcpu is protected against concurrent callers by
using atomic operations there's no need anymore to pause the affected
vCPUs.
Finally the global TLB flush performed by flush_tlb_mask is also not
necessary, since we only want to flush the guest TLB state it's enough
to trigger a vmexit on the pCPUs currently holding any vCPU state, as
such vmexit will already perform an ASID/VPID update, and thus clear
the guest TLB.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
---
Changes since v5:
- Remove custom synchronization as on_selected_cpus already take care
of it.
- s/handle_flush/dummy_flush/.
- Update comment on dummy_flush helper.
Changes since v3:
- s/do_flush/handle_flush/.
- Add comment about handle_flush usage.
- Fix VPID typo in comment.
---
xen/arch/x86/mm/hap/hap.c | 46 ++++++++++++++++-----------------------
1 file changed, 19 insertions(+), 27 deletions(-)
diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c
index 5616235bd8..8dbbcc3676 100644
--- a/xen/arch/x86/mm/hap/hap.c
+++ b/xen/arch/x86/mm/hap/hap.c
@@ -669,32 +669,24 @@ static void hap_update_cr3(struct vcpu *v, int do_locking, bool noflush)
hvm_update_guest_cr3(v, noflush);
}
+/*
+ * Dummy function to use with on_selected_cpus in order to trigger a vmexit on
+ * selected pCPUs. When the VM resumes execution it will get a new ASID/VPID
+ * and thus a clean TLB.
+ */
+static void dummy_flush(void *data)
+{
+}
+
static bool flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
void *ctxt)
{
static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
cpumask_t *mask = &this_cpu(flush_cpumask);
struct domain *d = current->domain;
+ unsigned int this_cpu = smp_processor_id();
struct vcpu *v;
- /* Avoid deadlock if more than one vcpu tries this at the same time. */
- if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
- return false;
-
- /* Pause all other vcpus. */
- for_each_vcpu ( d, v )
- if ( v != current && flush_vcpu(ctxt, v) )
- vcpu_pause_nosync(v);
-
- /* Now that all VCPUs are signalled to deschedule, we wait... */
- for_each_vcpu ( d, v )
- if ( v != current && flush_vcpu(ctxt, v) )
- while ( !vcpu_runnable(v) && v->is_running )
- cpu_relax();
-
- /* All other vcpus are paused, safe to unlock now. */
- spin_unlock(&d->hypercall_deadlock_mutex);
-
cpumask_clear(mask);
/* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
@@ -705,20 +697,20 @@ static bool flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
if ( !flush_vcpu(ctxt, v) )
continue;
- paging_update_cr3(v, false);
+ hvm_asid_flush_vcpu(v);
cpu = read_atomic(&v->dirty_cpu);
- if ( is_vcpu_dirty_cpu(cpu) )
+ if ( cpu != this_cpu && is_vcpu_dirty_cpu(cpu) )
__cpumask_set_cpu(cpu, mask);
}
- /* Flush TLBs on all CPUs with dirty vcpu state. */
- flush_tlb_mask(mask);
-
- /* Done. */
- for_each_vcpu ( d, v )
- if ( v != current && flush_vcpu(ctxt, v) )
- vcpu_unpause(v);
+ /*
+ * Trigger a vmexit on all pCPUs with dirty vCPU state in order to force an
+ * ASID/VPID change and hence accomplish a guest TLB flush. Note that vCPUs
+ * not currently running will already be flushed when scheduled because of
+ * the ASID tickle done in the loop above.
+ */
+ on_selected_cpus(mask, dummy_flush, mask, 0);
return true;
}
--
2.25.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Xen-devel] [PATCH v6 3/6] x86/hap: improve hypervisor assisted guest TLB flush
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 3/6] x86/hap: improve hypervisor assisted guest TLB flush Roger Pau Monne
@ 2020-03-05 15:38 ` Jan Beulich
0 siblings, 0 replies; 13+ messages in thread
From: Jan Beulich @ 2020-03-05 15:38 UTC (permalink / raw)
To: Roger Pau Monne; +Cc: xen-devel, George Dunlap, Wei Liu, Andrew Cooper
On 03.03.2020 18:20, Roger Pau Monne wrote:
> The current implementation of the hypervisor assisted flush for HAP is
> extremely inefficient.
>
> First of all there's no need to call paging_update_cr3, as the only
> relevant part of that function when doing a flush is the ASID vCPU
> flush, so just call that function directly.
>
> Since hvm_asid_flush_vcpu is protected against concurrent callers by
> using atomic operations there's no need anymore to pause the affected
> vCPUs.
>
> Finally the global TLB flush performed by flush_tlb_mask is also not
> necessary, since we only want to flush the guest TLB state it's enough
> to trigger a vmexit on the pCPUs currently holding any vCPU state, as
> such vmexit will already perform an ASID/VPID update, and thus clear
> the guest TLB.
>
> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
> Reviewed-by: Wei Liu <wl@xen.org>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Xen-devel] [PATCH v6 4/6] x86/tlb: introduce a flush guests TLB flag
2020-03-03 17:20 [Xen-devel] [PATCH v6 0/6] x86: improve assisted tlb flush and use it in guest mode Roger Pau Monne
` (2 preceding siblings ...)
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 3/6] x86/hap: improve hypervisor assisted guest TLB flush Roger Pau Monne
@ 2020-03-03 17:20 ` Roger Pau Monne
2020-03-06 9:28 ` Jan Beulich
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 5/6] x86/tlb: allow disabling the TLB clock Roger Pau Monne
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 6/6] x86/tlb: use Xen L0 assisted TLB flush when available Roger Pau Monne
5 siblings, 1 reply; 13+ messages in thread
From: Roger Pau Monne @ 2020-03-03 17:20 UTC (permalink / raw)
To: xen-devel
Cc: Wei Liu, Andrew Cooper, Tim Deegan, George Dunlap, Jan Beulich,
Roger Pau Monne
Introduce a specific flag to request a HVM guest TLB flush, which is
an ASID/VPID tickle that forces a guest linear to guest physical TLB
flush for all HVM guests.
This was previously unconditionally done in each pre_flush call, but
that's not required: HVM guests not using shadow don't require linear
TLB flushes as Xen doesn't modify the guest page tables in that case
(ie: when using HAP). Note that shadow paging code already takes care
of issuing the necessary flushes when the shadow page tables are
modified.
In order to keep the previous behavior modify all shadow code TLB
flushes to also flush the guest linear to physical TLB, in order to
keep the previous behavior. I haven't looked at each specific shadow
code TLB flush in order to figure out whether it actually requires a
guest TLB flush or not, so there might be room for improvement in that
regard.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
Acked-by: Tim Deegan <tim@xen.org>
---
Changes since v5:
- Rename FLUSH_GUESTS_TLB to FLUSH_HVM_ASID_CORE.
- Clarify commit message.
- Define FLUSH_HVM_ASID_CORE to 0 when !CONFIG_HVM.
---
xen/arch/x86/flushtlb.c | 5 +++--
xen/arch/x86/mm/shadow/common.c | 18 +++++++++---------
xen/arch/x86/mm/shadow/hvm.c | 2 +-
xen/arch/x86/mm/shadow/multi.c | 16 ++++++++--------
xen/include/asm-x86/flushtlb.h | 6 ++++++
5 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c
index 03f92c23dc..c1305c7e6b 100644
--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -59,8 +59,6 @@ static u32 pre_flush(void)
raise_softirq(NEW_TLBFLUSH_CLOCK_PERIOD_SOFTIRQ);
skip_clocktick:
- hvm_flush_guest_tlbs();
-
return t2;
}
@@ -221,6 +219,9 @@ unsigned int flush_area_local(const void *va, unsigned int flags)
do_tlb_flush();
}
+ if ( flags & FLUSH_HVM_ASID_CORE )
+ hvm_flush_guest_tlbs();
+
if ( flags & FLUSH_CACHE )
{
const struct cpuinfo_x86 *c = ¤t_cpu_data;
diff --git a/xen/arch/x86/mm/shadow/common.c b/xen/arch/x86/mm/shadow/common.c
index 121ddf1255..aa750eafae 100644
--- a/xen/arch/x86/mm/shadow/common.c
+++ b/xen/arch/x86/mm/shadow/common.c
@@ -363,7 +363,7 @@ static int oos_remove_write_access(struct vcpu *v, mfn_t gmfn,
}
if ( ftlb )
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
return 0;
}
@@ -939,7 +939,7 @@ static void _shadow_prealloc(struct domain *d, unsigned int pages)
/* See if that freed up enough space */
if ( d->arch.paging.shadow.free_pages >= pages )
{
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
return;
}
}
@@ -993,7 +993,7 @@ static void shadow_blow_tables(struct domain *d)
pagetable_get_mfn(v->arch.shadow_table[i]), 0);
/* Make sure everyone sees the unshadowings */
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
}
void shadow_blow_tables_per_domain(struct domain *d)
@@ -1102,7 +1102,7 @@ mfn_t shadow_alloc(struct domain *d,
if ( unlikely(!cpumask_empty(&mask)) )
{
perfc_incr(shadow_alloc_tlbflush);
- flush_tlb_mask(&mask);
+ flush_mask(&mask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
}
/* Now safe to clear the page for reuse */
clear_domain_page(page_to_mfn(sp));
@@ -2290,7 +2290,7 @@ void sh_remove_shadows(struct domain *d, mfn_t gmfn, int fast, int all)
/* Need to flush TLBs now, so that linear maps are safe next time we
* take a fault. */
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
paging_unlock(d);
}
@@ -3005,7 +3005,7 @@ static void sh_unshadow_for_p2m_change(struct domain *d, unsigned long gfn,
{
sh_remove_all_shadows_and_parents(d, mfn);
if ( sh_remove_all_mappings(d, mfn, _gfn(gfn)) )
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
}
}
@@ -3045,7 +3045,7 @@ static void sh_unshadow_for_p2m_change(struct domain *d, unsigned long gfn,
}
omfn = mfn_add(omfn, 1);
}
- flush_tlb_mask(&flushmask);
+ flush_mask(&flushmask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
if ( npte )
unmap_domain_page(npte);
@@ -3332,7 +3332,7 @@ int shadow_track_dirty_vram(struct domain *d,
}
}
if ( flush_tlb )
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
goto out;
out_sl1ma:
@@ -3402,7 +3402,7 @@ bool shadow_flush_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
}
/* Flush TLBs on all CPUs with dirty vcpu state. */
- flush_tlb_mask(mask);
+ flush_mask(mask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
/* Done. */
for_each_vcpu ( d, v )
diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index 1e6024c71f..509162cdce 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -591,7 +591,7 @@ static void validate_guest_pt_write(struct vcpu *v, mfn_t gmfn,
if ( rc & SHADOW_SET_FLUSH )
/* Need to flush TLBs to pick up shadow PT changes */
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
if ( rc & SHADOW_SET_ERROR )
{
diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c
index b6afc0fba4..667fca96c7 100644
--- a/xen/arch/x86/mm/shadow/multi.c
+++ b/xen/arch/x86/mm/shadow/multi.c
@@ -3066,7 +3066,7 @@ static int sh_page_fault(struct vcpu *v,
perfc_incr(shadow_rm_write_flush_tlb);
smp_wmb();
atomic_inc(&d->arch.paging.shadow.gtable_dirty_version);
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
}
#if (SHADOW_OPTIMIZATIONS & SHOPT_OUT_OF_SYNC)
@@ -3575,7 +3575,7 @@ static bool sh_invlpg(struct vcpu *v, unsigned long linear)
if ( mfn_to_page(sl1mfn)->u.sh.type
== SH_type_fl1_shadow )
{
- flush_tlb_local();
+ flush_local(FLUSH_TLB | FLUSH_HVM_ASID_CORE);
return false;
}
@@ -3810,7 +3810,7 @@ sh_update_linear_entries(struct vcpu *v)
* table entry. But, without this change, it would fetch the wrong
* value due to a stale TLB.
*/
- flush_tlb_local();
+ flush_local(FLUSH_TLB | FLUSH_HVM_ASID_CORE);
}
}
@@ -4011,7 +4011,7 @@ sh_update_cr3(struct vcpu *v, int do_locking, bool noflush)
* (old) shadow linear maps in the writeable mapping heuristics. */
#if GUEST_PAGING_LEVELS == 2
if ( sh_remove_write_access(d, gmfn, 2, 0) != 0 )
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
sh_set_toplevel_shadow(v, 0, gmfn, SH_type_l2_shadow);
#elif GUEST_PAGING_LEVELS == 3
/* PAE guests have four shadow_table entries, based on the
@@ -4035,7 +4035,7 @@ sh_update_cr3(struct vcpu *v, int do_locking, bool noflush)
}
}
if ( flush )
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
/* Now install the new shadows. */
for ( i = 0; i < 4; i++ )
{
@@ -4056,7 +4056,7 @@ sh_update_cr3(struct vcpu *v, int do_locking, bool noflush)
}
#elif GUEST_PAGING_LEVELS == 4
if ( sh_remove_write_access(d, gmfn, 4, 0) != 0 )
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
sh_set_toplevel_shadow(v, 0, gmfn, SH_type_l4_shadow);
if ( !shadow_mode_external(d) && !is_pv_32bit_domain(d) )
{
@@ -4502,7 +4502,7 @@ static void sh_pagetable_dying(paddr_t gpa)
}
}
if ( flush )
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
/* Remember that we've seen the guest use this interface, so we
* can rely on it using it in future, instead of guessing at
@@ -4539,7 +4539,7 @@ static void sh_pagetable_dying(paddr_t gpa)
mfn_to_page(gmfn)->pagetable_dying = true;
shadow_unhook_mappings(d, smfn, 1/* user pages only */);
/* Now flush the TLB: we removed toplevel mappings. */
- flush_tlb_mask(d->dirty_cpumask);
+ flush_mask(d->dirty_cpumask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
}
/* Remember that we've seen the guest use this interface, so we
diff --git a/xen/include/asm-x86/flushtlb.h b/xen/include/asm-x86/flushtlb.h
index 2cfe4e6e97..579dc56803 100644
--- a/xen/include/asm-x86/flushtlb.h
+++ b/xen/include/asm-x86/flushtlb.h
@@ -105,6 +105,12 @@ void switch_cr3_cr4(unsigned long cr3, unsigned long cr4);
#define FLUSH_VCPU_STATE 0x1000
/* Flush the per-cpu root page table */
#define FLUSH_ROOT_PGTBL 0x2000
+#if CONFIG_HVM
+ /* Flush all HVM guests linear TLB (using ASID/VPID) */
+#define FLUSH_HVM_ASID_CORE 0x4000
+#else
+#define FLUSH_HVM_ASID_CORE 0
+#endif
/* Flush local TLBs/caches. */
unsigned int flush_area_local(const void *va, unsigned int flags);
--
2.25.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Xen-devel] [PATCH v6 4/6] x86/tlb: introduce a flush guests TLB flag
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 4/6] x86/tlb: introduce a flush guests TLB flag Roger Pau Monne
@ 2020-03-06 9:28 ` Jan Beulich
0 siblings, 0 replies; 13+ messages in thread
From: Jan Beulich @ 2020-03-06 9:28 UTC (permalink / raw)
To: Roger Pau Monne
Cc: xen-devel, Tim Deegan, George Dunlap, Wei Liu, Andrew Cooper
On 03.03.2020 18:20, Roger Pau Monne wrote:
> Introduce a specific flag to request a HVM guest TLB flush, which is
> an ASID/VPID tickle that forces a guest linear to guest physical TLB
> flush for all HVM guests.
>
> This was previously unconditionally done in each pre_flush call, but
> that's not required: HVM guests not using shadow don't require linear
> TLB flushes as Xen doesn't modify the guest page tables in that case
> (ie: when using HAP). Note that shadow paging code already takes care
> of issuing the necessary flushes when the shadow page tables are
> modified.
>
> In order to keep the previous behavior modify all shadow code TLB
> flushes to also flush the guest linear to physical TLB, in order to
> keep the previous behavior. I haven't looked at each specific shadow
> code TLB flush in order to figure out whether it actually requires a
> guest TLB flush or not, so there might be room for improvement in that
> regard.
I'm still missing a discussion of the safety of the removal of the
tickle from the switch_cr3_cr4() path: I don't think it can be
excluded offhand that shadow code somewhere relies on this happening
as a side effect of write_ptbase().
Jan
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [Xen-devel] [PATCH v6 5/6] x86/tlb: allow disabling the TLB clock
2020-03-03 17:20 [Xen-devel] [PATCH v6 0/6] x86: improve assisted tlb flush and use it in guest mode Roger Pau Monne
` (3 preceding siblings ...)
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 4/6] x86/tlb: introduce a flush guests TLB flag Roger Pau Monne
@ 2020-03-03 17:20 ` Roger Pau Monne
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 6/6] x86/tlb: use Xen L0 assisted TLB flush when available Roger Pau Monne
5 siblings, 0 replies; 13+ messages in thread
From: Roger Pau Monne @ 2020-03-03 17:20 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Wei Liu, Jan Beulich, Roger Pau Monne
The TLB clock is helpful when running Xen on bare metal because when
doing a TLB flush each CPU is IPI'ed and can keep a timestamp of the
last flush.
This is not the case however when Xen is running virtualized, and the
underlying hypervisor provides mechanism to assist in performing TLB
flushes: Xen itself for example offers a HVMOP_flush_tlbs hypercall in
order to perform a TLB flush without having to IPI each CPU. When
using such mechanisms it's no longer possible to keep a timestamp of
the flushes on each CPU, as they are performed by the underlying
hypervisor.
Offer a boolean in order to signal Xen that the timestamped TLB
shouldn't be used. This avoids keeping the timestamps of the flushes,
and also forces NEED_FLUSH to always return true.
No functional change intended, as this change doesn't introduce any
user that disables the timestamped TLB.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
xen/arch/x86/flushtlb.c | 19 +++++++++++++------
xen/include/asm-x86/flushtlb.h | 17 ++++++++++++++++-
2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c
index c1305c7e6b..3a70b6327a 100644
--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -32,6 +32,9 @@
u32 tlbflush_clock = 1U;
DEFINE_PER_CPU(u32, tlbflush_time);
+/* Signals whether the TLB flush clock is in use. */
+bool __read_mostly tlb_clk_enabled = true;
+
/*
* pre_flush(): Increment the virtual TLB-flush clock. Returns new clock value.
*
@@ -82,12 +85,13 @@ static void post_flush(u32 t)
static void do_tlb_flush(void)
{
unsigned long flags, cr4;
- u32 t;
+ u32 t = 0;
/* This non-reentrant function is sometimes called in interrupt context. */
local_irq_save(flags);
- t = pre_flush();
+ if ( tlb_clk_enabled )
+ t = pre_flush();
if ( use_invpcid )
invpcid_flush_all();
@@ -99,7 +103,8 @@ static void do_tlb_flush(void)
else
write_cr3(read_cr3());
- post_flush(t);
+ if ( tlb_clk_enabled )
+ post_flush(t);
local_irq_restore(flags);
}
@@ -107,7 +112,7 @@ static void do_tlb_flush(void)
void switch_cr3_cr4(unsigned long cr3, unsigned long cr4)
{
unsigned long flags, old_cr4;
- u32 t;
+ u32 t = 0;
/* Throughout this function we make this assumption: */
ASSERT(!(cr4 & X86_CR4_PCIDE) || !(cr4 & X86_CR4_PGE));
@@ -115,7 +120,8 @@ void switch_cr3_cr4(unsigned long cr3, unsigned long cr4)
/* This non-reentrant function is sometimes called in interrupt context. */
local_irq_save(flags);
- t = pre_flush();
+ if ( tlb_clk_enabled )
+ t = pre_flush();
old_cr4 = read_cr4();
ASSERT(!(old_cr4 & X86_CR4_PCIDE) || !(old_cr4 & X86_CR4_PGE));
@@ -167,7 +173,8 @@ void switch_cr3_cr4(unsigned long cr3, unsigned long cr4)
if ( cr4 & X86_CR4_PCIDE )
invpcid_flush_all_nonglobals();
- post_flush(t);
+ if ( tlb_clk_enabled )
+ post_flush(t);
local_irq_restore(flags);
}
diff --git a/xen/include/asm-x86/flushtlb.h b/xen/include/asm-x86/flushtlb.h
index 579dc56803..724455ae0c 100644
--- a/xen/include/asm-x86/flushtlb.h
+++ b/xen/include/asm-x86/flushtlb.h
@@ -21,10 +21,21 @@ extern u32 tlbflush_clock;
/* Time at which each CPU's TLB was last flushed. */
DECLARE_PER_CPU(u32, tlbflush_time);
-#define tlbflush_current_time() tlbflush_clock
+/* TLB clock is in use. */
+extern bool tlb_clk_enabled;
+
+static inline uint32_t tlbflush_current_time(void)
+{
+ /* Returning 0 from tlbflush_current_time will always force a flush. */
+ return tlb_clk_enabled ? tlbflush_clock : 0;
+}
static inline void page_set_tlbflush_timestamp(struct page_info *page)
{
+ /* Avoid the write if the TLB clock is disabled. */
+ if ( !tlb_clk_enabled )
+ return;
+
/*
* Prevent storing a stale time stamp, which could happen if an update
* to tlbflush_clock plus a subsequent flush IPI happen between the
@@ -67,6 +78,10 @@ static inline void tlbflush_filter(cpumask_t *mask, uint32_t page_timestamp)
{
unsigned int cpu;
+ /* Short-circuit: there's no need to iterate if the clock is disabled. */
+ if ( !tlb_clk_enabled )
+ return;
+
for_each_cpu ( cpu, mask )
if ( !NEED_FLUSH(per_cpu(tlbflush_time, cpu), page_timestamp) )
__cpumask_clear_cpu(cpu, mask);
--
2.25.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [Xen-devel] [PATCH v6 6/6] x86/tlb: use Xen L0 assisted TLB flush when available
2020-03-03 17:20 [Xen-devel] [PATCH v6 0/6] x86: improve assisted tlb flush and use it in guest mode Roger Pau Monne
` (4 preceding siblings ...)
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 5/6] x86/tlb: allow disabling the TLB clock Roger Pau Monne
@ 2020-03-03 17:20 ` Roger Pau Monne
2020-03-06 9:32 ` Jan Beulich
5 siblings, 1 reply; 13+ messages in thread
From: Roger Pau Monne @ 2020-03-03 17:20 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Wei Liu, Jan Beulich, Roger Pau Monne
Use Xen's L0 HVMOP_flush_tlbs hypercall in order to perform flushes.
This greatly increases the performance of TLB flushes when running
with a high amount of vCPUs as a Xen guest, and is specially important
when running in shim mode.
The following figures are from a PV guest running `make -j32 xen` in
shim mode with 32 vCPUs and HAP.
Using x2APIC and ALLBUT shorthand:
real 4m35.973s
user 4m35.110s
sys 36m24.117s
Using L0 assisted flush:
real 1m2.596s
user 4m34.818s
sys 5m16.374s
The implementation adds a new hook to hypervisor_ops so other
enlightenments can also implement such assisted flush just by filling
the hook.
Note that the Xen implementation completely ignores the dirty CPU mask
and the linear address passed in, and always performs a global TLB
flush on all vCPUs. This is a limitation of the hypercall provided by
Xen. Also note that local TLB flushes are not performed using the
assisted TLB flush, only remote ones.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
---
Changes since v5:
- Clarify commit message.
- Test for assisted flush at setup, do this for all hypervisors.
- Return EOPNOTSUPP if assisted flush is not available.
Changes since v4:
- Adjust order calculation.
Changes since v3:
- Use an alternative call for the flush hook.
Changes since v1:
- Add a L0 assisted hook to hypervisor ops.
---
xen/arch/x86/guest/hypervisor.c | 14 ++++++++++++++
xen/arch/x86/guest/xen/xen.c | 6 ++++++
xen/arch/x86/smp.c | 7 +++++++
xen/include/asm-x86/guest/hypervisor.h | 17 +++++++++++++++++
4 files changed, 44 insertions(+)
diff --git a/xen/arch/x86/guest/hypervisor.c b/xen/arch/x86/guest/hypervisor.c
index 647cdb1367..e46de42ded 100644
--- a/xen/arch/x86/guest/hypervisor.c
+++ b/xen/arch/x86/guest/hypervisor.c
@@ -18,6 +18,7 @@
*
* Copyright (c) 2019 Microsoft.
*/
+#include <xen/cpumask.h>
#include <xen/init.h>
#include <xen/types.h>
@@ -51,6 +52,10 @@ void __init hypervisor_setup(void)
{
if ( ops.setup )
ops.setup();
+
+ /* Check if assisted flush is available and disable the TLB clock if so. */
+ if ( !hypervisor_flush_tlb(cpumask_of(smp_processor_id()), NULL, 0) )
+ tlb_clk_enabled = false;
}
int hypervisor_ap_setup(void)
@@ -73,6 +78,15 @@ void __init hypervisor_e820_fixup(struct e820map *e820)
ops.e820_fixup(e820);
}
+int hypervisor_flush_tlb(const cpumask_t *mask, const void *va,
+ unsigned int order)
+{
+ if ( ops.flush_tlb )
+ return alternative_call(ops.flush_tlb, mask, va, order);
+
+ return -EOPNOTSUPP;
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c
index e74fd1e995..3bc01c8723 100644
--- a/xen/arch/x86/guest/xen/xen.c
+++ b/xen/arch/x86/guest/xen/xen.c
@@ -324,12 +324,18 @@ static void __init e820_fixup(struct e820map *e820)
pv_shim_fixup_e820(e820);
}
+static int flush_tlb(const cpumask_t *mask, const void *va, unsigned int order)
+{
+ return xen_hypercall_hvm_op(HVMOP_flush_tlbs, NULL);
+}
+
static const struct hypervisor_ops __initconstrel ops = {
.name = "Xen",
.setup = setup,
.ap_setup = ap_setup,
.resume = resume,
.e820_fixup = e820_fixup,
+ .flush_tlb = flush_tlb,
};
const struct hypervisor_ops *__init xg_probe(void)
diff --git a/xen/arch/x86/smp.c b/xen/arch/x86/smp.c
index bcead5d01b..1d9fec65de 100644
--- a/xen/arch/x86/smp.c
+++ b/xen/arch/x86/smp.c
@@ -15,6 +15,7 @@
#include <xen/perfc.h>
#include <xen/spinlock.h>
#include <asm/current.h>
+#include <asm/guest.h>
#include <asm/smp.h>
#include <asm/mc146818rtc.h>
#include <asm/flushtlb.h>
@@ -268,6 +269,12 @@ void flush_area_mask(const cpumask_t *mask, const void *va, unsigned int flags)
if ( (flags & ~FLUSH_ORDER_MASK) &&
!cpumask_subset(mask, cpumask_of(cpu)) )
{
+ if ( cpu_has_hypervisor &&
+ !(flags & ~(FLUSH_TLB | FLUSH_TLB_GLOBAL | FLUSH_VA_VALID |
+ FLUSH_ORDER_MASK)) &&
+ !hypervisor_flush_tlb(mask, va, (flags - 1) & FLUSH_ORDER_MASK) )
+ return;
+
spin_lock(&flush_lock);
cpumask_and(&flush_cpumask, mask, &cpu_online_map);
cpumask_clear_cpu(cpu, &flush_cpumask);
diff --git a/xen/include/asm-x86/guest/hypervisor.h b/xen/include/asm-x86/guest/hypervisor.h
index ade10e74ea..77a1d21824 100644
--- a/xen/include/asm-x86/guest/hypervisor.h
+++ b/xen/include/asm-x86/guest/hypervisor.h
@@ -19,6 +19,8 @@
#ifndef __X86_HYPERVISOR_H__
#define __X86_HYPERVISOR_H__
+#include <xen/cpumask.h>
+
#include <asm/e820.h>
struct hypervisor_ops {
@@ -32,6 +34,8 @@ struct hypervisor_ops {
void (*resume)(void);
/* Fix up e820 map */
void (*e820_fixup)(struct e820map *e820);
+ /* L0 assisted TLB flush */
+ int (*flush_tlb)(const cpumask_t *mask, const void *va, unsigned int order);
};
#ifdef CONFIG_GUEST
@@ -41,6 +45,14 @@ void hypervisor_setup(void);
int hypervisor_ap_setup(void);
void hypervisor_resume(void);
void hypervisor_e820_fixup(struct e820map *e820);
+/*
+ * L0 assisted TLB flush.
+ * mask: cpumask of the dirty vCPUs that should be flushed.
+ * va: linear address to flush, or NULL for global flushes.
+ * order: order of the linear address pointed by va.
+ */
+int hypervisor_flush_tlb(const cpumask_t *mask, const void *va,
+ unsigned int order);
#else
@@ -52,6 +64,11 @@ static inline void hypervisor_setup(void) { ASSERT_UNREACHABLE(); }
static inline int hypervisor_ap_setup(void) { return 0; }
static inline void hypervisor_resume(void) { ASSERT_UNREACHABLE(); }
static inline void hypervisor_e820_fixup(struct e820map *e820) {}
+static inline int hypervisor_flush_tlb(const cpumask_t *mask, const void *va,
+ unsigned int order)
+{
+ return -EOPNOTSUPP;
+}
#endif /* CONFIG_GUEST */
--
2.25.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Xen-devel] [PATCH v6 6/6] x86/tlb: use Xen L0 assisted TLB flush when available
2020-03-03 17:20 ` [Xen-devel] [PATCH v6 6/6] x86/tlb: use Xen L0 assisted TLB flush when available Roger Pau Monne
@ 2020-03-06 9:32 ` Jan Beulich
2020-03-19 15:40 ` Roger Pau Monné
0 siblings, 1 reply; 13+ messages in thread
From: Jan Beulich @ 2020-03-06 9:32 UTC (permalink / raw)
To: Roger Pau Monne; +Cc: xen-devel, Wei Liu, Andrew Cooper
On 03.03.2020 18:20, Roger Pau Monne wrote:
> Use Xen's L0 HVMOP_flush_tlbs hypercall in order to perform flushes.
> This greatly increases the performance of TLB flushes when running
> with a high amount of vCPUs as a Xen guest, and is specially important
> when running in shim mode.
>
> The following figures are from a PV guest running `make -j32 xen` in
> shim mode with 32 vCPUs and HAP.
>
> Using x2APIC and ALLBUT shorthand:
> real 4m35.973s
> user 4m35.110s
> sys 36m24.117s
>
> Using L0 assisted flush:
> real 1m2.596s
> user 4m34.818s
> sys 5m16.374s
>
> The implementation adds a new hook to hypervisor_ops so other
> enlightenments can also implement such assisted flush just by filling
> the hook.
>
> Note that the Xen implementation completely ignores the dirty CPU mask
> and the linear address passed in, and always performs a global TLB
> flush on all vCPUs. This is a limitation of the hypercall provided by
> Xen. Also note that local TLB flushes are not performed using the
> assisted TLB flush, only remote ones.
As to this last sentence - isn't this wasteful at least when a
full address space flush is being processed anyway?
> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
> Reviewed-by: Wei Liu <wl@xen.org>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
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* Re: [Xen-devel] [PATCH v6 6/6] x86/tlb: use Xen L0 assisted TLB flush when available
2020-03-06 9:32 ` Jan Beulich
@ 2020-03-19 15:40 ` Roger Pau Monné
0 siblings, 0 replies; 13+ messages in thread
From: Roger Pau Monné @ 2020-03-19 15:40 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel, Wei Liu, Andrew Cooper
On Fri, Mar 06, 2020 at 10:32:55AM +0100, Jan Beulich wrote:
> On 03.03.2020 18:20, Roger Pau Monne wrote:
> > Use Xen's L0 HVMOP_flush_tlbs hypercall in order to perform flushes.
> > This greatly increases the performance of TLB flushes when running
> > with a high amount of vCPUs as a Xen guest, and is specially important
> > when running in shim mode.
> >
> > The following figures are from a PV guest running `make -j32 xen` in
> > shim mode with 32 vCPUs and HAP.
> >
> > Using x2APIC and ALLBUT shorthand:
> > real 4m35.973s
> > user 4m35.110s
> > sys 36m24.117s
> >
> > Using L0 assisted flush:
> > real 1m2.596s
> > user 4m34.818s
> > sys 5m16.374s
> >
> > The implementation adds a new hook to hypervisor_ops so other
> > enlightenments can also implement such assisted flush just by filling
> > the hook.
> >
> > Note that the Xen implementation completely ignores the dirty CPU mask
> > and the linear address passed in, and always performs a global TLB
> > flush on all vCPUs. This is a limitation of the hypercall provided by
> > Xen. Also note that local TLB flushes are not performed using the
> > assisted TLB flush, only remote ones.
>
> As to this last sentence - isn't this wasteful at least when a
> full address space flush is being processed anyway?
Likely yes, if there are global TLB flushes in parallel to local ones.
AFAICT the purpose of the timestamped TLB is to cope with some of
this, by recording the last TLB stamp and avoiding flushes requested
before that. Here we have to disable such timestamps, since the
flush is done on the back of the vCPU, and hence it's not possible to
accurately record it's timestamp.
From my data above the benefit of using the assisted TLB greatly
outweighs the fact that the timestamped TLB is disabled.
> > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
> > Reviewed-by: Wei Liu <wl@xen.org>
>
> Reviewed-by: Jan Beulich <jbeulich@suse.com>
Thanks, will resend this now.
Roger.
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