[PATCH 1/2] arm-bsp/trusted-firmware-a: update SHA for tc0

[PATCH 1/2] arm-bsp/trusted-firmware-a: update SHA for tc0

[Arunachalam Ganapathy]

This SHA contains fix for SVE and AMU extension

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iefa3e8f9bee41098ea49304d88dc04df74ddcb9c
---
 .../trusted-firmware-a/trusted-firmware-a-tc0.inc            | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc
index 53ff110..93a9b4d 100644
--- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc
+++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc
@@ -1,5 +1,10 @@
 # TC0 specific TFA configuration
 
+# Intermediate SHA with 2.5 baseline version
+SRCREV_tfa = "a52c52477aa797e6a261215e9b3536533590b334"
+PV = "2.5+git${SRCPV}"
+LIC_FILES_CHKSUM = "file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde"
+
 DEPENDS += "scp-firmware"
 
 COMPATIBLE_MACHINE = "tc0"
-- 
2.29.2

[PATCH 2/2] arm-bsp/tc0: add managed exit patch for optee

[Arunachalam Ganapathy]

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I2a8db6024af35bf95e94963b58011daebb3c666b
---
 .../tc0/0001-WIP-Enable-managed-exit.patch    | 123 ++++++++++++++++++
 .../recipes-security/optee/optee-os-tc0.inc   |   5 +-
 2 files changed, 127 insertions(+), 1 deletion(-)
 create mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/tc0/0001-WIP-Enable-managed-exit.patch

diff --git a/meta-arm-bsp/recipes-security/optee/files/optee-os/tc0/0001-WIP-Enable-managed-exit.patch b/meta-arm-bsp/recipes-security/optee/files/optee-os/tc0/0001-WIP-Enable-managed-exit.patch
new file mode 100644
index 0000000..c038299
--- /dev/null
+++ b/meta-arm-bsp/recipes-security/optee/files/optee-os/tc0/0001-WIP-Enable-managed-exit.patch
@@ -0,0 +1,123 @@
+From 14b84786e85483bf3c737ef8b392204e307c0ff1 Mon Sep 17 00:00:00 2001
+From: Olivier Deprez <olivier.deprez@arm.com>
+Date: Mon, 16 Nov 2020 10:14:02 +0100
+Subject: [PATCH] WIP: Enable managed exit
+
+This change declares OP-TEE SP as supporting managed exit in response to
+a NS interrupt triggering while the SWd runs.
+
+At init OP-TEE enables (HF_INTERRUPT_ENABLE) the managed exit virtual
+interrupt through the Hafnium para-virtualized interface.
+
+Physical interrupts are trapped to the SPMC which injects a managed exit
+interrupt to OP-TEE. The managed exit interrupt is acknowledged by
+OP-TEE by HF_INTERUPT_GET hvc call.
+
+Note: this code change is meant with in mind the SPMC runs at SEL2. It
+needs slight refactoring such that it does not break the SEL1 SPMC
+configuration.
+
+Change-Id: I9a95f36cf517c11048ff04680007f40259c4f636
+Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+---
+ core/arch/arm/kernel/boot.c                          | 12 ++++++++++++
+ core/arch/arm/kernel/thread_a64.S                    | 11 ++++++++++-
+ core/arch/arm/kernel/thread_spmc.c                   | 11 +++++++++++
+ .../arm/plat-totalcompute/fdts/optee_sp_manifest.dts |  2 +-
+ 4 files changed, 34 insertions(+), 2 deletions(-)
+
+diff --git a/core/arch/arm/kernel/boot.c b/core/arch/arm/kernel/boot.c
+index 09c1b811..d130107f 100644
+--- a/core/arch/arm/kernel/boot.c
++++ b/core/arch/arm/kernel/boot.c
+@@ -1279,6 +1279,18 @@ static void init_secondary_helper(unsigned long nsec_entry)
+ 	init_vfp_sec();
+ 	init_vfp_nsec();
+ 
++	/* Enable managed exit interrupt for secondary core. */
++	__asm__ volatile (
++		"mov x0, %0;"
++		"mov x1, %1;"
++		"mov x2, %2;"
++		"mov x3, %3;"
++		"hvc #0"
++		: : "i" (0xff03), "i" (4), "i" (1), "i" (1));
++
++	IMSG("%s core %lu: enabled managed exit interrupt.",
++		__func__, get_core_pos());
++
+ 	IMSG("Secondary CPU %zu switching to normal world boot", get_core_pos());
+ }
+ 
+diff --git a/core/arch/arm/kernel/thread_a64.S b/core/arch/arm/kernel/thread_a64.S
+index 3e0f5115..63bf396a 100644
+--- a/core/arch/arm/kernel/thread_a64.S
++++ b/core/arch/arm/kernel/thread_a64.S
+@@ -904,6 +904,14 @@ END_FUNC el0_sync_abort
+ 	bl	dcache_op_louis
+ 	ic	iallu
+ #endif
++
++	/* HF_INTERRUPT_GET */
++	mov	x0, #0xff04
++	hvc	#0
++	/* Expect managed exit interrupt */
++	cmp	x0, #4
++	bne	.
++
+ 	/*
+ 	 * Mark current thread as suspended
+ 	 */
+@@ -1021,8 +1029,9 @@ LOCAL_FUNC elx_irq , :
+ #endif
+ END_FUNC elx_irq
+ 
++#define HF_MANAGED_EXIT		1
+ LOCAL_FUNC elx_fiq , :
+-#if defined(CFG_ARM_GICV3)
++#if defined(CFG_ARM_GICV3) || defined (HF_MANAGED_EXIT)
+ 	foreign_intr_handler	fiq
+ #else
+ 	native_intr_handler	fiq
+diff --git a/core/arch/arm/kernel/thread_spmc.c b/core/arch/arm/kernel/thread_spmc.c
+index bd7930e7..89ff82bc 100644
+--- a/core/arch/arm/kernel/thread_spmc.c
++++ b/core/arch/arm/kernel/thread_spmc.c
+@@ -1394,6 +1394,17 @@ static TEE_Result spmc_init(void)
+ 	my_endpoint_id = spmc_get_id();
+ 	DMSG("My endpoint ID %#x", my_endpoint_id);
+ 
++	/* Enable managed exit interrupt for boot core. */
++	__asm__ volatile (
++		"mov x0, %0;"
++		"mov x1, %1;"
++		"mov x2, %2;"
++		"mov x3, %3;"
++		"hvc #0"
++		: : "i" (0xff03), "i" (4), "i" (1), "i" (1));
++
++	IMSG("%s enabled managed exit interrupt.", __func__);
++
+ 	return TEE_SUCCESS;
+ }
+ #endif /*CFG_CORE_SEL2_SPMC*/
+diff --git a/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts b/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts
+index 4b8b3681..04847c4d 100644
+--- a/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts
++++ b/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts
+@@ -23,7 +23,7 @@
+ 	entrypoint-offset = <0x1000>;
+ 	xlat-granule = <0>; /* 4KiB */
+ 	boot-order = <0>;
+-	messaging-method = <0>; /* Direct messaging only */
++	messaging-method = <3>; /* Direct messaging and managed exit supported */
+ 
+ 	device-regions {
+ 		compatible = "arm,ffa-manifest-device-regions";
+-- 
+2.29.2
+
diff --git a/meta-arm-bsp/recipes-security/optee/optee-os-tc0.inc b/meta-arm-bsp/recipes-security/optee/optee-os-tc0.inc
index 7afc112..c48cc6c 100644
--- a/meta-arm-bsp/recipes-security/optee/optee-os-tc0.inc
+++ b/meta-arm-bsp/recipes-security/optee/optee-os-tc0.inc
@@ -6,7 +6,10 @@ SRCREV = "49dbb9ef65643c4322cf3f848910fa880d1c02f6"
 PV = "3.14.0+git${SRCPV}"
 
 FILESEXTRAPATHS_prepend_tc0 := "${THISDIR}/files/optee-os/tc0:"
-SRC_URI_append = "file://sp_layout.json"
+SRC_URI_append = " \
+    file://sp_layout.json \
+    file://0001-WIP-Enable-managed-exit.patch \
+    "
 
 COMPATIBLE_MACHINE = "tc0"
 
-- 
2.29.2

[PATCH 1/2] arm-bsp/trusted-firmware-a: Update SHA for tc0

[Usama Arif]

This SHA of trusted-firmware-a includes support for
additional features for tc0 including TZC and cpuidle.

Change-Id: I004f9614b2bada9b88d2fce90f0f10064d8437e4
Signed-off-by: Usama Arif <usama.arif@arm.com>
---
 .../recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc
index e2f41f1..9af04e8 100644
--- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc
+++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc
@@ -1,7 +1,7 @@
 # TCO specific TFA configuration
 
 # Intermediate SHA with 2.3 baseline version
-SRCREV_tfa = "2fe7d18b0d99fdf4c4dbf84863bb2036dfebc537"
+SRCREV_tfa = "16796a25fefc4ecf780211bf554d3b8dc5436fa4"
 
 DEPENDS += "scp-firmware"
 
-- 
2.17.1