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From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors
Date: Sat, 16 Mar 2019 01:20:02 +0000	[thread overview]
Message-ID: <07d2c6f05d4092419de488237910e7f9f85dcd4f.1552699115.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1552699115.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 15a5366616..b11c4ae22f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -113,10 +113,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
             env->pmp_state.pmp[pmp_index].cfg_reg = val;
             pmp_update_rule(env, pmp_index);
         } else {
-            PMP_DEBUG("ignoring write - locked");
+            qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
         }
     } else {
-        PMP_DEBUG("ignoring write - out of bounds");
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "ignoring pmpcfg write - out of bounds\n");
     }
 }
 
@@ -249,7 +250,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 
         /* partially inside */
         if ((s + e) == 1) {
-            PMP_DEBUG("pmp violation - access is partially inside");
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "pmp violation - access is partially inside\n");
             ret = 0;
             break;
         }
@@ -306,7 +308,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         env->mhartid, reg_index, val);
 
     if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
-        PMP_DEBUG("ignoring write - incorrect address");
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "ignoring pmpcfg write - incorrect address\n");
         return;
     }
 
@@ -353,10 +356,12 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
             env->pmp_state.pmp[addr_index].addr_reg = val;
             pmp_update_rule(env, addr_index);
         } else {
-            PMP_DEBUG("ignoring write - locked");
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "ignoring pmpaddr write - locked\n");
         }
     } else {
-        PMP_DEBUG("ignoring write - out of bounds");
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "ignoring pmpaddr write - out of bounds\n");
     }
 }
 
@@ -372,7 +377,8 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
     if (addr_index < MAX_RISCV_PMPS) {
         return env->pmp_state.pmp[addr_index].addr_reg;
     } else {
-        PMP_DEBUG("ignoring read - out of bounds");
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "ignoring pmpaddr read - out of bounds\n");
         return 0;
     }
 }
-- 
2.21.0



  reply	other threads:[~2019-03-16  1:27 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-16  1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-16  1:20 ` Alistair Francis [this message]
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct Alistair Francis
2019-03-16  1:22 ` [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-19  0:33   ` Alistair Francis
2019-03-19  3:41     ` Palmer Dabbelt
2019-03-19 17:14       ` Alistair Francis

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