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From: Alistair Francis <alistair23@gmail.com>
To: "palmer@sifive.com" <palmer@sifive.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	 Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
Date: Mon, 18 Mar 2019 17:33:38 -0700	[thread overview]
Message-ID: <CAKmqyKNOsaUEBTQsqt68201oNyQxpry9x8+D-o_fijcy=VKAjg@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKNLrSZPVmSx9pz9Khfz0wKMsOmTkKN7L5rcVkSQcaW9jQ@mail.gmail.com>

On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
> <Alistair.Francis@wdc.com> wrote:
> >
> > v3:
> >  - Add a patch to remove some dead code
> >  - Rebase on master
> > v2:
> >  - Add a patch for SiFive U SMP support
> >  - Rebase on master
> >
> > Alistair Francis (3):
> >   riscv: pmp: Log pmp access errors as guest errors
> >   riscv: sifive_u: Allow up to 4 CPUs to be created
> >   target/riscv: Remove unused struct
> >
> > Kito Cheng (1):
> >   RISC-V: linux-user support for RVE ABI
> >
> > Michael Clark (8):
> >   RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
> >   RISC-V: Allow interrupt controllers to claim interrupts
> >   RISC-V: Remove unnecessary disassembler constraints
> >   elf: Add RISC-V PSABI ELF header defines
> >   RISC-V: Change local interrupts from edge to level
> >   RISC-V: Add support for vectored interrupts
> >   RISC-V: Convert trap debugging to trace events
> >   RISC-V: Update load reservation comment in do_interrupt

@Palmer

Any chance this can go in for 4.0? It's just bug fixes that have been
on list for a while. Without this series u-boot SMP won't work in
QEMU, see here:
https://lists.denx.de/pipermail/u-boot/2019-March/360899.html

Alistair

>
> Sorry, this series should be v3 in the title. I won't resend it, just pretend :)
>
> Alistair
>
> >
> >  Makefile.objs               |   1 +
> >  disas/riscv.c               | 138 -----------------------------
> >  hw/riscv/sifive_plic.c      |  19 +++-
> >  hw/riscv/sifive_u.c         |   5 +-
> >  include/elf.h               |  10 +++
> >  linux-user/riscv/cpu_loop.c |  15 +++-
> >  target/riscv/cpu.c          |   6 --
> >  target/riscv/cpu.h          |   6 ++
> >  target/riscv/cpu_helper.c   | 168 +++++++++++++++---------------------
> >  target/riscv/cpu_user.h     |   3 +-
> >  target/riscv/csr.c          |  22 ++---
> >  target/riscv/pmp.c          |  20 +++--
> >  target/riscv/trace-events   |   2 +
> >  13 files changed, 148 insertions(+), 267 deletions(-)
> >  create mode 100644 target/riscv/trace-events
> >
> > --
> > 2.21.0
> >


  reply	other threads:[~2019-03-19  0:35 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-16  1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI Alistair Francis
2019-03-16  1:20 ` [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created Alistair Francis
2019-03-16  1:21 ` [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct Alistair Francis
2019-03-16  1:22 ` [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-19  0:33   ` Alistair Francis [this message]
2019-03-19  3:41     ` Palmer Dabbelt
2019-03-19 17:14       ` Alistair Francis

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