From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct
Date: Sat, 16 Mar 2019 01:21:39 +0000 [thread overview]
Message-ID: <0a131426e4b8d02a2923df22379df81c8314c714.1552699115.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1552699115.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc3ddc0ae4..568c4cd637 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -80,12 +80,6 @@ const char * const riscv_intr_names[] = {
"reserved"
};
-typedef struct RISCVCPUInfo {
- const int bit_widths;
- const char *name;
- void (*initfn)(Object *obj);
-} RISCVCPUInfo;
-
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
--
2.21.0
next prev parent reply other threads:[~2019-03-16 1:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created Alistair Francis
2019-03-16 1:21 ` Alistair Francis [this message]
2019-03-16 1:22 ` [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-19 0:33 ` Alistair Francis
2019-03-19 3:41 ` Palmer Dabbelt
2019-03-19 17:14 ` Alistair Francis
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