From: Catalin Marinas <catalin.marinas@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 12/20] ARM: LPAE: Add context switching support Date: Fri, 12 Nov 2010 18:00:32 +0000 [thread overview] Message-ID: <1289584840-18097-13-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1289584840-18097-1-git-send-email-catalin.marinas@arm.com> With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm/mm/context.c | 18 ++++++++++++++++-- arch/arm/mm/proc-v7.S | 8 +++++++- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index b0ee9ba..d40d3fa 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -22,6 +22,20 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION; DEFINE_PER_CPU(struct mm_struct *, current_mm); #endif +#ifdef CONFIG_ARM_LPAE +#define cpu_set_asid(asid) { \ + unsigned long ttbl, ttbh; \ + asm(" mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ + " mov %1, %1, lsl #(48 - 32) @ set ASID\n" \ + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ + : "=r" (ttbl), "=r" (ttbh) \ + : "r" (asid & ~ASID_MASK)); \ +} +#else +#define cpu_set_asid(asid) \ + asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +#endif + /* * We fork()ed a process, and we need a new context for the child * to run in. We reserve version 0 for initial tasks so we will @@ -37,7 +51,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { /* set the reserved ASID before flushing the TLB */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); + cpu_set_asid(0); isb(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { @@ -99,7 +113,7 @@ static void reset_context(void *info) set_mm_context(mm, asid); /* set the new ASID */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id)); + cpu_set_asid(mm->context.id); isb(); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 33a8c82..b0932c1 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -117,6 +117,11 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id +#ifdef CONFIG_ARM_LPAE + and r3, r1, #0xff + mov r3, r3, lsl #(48 - 32) @ ASID + mcrr p15, 0, r0, r3, c2 @ set TTB 0 +#else /* !CONFIG_ARM_LPAE */ ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 @@ -124,9 +129,10 @@ ENTRY(cpu_v7_switch_mm) #endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb -1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 isb mcr p15, 0, r1, c13, c0, 1 @ set context ID +#endif /* CONFIG_ARM_LPAE */ isb #endif mov pc, lr
WARNING: multiple messages have this Message-ID (diff)
From: catalin.marinas@arm.com (Catalin Marinas) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 12/20] ARM: LPAE: Add context switching support Date: Fri, 12 Nov 2010 18:00:32 +0000 [thread overview] Message-ID: <1289584840-18097-13-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1289584840-18097-1-git-send-email-catalin.marinas@arm.com> With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm/mm/context.c | 18 ++++++++++++++++-- arch/arm/mm/proc-v7.S | 8 +++++++- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index b0ee9ba..d40d3fa 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -22,6 +22,20 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION; DEFINE_PER_CPU(struct mm_struct *, current_mm); #endif +#ifdef CONFIG_ARM_LPAE +#define cpu_set_asid(asid) { \ + unsigned long ttbl, ttbh; \ + asm(" mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ + " mov %1, %1, lsl #(48 - 32) @ set ASID\n" \ + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ + : "=r" (ttbl), "=r" (ttbh) \ + : "r" (asid & ~ASID_MASK)); \ +} +#else +#define cpu_set_asid(asid) \ + asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +#endif + /* * We fork()ed a process, and we need a new context for the child * to run in. We reserve version 0 for initial tasks so we will @@ -37,7 +51,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { /* set the reserved ASID before flushing the TLB */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); + cpu_set_asid(0); isb(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { @@ -99,7 +113,7 @@ static void reset_context(void *info) set_mm_context(mm, asid); /* set the new ASID */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id)); + cpu_set_asid(mm->context.id); isb(); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 33a8c82..b0932c1 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -117,6 +117,11 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id +#ifdef CONFIG_ARM_LPAE + and r3, r1, #0xff + mov r3, r3, lsl #(48 - 32) @ ASID + mcrr p15, 0, r0, r3, c2 @ set TTB 0 +#else /* !CONFIG_ARM_LPAE */ ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 @@ -124,9 +129,10 @@ ENTRY(cpu_v7_switch_mm) #endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb -1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 isb mcr p15, 0, r1, c13, c0, 1 @ set context ID +#endif /* CONFIG_ARM_LPAE */ isb #endif mov pc, lr
next prev parent reply other threads:[~2010-11-12 18:01 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2010-11-12 18:00 [PATCH v2 00/20] ARM: Add support for the Large Physical Address Extensions Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 01/20] ARM: LPAE: Use PMD_(SHIFT|SIZE|MASK) instead of PGDIR_* Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-22 12:43 ` Russell King - ARM Linux 2010-11-22 12:43 ` Russell King - ARM Linux 2010-11-22 13:00 ` Catalin Marinas 2010-11-22 13:00 ` Catalin Marinas 2010-11-22 13:28 ` Russell King - ARM Linux 2010-11-22 13:28 ` Russell King - ARM Linux 2010-11-12 18:00 ` [PATCH v2 02/20] ARM: LPAE: Factor out 2-level page table definitions into separate files Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-15 23:31 ` Russell King - ARM Linux 2010-11-15 23:31 ` Russell King - ARM Linux 2010-11-16 9:14 ` Catalin Marinas 2010-11-16 9:14 ` Catalin Marinas 2010-11-16 9:59 ` Russell King - ARM Linux 2010-11-16 9:59 ` Russell King - ARM Linux 2010-11-16 10:02 ` Catalin Marinas 2010-11-16 10:02 ` Catalin Marinas 2010-11-16 10:04 ` Russell King - ARM Linux 2010-11-16 10:04 ` Russell King - ARM Linux 2010-11-16 10:11 ` Catalin Marinas 2010-11-16 10:11 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 03/20] ARM: LPAE: use u32 instead of unsigned long for 32-bit ptes Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-14 13:19 ` Russell King - ARM Linux 2010-11-14 13:19 ` Russell King - ARM Linux 2010-11-14 14:09 ` Catalin Marinas 2010-11-14 14:09 ` Catalin Marinas 2010-11-14 14:13 ` Catalin Marinas 2010-11-14 14:13 ` Catalin Marinas 2010-11-14 15:14 ` Russell King - ARM Linux 2010-11-14 15:14 ` Russell King - ARM Linux 2010-11-15 9:39 ` Catalin Marinas 2010-11-15 9:39 ` Catalin Marinas 2010-11-15 9:47 ` Arnd Bergmann 2010-11-15 9:47 ` Arnd Bergmann 2010-11-15 9:51 ` Catalin Marinas 2010-11-15 9:51 ` Catalin Marinas 2010-11-15 22:11 ` Nicolas Pitre 2010-11-15 22:11 ` Nicolas Pitre 2010-11-15 23:35 ` Russell King - ARM Linux 2010-11-15 23:35 ` Russell King - ARM Linux 2010-11-16 9:19 ` Catalin Marinas 2010-11-16 9:19 ` Catalin Marinas 2010-11-15 22:07 ` Nicolas Pitre 2010-11-15 22:07 ` Nicolas Pitre 2010-11-15 17:36 ` Russell King - ARM Linux 2010-11-15 17:36 ` Russell King - ARM Linux 2010-11-15 17:39 ` Catalin Marinas 2010-11-15 17:39 ` Catalin Marinas 2010-11-16 19:34 ` Catalin Marinas 2010-11-16 19:34 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 04/20] ARM: LPAE: Do not assume Linux PTEs are always at PTRS_PER_PTE offset Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-15 17:42 ` Russell King - ARM Linux 2010-11-15 17:42 ` Russell King - ARM Linux 2010-11-15 21:46 ` Catalin Marinas 2010-11-15 21:46 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 05/20] ARM: LPAE: Introduce L_PTE_NOEXEC and L_PTE_NOWRITE Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-15 18:30 ` Russell King - ARM Linux 2010-11-15 18:30 ` Russell King - ARM Linux 2010-11-16 10:07 ` Catalin Marinas 2010-11-16 10:07 ` Catalin Marinas 2010-11-16 15:18 ` Catalin Marinas 2010-11-16 15:18 ` Catalin Marinas 2010-11-16 15:32 ` Catalin Marinas 2010-11-16 15:32 ` Catalin Marinas 2010-11-16 18:19 ` Russell King - ARM Linux 2010-11-16 18:19 ` Russell King - ARM Linux 2010-11-17 17:02 ` Catalin Marinas 2010-11-17 17:02 ` Catalin Marinas 2010-11-17 17:16 ` Russell King - ARM Linux 2010-11-17 17:16 ` Russell King - ARM Linux 2010-11-17 17:22 ` Catalin Marinas 2010-11-17 17:22 ` Catalin Marinas 2010-11-17 17:24 ` Russell King - ARM Linux 2010-11-17 17:24 ` Russell King - ARM Linux 2010-11-17 17:30 ` Catalin Marinas 2010-11-17 17:30 ` Catalin Marinas 2010-11-17 17:32 ` Russell King - ARM Linux 2010-11-17 17:32 ` Russell King - ARM Linux 2010-11-17 17:34 ` Catalin Marinas 2010-11-17 17:34 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 06/20] ARM: LPAE: Introduce the 3-level page table format definitions Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-15 18:34 ` Russell King - ARM Linux 2010-11-15 18:34 ` Russell King - ARM Linux 2010-11-16 9:57 ` Catalin Marinas 2010-11-16 9:57 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 07/20] ARM: LPAE: Page table maintenance for the 3-level format Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-22 12:58 ` Russell King - ARM Linux 2010-11-22 12:58 ` Russell King - ARM Linux 2010-11-12 18:00 ` [PATCH v2 08/20] ARM: LPAE: MMU setup for the 3-level page table format Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-14 10:13 ` Catalin Marinas 2010-11-14 10:13 ` Catalin Marinas 2010-11-22 13:10 ` Russell King - ARM Linux 2010-11-22 13:10 ` Russell King - ARM Linux 2010-11-23 11:38 ` Catalin Marinas 2010-11-23 11:38 ` Catalin Marinas 2010-11-23 17:33 ` Russell King - ARM Linux 2010-11-23 17:33 ` Russell King - ARM Linux 2010-11-23 17:35 ` Catalin Marinas 2010-11-23 17:35 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 09/20] ARM: LPAE: Change setup_mm_for_reboot() to work with LPAE Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-22 13:11 ` Russell King - ARM Linux 2010-11-22 13:11 ` Russell King - ARM Linux 2010-11-12 18:00 ` [PATCH v2 10/20] ARM: LPAE: Remove the FIRST_USER_PGD_NR and USER_PTRS_PER_PGD definitions Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-22 13:11 ` Russell King - ARM Linux 2010-11-22 13:11 ` Russell King - ARM Linux 2010-11-12 18:00 ` [PATCH v2 11/20] ARM: LPAE: Add fault handling support Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-22 13:15 ` Russell King - ARM Linux 2010-11-22 13:15 ` Russell King - ARM Linux 2010-11-22 13:19 ` Catalin Marinas 2010-11-22 13:19 ` Catalin Marinas 2010-11-22 13:32 ` Russell King - ARM Linux 2010-11-22 13:32 ` Russell King - ARM Linux 2010-11-22 13:38 ` Catalin Marinas 2010-11-22 13:38 ` Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas [this message] 2010-11-12 18:00 ` [PATCH v2 12/20] ARM: LPAE: Add context switching support Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 13/20] ARM: LPAE: Add SMP support for the 3-level page table format Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-22 13:37 ` Russell King - ARM Linux 2010-11-22 13:37 ` Russell King - ARM Linux 2010-11-12 18:00 ` [PATCH v2 14/20] ARM: LPAE: use phys_addr_t instead of unsigned long for physical addresses Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 15/20] ARM: LPAE: Use generic dma_addr_t type definition Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 16/20] ARM: LPAE: mark memory banks with start > ULONG_MAX as highmem Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 17/20] ARM: LPAE: use phys_addr_t for physical start address in early_mem Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 18/20] ARM: LPAE: add support for ATAG_MEM64 Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 19/20] ARM: LPAE: define printk format for physical addresses and page table entries Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-22 13:43 ` Russell King - ARM Linux 2010-11-22 13:43 ` Russell King - ARM Linux 2010-11-22 13:49 ` Catalin Marinas 2010-11-22 13:49 ` Catalin Marinas 2010-11-12 18:00 ` [PATCH v2 20/20] ARM: LPAE: Add the Kconfig entries Catalin Marinas 2010-11-12 18:00 ` Catalin Marinas 2010-11-13 12:38 ` Sergei Shtylyov 2010-11-13 12:38 ` Sergei Shtylyov 2010-11-14 10:11 ` Catalin Marinas 2010-11-14 10:11 ` Catalin Marinas
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