* [PATCH v1 1/4] x86, CPU: Fixup tlb_flushall_shift formatting
2012-08-06 17:00 [PATCH v1 0/4] x86, CPU: TLB flushall shift, the AMD side Borislav Petkov
@ 2012-08-06 17:00 ` Borislav Petkov
2012-08-07 3:07 ` [tip:x86/mm] x86, cpu: " tip-bot for Borislav Petkov
2012-08-06 17:00 ` [PATCH v1 2/4] x86, CPU: Push TLB detection CPUID check down Borislav Petkov
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Borislav Petkov @ 2012-08-06 17:00 UTC (permalink / raw)
To: H. Peter Anvin; +Cc: Alex Shi, X86-ML, LKML, Borislav Petkov
From: Borislav Petkov <borislav.petkov@amd.com>
The TLB characteristics appeared like this in dmesg:
[ 0.065817] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512
[ 0.065817] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 512
[ 0.065817] tlb_flushall_shift is 0xffffffff
where tlb_flushall_shift is actually -1 but dumped as a hex number.
However, the Kconfig option CONFIG_DEBUG_TLBFLUSH and the rest of the
code treats this as a signed decimal and states "If you set it to -1,
the code flushes the whole TLB unconditionally."
So, fix its formatting in accordance with the other references to it.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Alex Shi <alex.shi@intel.com>
---
arch/x86/kernel/cpu/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 46d8786d655e..d239977f361f 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -474,7 +474,7 @@ void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c)
printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
- "tlb_flushall_shift is 0x%x\n",
+ "tlb_flushall_shift: %d\n",
tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
--
1.7.11.rc1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [tip:x86/mm] x86, cpu: Fixup tlb_flushall_shift formatting
2012-08-06 17:00 ` [PATCH v1 1/4] x86, CPU: Fixup tlb_flushall_shift formatting Borislav Petkov
@ 2012-08-07 3:07 ` tip-bot for Borislav Petkov
0 siblings, 0 replies; 10+ messages in thread
From: tip-bot for Borislav Petkov @ 2012-08-07 3:07 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, alex.shi, tglx, borislav.petkov
Commit-ID: a9ad773e0dd833651f0831020a0ea0265c29f2ea
Gitweb: http://git.kernel.org/tip/a9ad773e0dd833651f0831020a0ea0265c29f2ea
Author: Borislav Petkov <borislav.petkov@amd.com>
AuthorDate: Mon, 6 Aug 2012 19:00:36 +0200
Committer: H. Peter Anvin <hpa@zytor.com>
CommitDate: Mon, 6 Aug 2012 19:18:09 -0700
x86, cpu: Fixup tlb_flushall_shift formatting
The TLB characteristics appeared like this in dmesg:
[ 0.065817] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512
[ 0.065817] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 512
[ 0.065817] tlb_flushall_shift is 0xffffffff
where tlb_flushall_shift is actually -1 but dumped as a hex number.
However, the Kconfig option CONFIG_DEBUG_TLBFLUSH and the rest of the
code treats this as a signed decimal and states "If you set it to -1,
the code flushes the whole TLB unconditionally."
So, fix its formatting in accordance with the other references to it.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Link: http://lkml.kernel.org/r/1344272439-29080-2-git-send-email-bp@amd64.org
Acked-by: Alex Shi <alex.shi@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/kernel/cpu/common.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 46d8786..d239977 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -474,7 +474,7 @@ void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c)
printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
- "tlb_flushall_shift is 0x%x\n",
+ "tlb_flushall_shift: %d\n",
tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1 2/4] x86, CPU: Push TLB detection CPUID check down
2012-08-06 17:00 [PATCH v1 0/4] x86, CPU: TLB flushall shift, the AMD side Borislav Petkov
2012-08-06 17:00 ` [PATCH v1 1/4] x86, CPU: Fixup tlb_flushall_shift formatting Borislav Petkov
@ 2012-08-06 17:00 ` Borislav Petkov
2012-08-07 0:35 ` Alex Shi
2012-08-07 3:08 ` [tip:x86/mm] x86, cpu: " tip-bot for Borislav Petkov
2012-08-06 17:00 ` [PATCH v1 3/4] x86, CPU: Add AMD TLB size detection Borislav Petkov
2012-08-06 17:00 ` [PATCH v1 4/4] x86, CPU: Preset default tlb_flushall_shift on AMD Borislav Petkov
3 siblings, 2 replies; 10+ messages in thread
From: Borislav Petkov @ 2012-08-06 17:00 UTC (permalink / raw)
To: H. Peter Anvin; +Cc: Alex Shi, X86-ML, LKML, Borislav Petkov
From: Borislav Petkov <borislav.petkov@amd.com>
Push the max CPUID leaf check into the ->detect_tlb function and remove
general test case from the generic path.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
arch/x86/kernel/cpu/common.c | 3 +--
arch/x86/kernel/cpu/intel.c | 4 ++++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d239977f361f..080f4a737e3e 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -940,8 +940,7 @@ void __init identify_boot_cpu(void)
#else
vgetcpu_set_mode();
#endif
- if (boot_cpu_data.cpuid_level >= 2)
- cpu_detect_tlb(&boot_cpu_data);
+ cpu_detect_tlb(&boot_cpu_data);
}
void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 0a4ce2980a5a..198e019a531a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -648,6 +648,10 @@ static void __cpuinit intel_detect_tlb(struct cpuinfo_x86 *c)
int i, j, n;
unsigned int regs[4];
unsigned char *desc = (unsigned char *)regs;
+
+ if (c->cpuid_level < 2)
+ return;
+
/* Number of times to iterate */
n = cpuid_eax(2) & 0xFF;
--
1.7.11.rc1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/4] x86, CPU: Push TLB detection CPUID check down
2012-08-06 17:00 ` [PATCH v1 2/4] x86, CPU: Push TLB detection CPUID check down Borislav Petkov
@ 2012-08-07 0:35 ` Alex Shi
2012-08-07 3:08 ` [tip:x86/mm] x86, cpu: " tip-bot for Borislav Petkov
1 sibling, 0 replies; 10+ messages in thread
From: Alex Shi @ 2012-08-07 0:35 UTC (permalink / raw)
To: Borislav Petkov; +Cc: H. Peter Anvin, X86-ML, LKML, Borislav Petkov
On 08/07/2012 01:00 AM, Borislav Petkov wrote:
> From: Borislav Petkov <borislav.petkov@amd.com>
>
> Push the max CPUID leaf check into the ->detect_tlb function and remove
> general test case from the generic path.
>
> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Alex Shi <alex.shi@intel.com>
> ---
> arch/x86/kernel/cpu/common.c | 3 +--
> arch/x86/kernel/cpu/intel.c | 4 ++++
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index d239977f361f..080f4a737e3e 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -940,8 +940,7 @@ void __init identify_boot_cpu(void)
> #else
> vgetcpu_set_mode();
> #endif
> - if (boot_cpu_data.cpuid_level >= 2)
> - cpu_detect_tlb(&boot_cpu_data);
> + cpu_detect_tlb(&boot_cpu_data);
> }
>
> void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 0a4ce2980a5a..198e019a531a 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -648,6 +648,10 @@ static void __cpuinit intel_detect_tlb(struct cpuinfo_x86 *c)
> int i, j, n;
> unsigned int regs[4];
> unsigned char *desc = (unsigned char *)regs;
> +
> + if (c->cpuid_level < 2)
> + return;
> +
> /* Number of times to iterate */
> n = cpuid_eax(2) & 0xFF;
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [tip:x86/mm] x86, cpu: Push TLB detection CPUID check down
2012-08-06 17:00 ` [PATCH v1 2/4] x86, CPU: Push TLB detection CPUID check down Borislav Petkov
2012-08-07 0:35 ` Alex Shi
@ 2012-08-07 3:08 ` tip-bot for Borislav Petkov
1 sibling, 0 replies; 10+ messages in thread
From: tip-bot for Borislav Petkov @ 2012-08-07 3:08 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, alex.shi, tglx, borislav.petkov
Commit-ID: 5b556332c3ab19e6375836d35ca658776e9ba0f6
Gitweb: http://git.kernel.org/tip/5b556332c3ab19e6375836d35ca658776e9ba0f6
Author: Borislav Petkov <borislav.petkov@amd.com>
AuthorDate: Mon, 6 Aug 2012 19:00:37 +0200
Committer: H. Peter Anvin <hpa@zytor.com>
CommitDate: Mon, 6 Aug 2012 19:18:29 -0700
x86, cpu: Push TLB detection CPUID check down
Push the max CPUID leaf check into the ->detect_tlb function and remove
general test case from the generic path.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Link: http://lkml.kernel.org/r/1344272439-29080-3-git-send-email-bp@amd64.org
Acked-by: Alex Shi <alex.shi@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/kernel/cpu/common.c | 3 +--
arch/x86/kernel/cpu/intel.c | 4 ++++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d239977..080f4a7 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -940,8 +940,7 @@ void __init identify_boot_cpu(void)
#else
vgetcpu_set_mode();
#endif
- if (boot_cpu_data.cpuid_level >= 2)
- cpu_detect_tlb(&boot_cpu_data);
+ cpu_detect_tlb(&boot_cpu_data);
}
void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 0a4ce29..198e019 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -648,6 +648,10 @@ static void __cpuinit intel_detect_tlb(struct cpuinfo_x86 *c)
int i, j, n;
unsigned int regs[4];
unsigned char *desc = (unsigned char *)regs;
+
+ if (c->cpuid_level < 2)
+ return;
+
/* Number of times to iterate */
n = cpuid_eax(2) & 0xFF;
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1 3/4] x86, CPU: Add AMD TLB size detection
2012-08-06 17:00 [PATCH v1 0/4] x86, CPU: TLB flushall shift, the AMD side Borislav Petkov
2012-08-06 17:00 ` [PATCH v1 1/4] x86, CPU: Fixup tlb_flushall_shift formatting Borislav Petkov
2012-08-06 17:00 ` [PATCH v1 2/4] x86, CPU: Push TLB detection CPUID check down Borislav Petkov
@ 2012-08-06 17:00 ` Borislav Petkov
2012-08-07 3:09 ` [tip:x86/mm] x86, cpu: " tip-bot for Borislav Petkov
2012-08-06 17:00 ` [PATCH v1 4/4] x86, CPU: Preset default tlb_flushall_shift on AMD Borislav Petkov
3 siblings, 1 reply; 10+ messages in thread
From: Borislav Petkov @ 2012-08-06 17:00 UTC (permalink / raw)
To: H. Peter Anvin; +Cc: Alex Shi, X86-ML, LKML, Borislav Petkov
From: Borislav Petkov <borislav.petkov@amd.com>
Read I- and DTLB entries count from CPUID on AMD. Handle all the
different family-specific cases.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
arch/x86/kernel/cpu/amd.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9d92e19039f0..bcd200839c90 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -737,6 +737,59 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
}
#endif
+static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+{
+ u32 ebx, eax, ecx, edx;
+ u16 mask = 0xfff;
+
+ if (c->x86 < 0xf)
+ return;
+
+ if (c->extended_cpuid_level < 0x80000006)
+ return;
+
+ cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
+
+ tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
+ tlb_lli_4k[ENTRIES] = ebx & mask;
+
+ /*
+ * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
+ * characteristics from the CPUID function 0x80000005 instead.
+ */
+ if (c->x86 == 0xf) {
+ cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
+ mask = 0xff;
+ }
+
+ /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+ if (!((eax >> 16) & mask)) {
+ u32 a, b, c, d;
+
+ cpuid(0x80000005, &a, &b, &c, &d);
+ tlb_lld_2m[ENTRIES] = (a >> 16) & 0xff;
+ } else {
+ tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
+ }
+
+ /* a 4M entry uses two 2M entries */
+ tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
+
+ /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+ if (!(eax & mask)) {
+ /* Erratum 658 */
+ if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
+ tlb_lli_2m[ENTRIES] = 1024;
+ } else {
+ cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
+ tlb_lli_2m[ENTRIES] = eax & 0xff;
+ }
+ } else
+ tlb_lli_2m[ENTRIES] = eax & mask;
+
+ tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
+}
+
static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
.c_vendor = "AMD",
.c_ident = { "AuthenticAMD" },
@@ -756,6 +809,7 @@ static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
.c_size_cache = amd_size_cache,
#endif
.c_early_init = early_init_amd,
+ .c_detect_tlb = cpu_detect_tlb_amd,
.c_bsp_init = bsp_init_amd,
.c_init = init_amd,
.c_x86_vendor = X86_VENDOR_AMD,
--
1.7.11.rc1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [tip:x86/mm] x86, cpu: Add AMD TLB size detection
2012-08-06 17:00 ` [PATCH v1 3/4] x86, CPU: Add AMD TLB size detection Borislav Petkov
@ 2012-08-07 3:09 ` tip-bot for Borislav Petkov
0 siblings, 0 replies; 10+ messages in thread
From: tip-bot for Borislav Petkov @ 2012-08-07 3:09 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, tglx, borislav.petkov
Commit-ID: b46882e4c4de4813947fce940fe74af794a1eb72
Gitweb: http://git.kernel.org/tip/b46882e4c4de4813947fce940fe74af794a1eb72
Author: Borislav Petkov <borislav.petkov@amd.com>
AuthorDate: Mon, 6 Aug 2012 19:00:38 +0200
Committer: H. Peter Anvin <hpa@zytor.com>
CommitDate: Mon, 6 Aug 2012 19:18:34 -0700
x86, cpu: Add AMD TLB size detection
Read I- and DTLB entries count from CPUID on AMD. Handle all the
different family-specific cases.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Link: http://lkml.kernel.org/r/1344272439-29080-4-git-send-email-bp@amd64.org
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/kernel/cpu/amd.c | 54 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9d92e19..bcd2008 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -737,6 +737,59 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
}
#endif
+static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
+{
+ u32 ebx, eax, ecx, edx;
+ u16 mask = 0xfff;
+
+ if (c->x86 < 0xf)
+ return;
+
+ if (c->extended_cpuid_level < 0x80000006)
+ return;
+
+ cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
+
+ tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
+ tlb_lli_4k[ENTRIES] = ebx & mask;
+
+ /*
+ * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
+ * characteristics from the CPUID function 0x80000005 instead.
+ */
+ if (c->x86 == 0xf) {
+ cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
+ mask = 0xff;
+ }
+
+ /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+ if (!((eax >> 16) & mask)) {
+ u32 a, b, c, d;
+
+ cpuid(0x80000005, &a, &b, &c, &d);
+ tlb_lld_2m[ENTRIES] = (a >> 16) & 0xff;
+ } else {
+ tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
+ }
+
+ /* a 4M entry uses two 2M entries */
+ tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
+
+ /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
+ if (!(eax & mask)) {
+ /* Erratum 658 */
+ if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
+ tlb_lli_2m[ENTRIES] = 1024;
+ } else {
+ cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
+ tlb_lli_2m[ENTRIES] = eax & 0xff;
+ }
+ } else
+ tlb_lli_2m[ENTRIES] = eax & mask;
+
+ tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
+}
+
static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
.c_vendor = "AMD",
.c_ident = { "AuthenticAMD" },
@@ -756,6 +809,7 @@ static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
.c_size_cache = amd_size_cache,
#endif
.c_early_init = early_init_amd,
+ .c_detect_tlb = cpu_detect_tlb_amd,
.c_bsp_init = bsp_init_amd,
.c_init = init_amd,
.c_x86_vendor = X86_VENDOR_AMD,
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1 4/4] x86, CPU: Preset default tlb_flushall_shift on AMD
2012-08-06 17:00 [PATCH v1 0/4] x86, CPU: TLB flushall shift, the AMD side Borislav Petkov
` (2 preceding siblings ...)
2012-08-06 17:00 ` [PATCH v1 3/4] x86, CPU: Add AMD TLB size detection Borislav Petkov
@ 2012-08-06 17:00 ` Borislav Petkov
2012-08-07 3:10 ` [tip:x86/mm] x86, cpu: " tip-bot for Borislav Petkov
3 siblings, 1 reply; 10+ messages in thread
From: Borislav Petkov @ 2012-08-06 17:00 UTC (permalink / raw)
To: H. Peter Anvin; +Cc: Alex Shi, X86-ML, LKML, Borislav Petkov
From: Borislav Petkov <borislav.petkov@amd.com>
Run the mprotect.c microbenchmark on all our families >= K8 and preset
the flushall shift variable accordingly.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
arch/x86/kernel/cpu/amd.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bcd200839c90..f7e98a2c0d12 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -737,6 +737,17 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
}
#endif
+static void __cpuinit cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)
+{
+ if (!cpu_has_invlpg)
+ return;
+
+ tlb_flushall_shift = 5;
+
+ if (c->x86 <= 0x11)
+ tlb_flushall_shift = 4;
+}
+
static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
{
u32 ebx, eax, ecx, edx;
@@ -788,6 +799,8 @@ static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
tlb_lli_2m[ENTRIES] = eax & mask;
tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
+
+ cpu_set_tlb_flushall_shift(c);
}
static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
--
1.7.11.rc1
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* [tip:x86/mm] x86, cpu: Preset default tlb_flushall_shift on AMD
2012-08-06 17:00 ` [PATCH v1 4/4] x86, CPU: Preset default tlb_flushall_shift on AMD Borislav Petkov
@ 2012-08-07 3:10 ` tip-bot for Borislav Petkov
0 siblings, 0 replies; 10+ messages in thread
From: tip-bot for Borislav Petkov @ 2012-08-07 3:10 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, tglx, borislav.petkov
Commit-ID: 057237bb35a605d795fd787868a1088705f26ee5
Gitweb: http://git.kernel.org/tip/057237bb35a605d795fd787868a1088705f26ee5
Author: Borislav Petkov <borislav.petkov@amd.com>
AuthorDate: Mon, 6 Aug 2012 19:00:39 +0200
Committer: H. Peter Anvin <hpa@zytor.com>
CommitDate: Mon, 6 Aug 2012 19:18:39 -0700
x86, cpu: Preset default tlb_flushall_shift on AMD
Run the mprotect.c microbenchmark on all our families >= K8 and preset
the flushall shift variable accordingly.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Link: http://lkml.kernel.org/r/1344272439-29080-5-git-send-email-bp@amd64.org
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/kernel/cpu/amd.c | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bcd2008..f7e98a2 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -737,6 +737,17 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
}
#endif
+static void __cpuinit cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)
+{
+ if (!cpu_has_invlpg)
+ return;
+
+ tlb_flushall_shift = 5;
+
+ if (c->x86 <= 0x11)
+ tlb_flushall_shift = 4;
+}
+
static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
{
u32 ebx, eax, ecx, edx;
@@ -788,6 +799,8 @@ static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
tlb_lli_2m[ENTRIES] = eax & mask;
tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
+
+ cpu_set_tlb_flushall_shift(c);
}
static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
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