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From: Stephen Boyd <sboyd@codeaurora.org>
To: David Brown <davidb@codeaurora.org>, Kumar Gala <galak@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Lina Iyer <lina.iyer@linaro.org>
Subject: [PATCH 2/8] msm: scm: Get cacheline size from CTR
Date: Mon,  4 Aug 2014 18:31:44 -0700	[thread overview]
Message-ID: <1407202310-3359-3-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1407202310-3359-1-git-send-email-sboyd@codeaurora.org>

Instead of hardcoding the cacheline size as 32, get the cacheline
size from the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-qcom/scm.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-qcom/scm.c b/arch/arm/mach-qcom/scm.c
index 820c72165e19..c08786ebf116 100644
--- a/arch/arm/mach-qcom/scm.c
+++ b/arch/arm/mach-qcom/scm.c
@@ -27,9 +27,6 @@
 
 #include "scm.h"
 
-/* Cache line size for msm8x60 */
-#define CACHELINESIZE 32
-
 #define SCM_ENOMEM		-5
 #define SCM_EOPNOTSUPP		-4
 #define SCM_EINVAL_ADDR		-3
@@ -214,13 +211,18 @@ static int __scm_call(const struct scm_command *cmd)
 
 static void scm_inv_range(unsigned long start, unsigned long end)
 {
-	start = round_down(start, CACHELINESIZE);
-	end = round_up(end, CACHELINESIZE);
+	u32 cacheline_size, ctr;
+
+	asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+	cacheline_size = 4 << ((ctr >> 16) & 0xf);
+
+	start = round_down(start, cacheline_size);
+	end = round_up(end, cacheline_size);
 	outer_inv_range(start, end);
 	while (start < end) {
 		asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
 		     : "memory");
-		start += CACHELINESIZE;
+		start += cacheline_size;
 	}
 	dsb();
 	isb();
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@codeaurora.org>
To: David Brown <davidb@codeaurora.org>, Kumar Gala <galak@codeaurora.org>
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Lina Iyer <lina.iyer@linaro.org>
Subject: [PATCH 2/8] msm: scm: Get cacheline size from CTR
Date: Mon,  4 Aug 2014 18:31:44 -0700	[thread overview]
Message-ID: <1407202310-3359-3-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1407202310-3359-1-git-send-email-sboyd@codeaurora.org>

Instead of hardcoding the cacheline size as 32, get the cacheline
size from the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-qcom/scm.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-qcom/scm.c b/arch/arm/mach-qcom/scm.c
index 820c72165e19..c08786ebf116 100644
--- a/arch/arm/mach-qcom/scm.c
+++ b/arch/arm/mach-qcom/scm.c
@@ -27,9 +27,6 @@
 
 #include "scm.h"
 
-/* Cache line size for msm8x60 */
-#define CACHELINESIZE 32
-
 #define SCM_ENOMEM		-5
 #define SCM_EOPNOTSUPP		-4
 #define SCM_EINVAL_ADDR		-3
@@ -214,13 +211,18 @@ static int __scm_call(const struct scm_command *cmd)
 
 static void scm_inv_range(unsigned long start, unsigned long end)
 {
-	start = round_down(start, CACHELINESIZE);
-	end = round_up(end, CACHELINESIZE);
+	u32 cacheline_size, ctr;
+
+	asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+	cacheline_size = 4 << ((ctr >> 16) & 0xf);
+
+	start = round_down(start, cacheline_size);
+	end = round_up(end, cacheline_size);
 	outer_inv_range(start, end);
 	while (start < end) {
 		asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
 		     : "memory");
-		start += CACHELINESIZE;
+		start += cacheline_size;
 	}
 	dsb();
 	isb();
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation


WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/8] msm: scm: Get cacheline size from CTR
Date: Mon,  4 Aug 2014 18:31:44 -0700	[thread overview]
Message-ID: <1407202310-3359-3-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1407202310-3359-1-git-send-email-sboyd@codeaurora.org>

Instead of hardcoding the cacheline size as 32, get the cacheline
size from the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-qcom/scm.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-qcom/scm.c b/arch/arm/mach-qcom/scm.c
index 820c72165e19..c08786ebf116 100644
--- a/arch/arm/mach-qcom/scm.c
+++ b/arch/arm/mach-qcom/scm.c
@@ -27,9 +27,6 @@
 
 #include "scm.h"
 
-/* Cache line size for msm8x60 */
-#define CACHELINESIZE 32
-
 #define SCM_ENOMEM		-5
 #define SCM_EOPNOTSUPP		-4
 #define SCM_EINVAL_ADDR		-3
@@ -214,13 +211,18 @@ static int __scm_call(const struct scm_command *cmd)
 
 static void scm_inv_range(unsigned long start, unsigned long end)
 {
-	start = round_down(start, CACHELINESIZE);
-	end = round_up(end, CACHELINESIZE);
+	u32 cacheline_size, ctr;
+
+	asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+	cacheline_size = 4 << ((ctr >> 16) & 0xf);
+
+	start = round_down(start, cacheline_size);
+	end = round_up(end, cacheline_size);
 	outer_inv_range(start, end);
 	while (start < end) {
 		asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
 		     : "memory");
-		start += CACHELINESIZE;
+		start += cacheline_size;
 	}
 	dsb();
 	isb();
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

  parent reply	other threads:[~2014-08-05  1:31 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-05  1:31 [PATCH 0/8] qcom SCM updates Stephen Boyd
2014-08-05  1:31 ` Stephen Boyd
2014-08-05  1:31 ` [PATCH 1/8] msm: scm: Fix incorrect cache invalidation Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31 ` Stephen Boyd [this message]
2014-08-05  1:31   ` [PATCH 2/8] msm: scm: Get cacheline size from CTR Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31 ` [PATCH 3/8] msm: scm: Flush the command buffer only instead of the entire cache Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31 ` [PATCH 4/8] msm: scm: Add atomic SCM APIs Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31 ` [PATCH 5/8] msm: scm: Add API to query for service/command availability Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31 ` [PATCH 6/8] msm: scm: Add a feat version query API Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31 ` [PATCH 7/8] msm: scm: Add logging of actual return code from scm call Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  1:31 ` [PATCH 8/8] msm: scm: Move the scm driver to drivers/soc/qcom Stephen Boyd
2014-08-05  1:31   ` Stephen Boyd
2014-08-05  4:07   ` Lina Iyer
2014-08-05  4:07     ` Lina Iyer
2014-08-05 20:12     ` Bjorn Andersson
2014-08-05 20:12       ` Bjorn Andersson
2014-08-05 20:12       ` Bjorn Andersson
2014-08-05 20:17       ` Lina Iyer
2014-08-05 20:17         ` Lina Iyer
2014-08-05 20:17         ` Lina Iyer
2015-01-22  1:13   ` Olof Johansson
2015-01-22  1:13     ` Olof Johansson
2015-01-22  1:13     ` Olof Johansson
2015-01-22  1:53     ` Bjorn Andersson
2015-01-22  1:53       ` Bjorn Andersson
2015-01-22  1:53       ` Bjorn Andersson
2015-01-22 16:49       ` Kumar Gala
2015-01-22 16:49         ` Kumar Gala
2015-01-22 16:49         ` Kumar Gala
2015-01-23  1:19     ` Rob Clark
2015-01-23  1:19       ` Rob Clark
2015-01-23  1:19       ` Rob Clark
2014-09-17 22:08 ` [PATCH 0/8] qcom SCM updates Kumar Gala
2014-09-17 22:08   ` Kumar Gala

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