[U-Boot] [PATCH 0/8] rockchip: spi: rk3399: support SPI on the RK3399

[U-Boot] [PATCH 0/8] rockchip: spi: rk3399: support SPI on the RK3399

[Philipp Tomsich]

The RK3399 has a similar SPI controller as previous Rockchip SoCs.

This changeset reuses this driver and evolves pinctrl and clk drivers for
the RK3399 to support the needs of the RK3399.
Validated for SPI1 and SPI5 on the RK3399-Q7.

We've included the changes to our defconfig and dts (both not upstream) in
the series to provide context for reviewers... these two final patches are
not intended to apply to the current upstream and the contained changes
will be subsumed by the (upcoming) patch publishing the RK3399-Q7 (Puma)
DTS and defconfig.


Jakob Unterwurzacher (3):
  rockchip: spi: enable support for the rk_spi driver for the RK3399
  rockchip: spi: rk3399: move CONFIG_SPI and CONFIG_SPI_FLASH to
    defconfig
  dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash

Philipp Tomsich (5):
  rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
  rockchip: pinctrl: rk3399: add support for the SPI5 controller
  defconfig: rk3399-puma: enable support for SPI and Winbond SPI flash
  defconfig: rk3399-puma: enable SPI as a boot-source in SPL
  rockchip: spl: RK3399: enable SPL_SPI_LOAD if SPI is enabled for SPL

 arch/arm/dts/rk3399-puma.dts                    | 26 ++++++++++
 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 +++++
 arch/arm/include/asm/arch-rockchip/periph.h     |  3 ++
 configs/puma_defconfig                          | 10 ++++
 drivers/clk/rockchip/clk_rk3399.c               | 69 +++++++++++++++++++++++++
 drivers/pinctrl/rockchip/pinctrl_rk3399.c       | 17 ++++++
 drivers/spi/rk_spi.c                            |  1 +
 include/configs/rk3399_common.h                 |  5 +-
 8 files changed, 141 insertions(+), 2 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH 1/8] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5

[Philipp Tomsich]

This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.

Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
---

 drivers/clk/rockchip/clk_rk3399.c | 69 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index f778ddf..b7c5a35 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -605,6 +605,67 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 	return DIV_TO_RATE(GPLL_HZ, src_clk_div);
 }
 
+#define SPI_CLK_REG_MASK(bus) \
+			(CLK_SPI_PLL_DIV_CON_MASK << \
+			CLK_SPI ##bus## _PLL_DIV_CON_SHIFT | \
+			CLK_SPI_PLL_SEL_MASK << \
+			CLK_SPI ##bus## _PLL_SEL_SHIFT)
+
+#define SPI_CLK_REG_VALUE(bus, clk_div) \
+			      ((clk_div - 1) << \
+					CLK_SPI ##bus## _PLL_DIV_CON_SHIFT | \
+			      CLK_SPI_PLL_SEL_GPLL << \
+					CLK_SPI ##bus## _PLL_SEL_SHIFT)
+
+#define SPI_CLK_DIV_VALUE(con, bus) \
+			(con >> CLK_SPI ##bus## _PLL_DIV_CON_SHIFT) & \
+				CLK_SPI_PLL_DIV_CON_MASK;
+
+static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
+{
+	u32 div, con;
+
+	switch (clk_id) {
+	case SCLK_SPI1:
+		con = readl(&cru->clksel_con[59]);
+		div = SPI_CLK_DIV_VALUE(con, 1);
+		break;
+	case SCLK_SPI5:
+		con = readl(&cru->clksel_con[58]);
+		div = SPI_CLK_DIV_VALUE(con, 5);
+		break;
+	default:
+		error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+{
+	int src_clk_div;
+
+	src_clk_div = GPLL_HZ / hz;
+	assert((src_clk_div - 1) < 127);
+
+	switch (clk_id) {
+	case SCLK_SPI1:
+		rk_clrsetreg(&cru->clksel_con[59], SPI_CLK_REG_MASK(1),
+			     I2C_CLK_REG_VALUE(1, src_clk_div));
+		break;
+	case SCLK_SPI5:
+		rk_clrsetreg(&cru->clksel_con[58], I2C_CLK_REG_MASK(5),
+			     I2C_CLK_REG_VALUE(5, src_clk_div));
+		break;
+	default:
+		error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(GPLL_HZ, src_clk_div);
+}
+
 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
 {
 	struct pll_div vpll_config = {0};
@@ -780,6 +841,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
 	case SCLK_I2C7:
 		rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 		break;
+	case SCLK_SPI1:
+	case SCLK_SPI5:
+		rate = rk3399_spi_get_clk(priv->cru, clk->id);
+		break;
 	case SCLK_UART0:
 	case SCLK_UART2:
 		return 24000000;
@@ -818,6 +883,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_I2C7:
 		ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
 		break;
+	case SCLK_SPI1:
+	case SCLK_SPI5:
+		ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
+		break;
 	case DCLK_VOP0:
 	case DCLK_VOP1:
 		ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
-- 
1.9.1

[U-Boot] [PATCH 1/8] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5

[Simon Glass]

Hi Philipp,

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This change adds support for configuring the module clocks for SPI1 and
> SPI5 from the 594MHz GPLL.
>
> Note that the driver (rk_spi.c) always sets this to 99MHz, but the
> implemented functionality is more general and will also support
> different clock configurations.
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3399.c | 69 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index f778ddf..b7c5a35 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -605,6 +605,67 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
>         return DIV_TO_RATE(GPLL_HZ, src_clk_div);
>  }
>
> +#define SPI_CLK_REG_MASK(bus) \
> +                       (CLK_SPI_PLL_DIV_CON_MASK << \
> +                       CLK_SPI ##bus## _PLL_DIV_CON_SHIFT | \
> +                       CLK_SPI_PLL_SEL_MASK << \
> +                       CLK_SPI ##bus## _PLL_SEL_SHIFT)
> +
> +#define SPI_CLK_REG_VALUE(bus, clk_div) \
> +                             ((clk_div - 1) << \
> +                                       CLK_SPI ##bus## _PLL_DIV_CON_SHIFT | \
> +                             CLK_SPI_PLL_SEL_GPLL << \
> +                                       CLK_SPI ##bus## _PLL_SEL_SHIFT)
> +
> +#define SPI_CLK_DIV_VALUE(con, bus) \
> +                       (con >> CLK_SPI ##bus## _PLL_DIV_CON_SHIFT) & \
> +                               CLK_SPI_PLL_DIV_CON_MASK;

I'm really not keen on this macro pasting as it makes it hard to find things.

Can we instead have something like:

static const u8 spi_shift[] = {
   CLK_SPI0_PLL_SEL_SHIFT,
   CLK_SPI1_PLL_SEL_SHIFT,
  ...
};

and then read it from the array? Since there are multiple pieces you might want:

struct spi_reg_layout {
   u8 sel_shift;
   u8 div_shift;
   u8 sel_mask;
   u8 div_mask;
};

static const struct spi_reg_layout spi_reg_layout[] = {
   { ... },
   { ... },

This is how Tegra does things, for example.

> +
> +static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
> +{
> +       u32 div, con;
> +
> +       switch (clk_id) {
> +       case SCLK_SPI1:
> +               con = readl(&cru->clksel_con[59]);
> +               div = SPI_CLK_DIV_VALUE(con, 1);
> +               break;
> +       case SCLK_SPI5:
> +               con = readl(&cru->clksel_con[58]);
> +               div = SPI_CLK_DIV_VALUE(con, 5);
> +               break;
> +       default:
> +               error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
> +               return -EINVAL;
> +       }
> +
> +       return DIV_TO_RATE(GPLL_HZ, div);
> +}
> +
> +static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> +{
> +       int src_clk_div;
> +
> +       src_clk_div = GPLL_HZ / hz;
> +       assert((src_clk_div - 1) < 127);
> +
> +       switch (clk_id) {
> +       case SCLK_SPI1:
> +               rk_clrsetreg(&cru->clksel_con[59], SPI_CLK_REG_MASK(1),
> +                            I2C_CLK_REG_VALUE(1, src_clk_div));
> +               break;
> +       case SCLK_SPI5:
> +               rk_clrsetreg(&cru->clksel_con[58], I2C_CLK_REG_MASK(5),
> +                            I2C_CLK_REG_VALUE(5, src_clk_div));
> +               break;
> +       default:
> +               error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
> +               return -EINVAL;
> +       }
> +
> +       return DIV_TO_RATE(GPLL_HZ, src_clk_div);
> +}
> +
>  static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
>  {
>         struct pll_div vpll_config = {0};
> @@ -780,6 +841,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
>         case SCLK_I2C7:
>                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
>                 break;
> +       case SCLK_SPI1:
> +       case SCLK_SPI5:
> +               rate = rk3399_spi_get_clk(priv->cru, clk->id);
> +               break;
>         case SCLK_UART0:
>         case SCLK_UART2:
>                 return 24000000;
> @@ -818,6 +883,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
>         case SCLK_I2C7:
>                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
>                 break;
> +       case SCLK_SPI1:
> +       case SCLK_SPI5:
> +               ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
> +               break;
>         case DCLK_VOP0:
>         case DCLK_VOP1:
>                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
> --
> 1.9.1
>

Regards,
Simon

[U-Boot] [PATCH 2/8] rockchip: pinctrl: rk3399: add support for the SPI5 controller

[Philipp Tomsich]

This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
 * grf_rk3399.h: adds definition for configuring the SPI5 pins
   		 in the GPIO2C group
 * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
   		     PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
		     through SPI5 to the appropriate pin-config
		     function; implements the pin-configuration
		     for PERIPH_ID_SPI5 using the GPIO2C group

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
---

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 ++++++++++++
 arch/arm/include/asm/arch-rockchip/periph.h     |  3 +++
 drivers/pinctrl/rockchip/pinctrl_rk3399.c       | 17 +++++++++++++++++
 3 files changed, 32 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index c424753..cbcff2e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -344,6 +344,18 @@ enum {
 	GRF_GPIO2C1_SEL_SHIFT   = 2,
 	GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
 	GRF_UART0BT_SOUT        = 1,
+	GRF_GPIO2C4_SEL_SHIFT   = 8,
+	GRF_GPIO2C4_SEL_MASK    = 3 << GRF_GPIO2C4_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_RXD     = 2,
+	GRF_GPIO2C5_SEL_SHIFT   = 10,
+	GRF_GPIO2C5_SEL_MASK    = 3 << GRF_GPIO2C5_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_TXD     = 2,
+	GRF_GPIO2C6_SEL_SHIFT   = 12,
+	GRF_GPIO2C6_SEL_MASK    = 3 << GRF_GPIO2C6_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CLK     = 2,
+	GRF_GPIO2C7_SEL_SHIFT   = 14,
+	GRF_GPIO2C7_SEL_MASK    = 3 << GRF_GPIO2C7_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CSN0    = 2,
 
 	/* GRF_GPIO3A_IOMUX */
 	GRF_GPIO3A0_SEL_SHIFT   = 0,
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
index 239a274..8018d47 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -27,6 +27,9 @@ enum periph_id {
 	PERIPH_ID_SPI0,
 	PERIPH_ID_SPI1,
 	PERIPH_ID_SPI2,
+	PERIPH_ID_SPI3,
+	PERIPH_ID_SPI4,
+	PERIPH_ID_SPI5,
 	PERIPH_ID_UART0,
 	PERIPH_ID_UART1,
 	PERIPH_ID_UART2,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index 507bec4..6eb657f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
 			     | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
 			     | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
 		break;
+	case PERIPH_ID_SPI5:
+		if (cs != 0)
+			goto err;
+		rk_clrsetreg(&grf->gpio2c_iomux,
+			     GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
+			     | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
+			     GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
+			     | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
+			     | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
+			     | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
+		break;
 	default:
+		printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
 		goto err;
 	}
 
@@ -259,6 +271,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
 	case PERIPH_ID_SPI2:
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+	case PERIPH_ID_SPI5:
 		pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
 		break;
 	case PERIPH_ID_UART0:
@@ -307,6 +322,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 		return PERIPH_ID_SPI1;
 	case 52:
 		return PERIPH_ID_SPI2;
+	case 132:
+		return PERIPH_ID_SPI5;
 	case 57:
 		return PERIPH_ID_I2C0;
 	case 59: /* Note strange order */
-- 
1.9.1

[U-Boot] [PATCH 2/8] rockchip: pinctrl: rk3399: add support for the SPI5 controller

[Simon Glass]

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This commit adds support for the pin-configuration of the SPI5
> controller of the RK3399 through the following changes:
>  * grf_rk3399.h: adds definition for configuring the SPI5 pins
>                  in the GPIO2C group
>  * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
>  * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
>                      PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
>                      through SPI5 to the appropriate pin-config
>                      function; implements the pin-configuration
>                      for PERIPH_ID_SPI5 using the GPIO2C group
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
> ---
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 ++++++++++++
>  arch/arm/include/asm/arch-rockchip/periph.h     |  3 +++
>  drivers/pinctrl/rockchip/pinctrl_rk3399.c       | 17 +++++++++++++++++
>  3 files changed, 32 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/8] rockchip: spi: enable support for the rk_spi driver for the RK3399

[Philipp Tomsich]

From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>

The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399.  This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.

This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
---

 drivers/spi/rk_spi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 3e44f17..91e169c 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -403,6 +403,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
 
 static const struct udevice_id rockchip_spi_ids[] = {
 	{ .compatible = "rockchip,rk3288-spi" },
+	{ .compatible = "rockchip,rk3399-spi" },
 	{ }
 };
 
-- 
1.9.1

[U-Boot] [PATCH 3/8] rockchip: spi: enable support for the rk_spi driver for the RK3399

[Simon Glass]

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
>
> The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
> block found in the RK3399.  This has been confirmed both with SPI NOR
> flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
>
> This change adds the 'rockchip,rk3399-spi' string to its compatible
> list to allow reuse of the existing driver.
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
> ---
>
>  drivers/spi/rk_spi.c | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 4/8] rockchip: spi: rk3399: move CONFIG_SPI and CONFIG_SPI_FLASH to defconfig

[Philipp Tomsich]

From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>

On the RK3399-Q7 we need to enable a number of configuration options
(e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI
and CONFIG_SPI_FLASH active.

To allow for these being defined in Kconfig (e.g. via defconfig) and
to avoid a warning on having the macro defined multiple times, we
remove them from the common header file.

Note that the rk3399-evb does not currently have the rk_spi.c driver
active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the
evb-rk3399_defconfig as part of this change.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
---

 include/configs/rk3399_common.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index c44f8ad..9d22e0c 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -52,8 +52,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_NR_DRAM_BANKS		1
 
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
 #ifndef CONFIG_SPL_BUILD
-- 
1.9.1

[U-Boot] [PATCH 4/8] rockchip: spi: rk3399: move CONFIG_SPI and CONFIG_SPI_FLASH to defconfig

[Simon Glass]

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
>
> On the RK3399-Q7 we need to enable a number of configuration options
> (e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI
> and CONFIG_SPI_FLASH active.
>
> To allow for these being defined in Kconfig (e.g. via defconfig) and
> to avoid a warning on having the macro defined multiple times, we
> remove them from the common header file.
>
> Note that the rk3399-evb does not currently have the rk_spi.c driver
> active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the
> evb-rk3399_defconfig as part of this change.
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
> ---
>
>  include/configs/rk3399_common.h | 2 --
>  1 file changed, 2 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 5/8] defconfig: rk3399-puma: enable support for SPI and Winbond SPI flash

[Philipp Tomsich]

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

 configs/puma_defconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/configs/puma_defconfig b/configs/puma_defconfig
index d045d41..fb33ba9 100644
--- a/configs/puma_defconfig
+++ b/configs/puma_defconfig
@@ -73,3 +73,10 @@ CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 # CONFIG_USE_TINY_PRINTF is not set
 CONFIG_ERRNO_STR=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
+CONFIG_CMD_SPI=y
-- 
1.9.1

[U-Boot] [PATCH 5/8] defconfig: rk3399-puma: enable support for SPI and Winbond SPI flash

[Simon Glass]

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
>  configs/puma_defconfig | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/configs/puma_defconfig b/configs/puma_defconfig
> index d045d41..fb33ba9 100644
> --- a/configs/puma_defconfig
> +++ b/configs/puma_defconfig
> @@ -73,3 +73,10 @@ CONFIG_USB_EHCI_GENERIC=y
>  CONFIG_USB_STORAGE=y
>  # CONFIG_USE_TINY_PRINTF is not set
>  CONFIG_ERRNO_STR=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_ROCKCHIP_SPI=y
> +CONFIG_SPI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_USE_4K_SECTORS=y
> +CONFIG_CMD_SPI=y
> --
> 1.9.1
>

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 6/8] defconfig: rk3399-puma: enable SPI as a boot-source in SPL

[Philipp Tomsich]

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

 configs/puma_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/puma_defconfig b/configs/puma_defconfig
index fb33ba9..efca8f9 100644
--- a/configs/puma_defconfig
+++ b/configs/puma_defconfig
@@ -80,3 +80,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_USE_4K_SECTORS=y
 CONFIG_CMD_SPI=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+
-- 
1.9.1

[U-Boot] [PATCH 6/8] defconfig: rk3399-puma: enable SPI as a boot-source in SPL

[Simon Glass]

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
>  configs/puma_defconfig | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/configs/puma_defconfig b/configs/puma_defconfig
> index fb33ba9..efca8f9 100644
> --- a/configs/puma_defconfig
> +++ b/configs/puma_defconfig
> @@ -80,3 +80,6 @@ CONFIG_SPI_FLASH=y
>  CONFIG_SPI_FLASH_WINBOND=y
>  CONFIG_SPI_FLASH_USE_4K_SECTORS=y
>  CONFIG_CMD_SPI=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +

unwanted blank line? Also are these in the right order?

> --
> 1.9.1
>

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 7/8] rockchip: spl: RK3399: enable SPL_SPI_LOAD if SPI is enabled for SPL

[Philipp Tomsich]

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

 include/configs/rk3399_common.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 9d22e0c..c409d95 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -18,6 +18,9 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+#define CONFIG_SPL_SPI_LOAD
+#endif
 
 #define COUNTER_FREQUENCY               24000000
 
-- 
1.9.1

[U-Boot] [PATCH 7/8] rockchip: spl: RK3399: enable SPL_SPI_LOAD if SPI is enabled for SPL

[Simon Glass]

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
>  include/configs/rk3399_common.h | 3 +++
>  1 file changed, 3 insertions(+)
>

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 8/8] dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash

[Philipp Tomsich]

From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>

The RK3399-Q7 (Puma) unsually (this is a build-time option for
customised boards) has an on-module SPI-flash connected to SPI1.
As of today, this is a Winbond W25Q32DW (32MBit) device.

The SPI5 controller is routed to the Q7 edge connector and provides
general-purpose SPI connectivity for customer base-boards.

With some minor improvements on integration into our outbound tree
 - explicitly modelled the SPI flash as 'spiflash' under spi0
   [dts: rk3399-puma: explicitly model spi-flash under spi1]
 - renamed the aliases to spi0 and spi1 to allow easier use of
   commands and legacy (SPL) infrastructure... i.e. the controllers
   will be 0 and 1 for 'sf probe', 'sspi', etc.
   [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands]

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
---

 arch/arm/dts/rk3399-puma.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts
index 4f68451..dc00bd9 100644
--- a/arch/arm/dts/rk3399-puma.dts
+++ b/arch/arm/dts/rk3399-puma.dts
@@ -18,6 +18,11 @@
 		u-boot,spl-boot-order = &sdhci, "mmc1";
 	};
 
+	aliases {
+		spi0 = &spi1;
+		spi1 = &spi5;
+	};
+
 	vdd_center: vdd-center {
 		compatible = "pwm-regulator";
 		pwms = <&pwm3 0 25000 0>;
@@ -159,3 +164,24 @@
 	rx_delay = <0x10>;
 	status = "okay";
 };
+
+&spi1 {
+	u-boot,dm-pre-reloc;
+
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	spiflash: w25q32dw at 0 {
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
+
+&spi5 {
+	status = "okay";
+};
-- 
1.9.1

[U-Boot] [PATCH 8/8] dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash

[Simon Glass]

On 28 March 2017 at 02:58, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
>
> The RK3399-Q7 (Puma) unsually (this is a build-time option for
> customised boards) has an on-module SPI-flash connected to SPI1.
> As of today, this is a Winbond W25Q32DW (32MBit) device.
>
> The SPI5 controller is routed to the Q7 edge connector and provides
> general-purpose SPI connectivity for customer base-boards.
>
> With some minor improvements on integration into our outbound tree
>  - explicitly modelled the SPI flash as 'spiflash' under spi0
>    [dts: rk3399-puma: explicitly model spi-flash under spi1]
>  - renamed the aliases to spi0 and spi1 to allow easier use of
>    commands and legacy (SPL) infrastructure... i.e. the controllers
>    will be 0 and 1 for 'sf probe', 'sspi', etc.
>    [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands]
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
> ---
>
>  arch/arm/dts/rk3399-puma.dts | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>