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From: no-reply@patchew.org
To: kbastian@mail.uni-paderborn.de
Cc: fam@euphon.net, sagark@eecs.berkeley.edu, palmer@sifive.com,
	richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Date: Thu, 31 Jan 2019 09:50:22 -0800 (PST)	[thread overview]
Message-ID: <154895702100.23946.13828912088535749394@ebba9967afc0> (raw)
In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de>

Patchew URL: https://patchew.org/QEMU/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190123092538.8004-1-kbastian@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
a6f2515ae7 target/riscv: Remaining rvc insn reuse 32 bit translators
93fb3eb825 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
5ef563612b target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
9dd8991561 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
953afe2701 target/riscv: Convert @cs_2 insns to share translation functions
0bceda7177 target/riscv: Remove decode_RV32_64G()
940985f42b target/riscv: Remove gen_system()
bb4e34c120 target/riscv: Rename trans_arith to gen_arith
4427b58cf1 target/riscv: Remove manual decoding of RV32/64M insn
8e1e88f2ab target/riscv: Remove shift and slt insn manual decoding
afe60ebe74 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
4d43443e2d target/riscv: Move gen_arith_imm() decoding into trans_* functions
de56786c84 target/riscv: Remove manual decoding from gen_store()
4fc18f5eb2 target/riscv: Remove manual decoding from gen_load()
66425abdcd target/riscv: Remove manual decoding from gen_branch()
4ca0a5af54 target/riscv: Remove gen_jalr()
19988a3346 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
a7aded6fd3 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
fd3e32e7e8 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
a56aa5a849 target/riscv: Convert RV priv insns to decodetree
c2b742260a target/riscv: Convert RV64D insns to decodetree
7c715e34ff target/riscv: Convert RV32D insns to decodetree
556d60b104 target/riscv: Convert RV64F insns to decodetree
7f43f5d073 target/riscv: Convert RV32F insns to decodetree
be015ccb8b target/riscv: Convert RV64A insns to decodetree
7bc964b2c5 target/riscv: Convert RV32A insns to decodetree
24b2b53919 target/riscv: Convert RVXM insns to decodetree
fcc4af623a target/riscv: Convert RVXI csr insns to decodetree
a2d032d8b4 target/riscv: Convert RVXI fence insns to decodetree
609b7bd70a target/riscv: Convert RVXI arithmetic insns to decodetree
8cd785fa06 target/riscv: Convert RV64I load/store insns to decodetree
0769f03796 target/riscv: Convert RV32I load/store insns to decodetree
3a1daf706a target/riscv: Convert RVXI branch insns to decodetree
a351b2d421 target/riscv: Activate decodetree and implemnt LUI & AUIPC
6d6ac91f67 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 6d6ac91f67ff (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit a351b2d4210b (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

ERROR: externs should be avoided in .c files
#124: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 3a1daf706aa1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 0769f037965c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 8cd785fa0678 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 609b7bd70a36 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a2d032d8b47f (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit fcc4af623a98 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 24b2b5391954 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 7bc964b2c549 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit be015ccb8b64 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 7f43f5d07372 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#77: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 556d60b104a3 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 7c715e34ff54 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#50: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit c2b742260a63 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit a56aa5a84908 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit fd3e32e7e801 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

ERROR: externs should be avoided in .c files
#245: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit a7aded6fd326 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 19988a334621 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 4ca0a5af54a0 (target/riscv: Remove gen_jalr())
21/35 Checking commit 66425abdcddc (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 4fc18f5eb222 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit de56786c8435 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 4d43443e2d92 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit afe60ebe74d0 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 8e1e88f2ab38 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4427b58cf10d (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit bb4e34c120a3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 940985f42bd3 (target/riscv: Remove gen_system())
30/35 Checking commit 0bceda71773b (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 953afe2701e0 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

ERROR: externs should be avoided in .c files
#181: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 9dd899156136 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 5ef563612bba (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 93fb3eb8256e (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit a6f2515ae7e6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

WARNING: multiple messages have this Message-ID (diff)
From: no-reply@patchew.org
To: kbastian@mail.uni-paderborn.de
Cc: fam@euphon.net, sagark@eecs.berkeley.edu, palmer@sifive.com,
	kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org,
	peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Date: Thu, 31 Jan 2019 09:50:22 -0800 (PST)	[thread overview]
Message-ID: <154895702100.23946.13828912088535749394@ebba9967afc0> (raw)
In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de>

Patchew URL: https://patchew.org/QEMU/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190123092538.8004-1-kbastian@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
a6f2515ae7 target/riscv: Remaining rvc insn reuse 32 bit translators
93fb3eb825 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
5ef563612b target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
9dd8991561 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
953afe2701 target/riscv: Convert @cs_2 insns to share translation functions
0bceda7177 target/riscv: Remove decode_RV32_64G()
940985f42b target/riscv: Remove gen_system()
bb4e34c120 target/riscv: Rename trans_arith to gen_arith
4427b58cf1 target/riscv: Remove manual decoding of RV32/64M insn
8e1e88f2ab target/riscv: Remove shift and slt insn manual decoding
afe60ebe74 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
4d43443e2d target/riscv: Move gen_arith_imm() decoding into trans_* functions
de56786c84 target/riscv: Remove manual decoding from gen_store()
4fc18f5eb2 target/riscv: Remove manual decoding from gen_load()
66425abdcd target/riscv: Remove manual decoding from gen_branch()
4ca0a5af54 target/riscv: Remove gen_jalr()
19988a3346 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
a7aded6fd3 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
fd3e32e7e8 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
a56aa5a849 target/riscv: Convert RV priv insns to decodetree
c2b742260a target/riscv: Convert RV64D insns to decodetree
7c715e34ff target/riscv: Convert RV32D insns to decodetree
556d60b104 target/riscv: Convert RV64F insns to decodetree
7f43f5d073 target/riscv: Convert RV32F insns to decodetree
be015ccb8b target/riscv: Convert RV64A insns to decodetree
7bc964b2c5 target/riscv: Convert RV32A insns to decodetree
24b2b53919 target/riscv: Convert RVXM insns to decodetree
fcc4af623a target/riscv: Convert RVXI csr insns to decodetree
a2d032d8b4 target/riscv: Convert RVXI fence insns to decodetree
609b7bd70a target/riscv: Convert RVXI arithmetic insns to decodetree
8cd785fa06 target/riscv: Convert RV64I load/store insns to decodetree
0769f03796 target/riscv: Convert RV32I load/store insns to decodetree
3a1daf706a target/riscv: Convert RVXI branch insns to decodetree
a351b2d421 target/riscv: Activate decodetree and implemnt LUI & AUIPC
6d6ac91f67 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 6d6ac91f67ff (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit a351b2d4210b (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

ERROR: externs should be avoided in .c files
#124: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 3a1daf706aa1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 0769f037965c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 8cd785fa0678 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 609b7bd70a36 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a2d032d8b47f (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit fcc4af623a98 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 24b2b5391954 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 7bc964b2c549 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit be015ccb8b64 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 7f43f5d07372 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#77: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 556d60b104a3 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 7c715e34ff54 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#50: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit c2b742260a63 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit a56aa5a84908 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit fd3e32e7e801 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

ERROR: externs should be avoided in .c files
#245: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit a7aded6fd326 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 19988a334621 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 4ca0a5af54a0 (target/riscv: Remove gen_jalr())
21/35 Checking commit 66425abdcddc (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 4fc18f5eb222 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit de56786c8435 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 4d43443e2d92 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit afe60ebe74d0 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 8e1e88f2ab38 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4427b58cf10d (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit bb4e34c120a3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 940985f42bd3 (target/riscv: Remove gen_system())
30/35 Checking commit 0bceda71773b (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 953afe2701e0 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

ERROR: externs should be avoided in .c files
#181: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 9dd899156136 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 5ef563612bba (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 93fb3eb8256e (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit a6f2515ae7e6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

  parent reply	other threads:[~2019-01-31 17:50 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-23  9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:23   ` [Qemu-devel] " Alistair
2019-01-25 22:23     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:23   ` [Qemu-devel] " Alistair
2019-01-25 22:23     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:25   ` [Qemu-devel] " Alistair
2019-01-25 22:25     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:27   ` [Qemu-devel] " Alistair
2019-01-25 22:27     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:28   ` [Qemu-devel] " Alistair
2019-01-25 22:28     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:29   ` [Qemu-devel] " Alistair
2019-01-25 22:29     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-31 17:50 ` no-reply [this message]
2019-01-31 17:50   ` [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply
2019-01-31 18:18 ` no-reply
2019-01-31 18:18   ` [Qemu-riscv] " no-reply
2019-01-31 18:22 ` no-reply
2019-01-31 18:22   ` [Qemu-riscv] " no-reply
2019-02-12 23:21 ` Palmer Dabbelt
2019-02-12 23:21   ` [Qemu-riscv] " Palmer Dabbelt
2019-02-13  2:15   ` [Qemu-devel] " Palmer Dabbelt
2019-02-13  2:15     ` [Qemu-riscv] " Palmer Dabbelt
2019-02-13  9:06     ` [Qemu-devel] " Bastian Koppelmann
2019-02-13  9:06       ` [Qemu-riscv] " Bastian Koppelmann
2019-02-13 15:34       ` Palmer Dabbelt
2019-02-13 15:34         ` [Qemu-riscv] " Palmer Dabbelt
2019-02-14  0:37       ` Palmer Dabbelt
2019-02-14  0:37         ` [Qemu-riscv] " Palmer Dabbelt

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