From: Alistair <alistair23@gmail.com> To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, sagark@eecs.berkeley.edu, palmer@sifive.com Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Date: Fri, 25 Jan 2019 14:25:08 -0800 [thread overview] Message-ID: <c843cc70-966a-684f-7c73-0739dceb1dda@gmail.com> (raw) In-Reply-To: <20190123092538.8004-24-kbastian@mail.uni-paderborn.de> On 1/23/19 1:25 AM, Bastian Koppelmann wrote: > With decodetree we don't need to convert RISC-V opcodes into to MemOps > as the old gen_store() did. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++-------- > target/riscv/translate.c | 8 +++++--- > 2 files changed, 24 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c > index 1ad00bd776..da843b4e99 100644 > --- a/target/riscv/insn_trans/trans_rvi.inc.c > +++ b/target/riscv/insn_trans/trans_rvi.inc.c > @@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) > return gen_load(ctx, a, MO_TEUW); > } > > -static bool trans_sb(DisasContext *ctx, arg_sb *a) > +static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop) > { > - gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); > + TCGv t0 = tcg_temp_new(); > + TCGv dat = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + tcg_gen_addi_tl(t0, t0, a->imm); > + gen_get_gpr(dat, a->rs2); > + > + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); > + tcg_temp_free(t0); > + tcg_temp_free(dat); > return true; > } > > + > +static bool trans_sb(DisasContext *ctx, arg_sb *a) > +{ > + return gen_store(ctx, a, MO_SB); > +} > + > static bool trans_sh(DisasContext *ctx, arg_sh *a) > { > - gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); > - return true; > + return gen_store(ctx, a, MO_TESW); > } > > static bool trans_sw(DisasContext *ctx, arg_sw *a) > { > - gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); > - return true; > + return gen_store(ctx, a, MO_TESL); > } > > #ifdef TARGET_RISCV64 > @@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a) > > static bool trans_sd(DisasContext *ctx, arg_sd *a) > { > - gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); > - return true; > + return gen_store(ctx, a, MO_TEQ); > } > #endif > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index d0fefa8fb9..59452be191 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -55,6 +55,7 @@ typedef struct DisasContext { > CPURISCVState *env; > } DisasContext; > > +#ifdef TARGET_RISCV64 > /* convert riscv funct3 to qemu memop for load/store */ > static const int tcg_memop_lookup[8] = { > [0 ... 7] = -1, > @@ -68,6 +69,7 @@ static const int tcg_memop_lookup[8] = { > [6] = MO_TEUL, > #endif > }; > +#endif > > #ifdef TARGET_RISCV64 > #define CASE_OP_32_64(X) case X: case glue(X, W) > @@ -509,9 +511,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, > tcg_temp_free(t0); > tcg_temp_free(t1); > } > -#endif > > -static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, > +static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, > target_long imm) > { > TCGv t0 = tcg_temp_new(); > @@ -530,6 +531,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, > tcg_temp_free(t0); > tcg_temp_free(dat); > } > +#endif > > #ifdef TARGET_RISCV32 > static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, > @@ -653,7 +655,7 @@ static void decode_RV32_64C0(DisasContext *ctx) > case 7: > #if defined(TARGET_RISCV64) > /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ > - gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2, > + gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, > GET_C_LD_IMM(ctx->opcode)); > #else > /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair <alistair23@gmail.com> To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, sagark@eecs.berkeley.edu, palmer@sifive.com Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Date: Fri, 25 Jan 2019 14:25:08 -0800 [thread overview] Message-ID: <c843cc70-966a-684f-7c73-0739dceb1dda@gmail.com> (raw) In-Reply-To: <20190123092538.8004-24-kbastian@mail.uni-paderborn.de> On 1/23/19 1:25 AM, Bastian Koppelmann wrote: > With decodetree we don't need to convert RISC-V opcodes into to MemOps > as the old gen_store() did. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++-------- > target/riscv/translate.c | 8 +++++--- > 2 files changed, 24 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c > index 1ad00bd776..da843b4e99 100644 > --- a/target/riscv/insn_trans/trans_rvi.inc.c > +++ b/target/riscv/insn_trans/trans_rvi.inc.c > @@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) > return gen_load(ctx, a, MO_TEUW); > } > > -static bool trans_sb(DisasContext *ctx, arg_sb *a) > +static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop) > { > - gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); > + TCGv t0 = tcg_temp_new(); > + TCGv dat = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + tcg_gen_addi_tl(t0, t0, a->imm); > + gen_get_gpr(dat, a->rs2); > + > + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); > + tcg_temp_free(t0); > + tcg_temp_free(dat); > return true; > } > > + > +static bool trans_sb(DisasContext *ctx, arg_sb *a) > +{ > + return gen_store(ctx, a, MO_SB); > +} > + > static bool trans_sh(DisasContext *ctx, arg_sh *a) > { > - gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); > - return true; > + return gen_store(ctx, a, MO_TESW); > } > > static bool trans_sw(DisasContext *ctx, arg_sw *a) > { > - gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); > - return true; > + return gen_store(ctx, a, MO_TESL); > } > > #ifdef TARGET_RISCV64 > @@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a) > > static bool trans_sd(DisasContext *ctx, arg_sd *a) > { > - gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); > - return true; > + return gen_store(ctx, a, MO_TEQ); > } > #endif > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index d0fefa8fb9..59452be191 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -55,6 +55,7 @@ typedef struct DisasContext { > CPURISCVState *env; > } DisasContext; > > +#ifdef TARGET_RISCV64 > /* convert riscv funct3 to qemu memop for load/store */ > static const int tcg_memop_lookup[8] = { > [0 ... 7] = -1, > @@ -68,6 +69,7 @@ static const int tcg_memop_lookup[8] = { > [6] = MO_TEUL, > #endif > }; > +#endif > > #ifdef TARGET_RISCV64 > #define CASE_OP_32_64(X) case X: case glue(X, W) > @@ -509,9 +511,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, > tcg_temp_free(t0); > tcg_temp_free(t1); > } > -#endif > > -static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, > +static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, > target_long imm) > { > TCGv t0 = tcg_temp_new(); > @@ -530,6 +531,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, > tcg_temp_free(t0); > tcg_temp_free(dat); > } > +#endif > > #ifdef TARGET_RISCV32 > static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, > @@ -653,7 +655,7 @@ static void decode_RV32_64C0(DisasContext *ctx) > case 7: > #if defined(TARGET_RISCV64) > /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ > - gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2, > + gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, > GET_C_LD_IMM(ctx->opcode)); > #else > /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ >
next prev parent reply other threads:[~2019-01-25 22:25 UTC|newest] Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:25 ` Alistair [this message] 2019-01-25 22:25 ` [Qemu-riscv] [Qemu-devel] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:27 ` [Qemu-devel] " Alistair 2019-01-25 22:27 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:28 ` [Qemu-devel] " Alistair 2019-01-25 22:28 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:29 ` [Qemu-devel] " Alistair 2019-01-25 22:29 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply 2019-01-31 17:50 ` [Qemu-riscv] " no-reply 2019-01-31 18:18 ` no-reply 2019-01-31 18:18 ` [Qemu-riscv] " no-reply 2019-01-31 18:22 ` no-reply 2019-01-31 18:22 ` [Qemu-riscv] " no-reply 2019-02-12 23:21 ` Palmer Dabbelt 2019-02-12 23:21 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-devel] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 9:06 ` [Qemu-devel] " Bastian Koppelmann 2019-02-13 9:06 ` [Qemu-riscv] " Bastian Koppelmann 2019-02-13 15:34 ` Palmer Dabbelt 2019-02-13 15:34 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-14 0:37 ` Palmer Dabbelt 2019-02-14 0:37 ` [Qemu-riscv] " Palmer Dabbelt
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