From: Yash Shah <yash.shah@sifive.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com Cc: aou@eecs.berkeley.edu, allison@lohutok.net, alexios.zavras@intel.com, gregkh@linuxfoundation.org, tglx@linutronix.de, bp@suse.de, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah <yash.shah@sifive.com> Subject: [PATCH v4 0/2] cacheinfo support to read no. of L2 cache ways enabled Date: Fri, 17 Jan 2020 13:13:36 +0530 [thread overview] Message-ID: <1579247018-6720-1-git-send-email-yash.shah@sifive.com> (raw) The patchset includes 2 patches. Patch 1 implements cache_get_priv_group which make use of a generic ops structure to return a private attribute group for custom cacheinfo. Patch 2 implements a private attribute named "number_of_ways_enabled" in the cacheinfo framework. Reading this attribute returns the number of L2 cache ways enabled at runtime, This patchset is based on Linux v5.5-rc6 and tested on HiFive Unleashed board. v4 vs v3: - Rename "sifive_l2_largest_wayenabled" to "l2_largest_wayenabled" and make it a static function v3 vs v2: - As per Anup Patel's suggestion[0], implement a new approach which uses generic ops structure. Hence addition of patch 1 to this series and corresponding changes to patch 2. - Dropped "riscv: dts: Add DT support for SiFive L2 cache controller" patch since it is already merged - Rebased on Linux v5.5-rc6 Changes in v2: - Rebase the series on v5.5-rc3 - Remove the reserved-memory node from DT [0]: https://lore.kernel.org/linux-riscv/CAAhSdy0CXde5s_ya=4YvmA4UQ5f5gLU-Z_FaOr8LPni+s_615Q@mail.gmail.com/ Yash Shah (2): riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure riscv: Add support to determine no. of L2 cache way enabled arch/riscv/include/asm/cacheinfo.h | 15 ++++++++++++++ arch/riscv/kernel/cacheinfo.c | 17 ++++++++++++++++ drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100644 arch/riscv/include/asm/cacheinfo.h -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Yash Shah <yash.shah@sifive.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com Cc: aou@eecs.berkeley.edu, sachin.ghadi@sifive.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, alexios.zavras@intel.com, Yash Shah <yash.shah@sifive.com>, anup@brainfault.org, tglx@linutronix.de, bp@suse.de, linux-riscv@lists.infradead.org, allison@lohutok.net Subject: [PATCH v4 0/2] cacheinfo support to read no. of L2 cache ways enabled Date: Fri, 17 Jan 2020 13:13:36 +0530 [thread overview] Message-ID: <1579247018-6720-1-git-send-email-yash.shah@sifive.com> (raw) The patchset includes 2 patches. Patch 1 implements cache_get_priv_group which make use of a generic ops structure to return a private attribute group for custom cacheinfo. Patch 2 implements a private attribute named "number_of_ways_enabled" in the cacheinfo framework. Reading this attribute returns the number of L2 cache ways enabled at runtime, This patchset is based on Linux v5.5-rc6 and tested on HiFive Unleashed board. v4 vs v3: - Rename "sifive_l2_largest_wayenabled" to "l2_largest_wayenabled" and make it a static function v3 vs v2: - As per Anup Patel's suggestion[0], implement a new approach which uses generic ops structure. Hence addition of patch 1 to this series and corresponding changes to patch 2. - Dropped "riscv: dts: Add DT support for SiFive L2 cache controller" patch since it is already merged - Rebased on Linux v5.5-rc6 Changes in v2: - Rebase the series on v5.5-rc3 - Remove the reserved-memory node from DT [0]: https://lore.kernel.org/linux-riscv/CAAhSdy0CXde5s_ya=4YvmA4UQ5f5gLU-Z_FaOr8LPni+s_615Q@mail.gmail.com/ Yash Shah (2): riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure riscv: Add support to determine no. of L2 cache way enabled arch/riscv/include/asm/cacheinfo.h | 15 ++++++++++++++ arch/riscv/kernel/cacheinfo.c | 17 ++++++++++++++++ drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100644 arch/riscv/include/asm/cacheinfo.h -- 2.7.4
next reply other threads:[~2020-01-17 7:44 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-17 7:43 Yash Shah [this message] 2020-01-17 7:43 ` [PATCH v4 0/2] cacheinfo support to read no. of L2 cache ways enabled Yash Shah 2020-01-17 7:43 ` [PATCH v4 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure Yash Shah 2020-01-17 7:43 ` Yash Shah 2020-01-17 7:43 ` [PATCH v4 2/2] riscv: Add support to determine no. of L2 cache way enabled Yash Shah 2020-01-17 7:43 ` Yash Shah 2020-02-07 18:24 ` Palmer Dabbelt 2020-02-07 18:24 ` Palmer Dabbelt 2020-02-18 6:25 ` Yash Shah 2020-02-18 6:25 ` Yash Shah
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