From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> To: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org>, Victor Kaplansky <VICTORK@il.ibm.com>, Oleg Nesterov <oleg@redhat.com>, Anton Blanchard <anton@samba.org>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Frederic Weisbecker <fweisbec@gmail.com>, LKML <linux-kernel@vger.kernel.org>, Linux PPC dev <linuxppc-dev@ozlabs.org>, Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>, Michael Ellerman <michael@ellerman.id.au>, Michael Neuling <mikey@neuling.org> Subject: Re: [RFC] arch: Introduce new TSO memory barrier smp_tmb() Date: Sun, 3 Nov 2013 14:42:42 -0800 [thread overview] Message-ID: <20131103224242.GF3947@linux.vnet.ibm.com> (raw) In-Reply-To: <20131103200124.GK19466@laptop.lan> On Sun, Nov 03, 2013 at 09:01:24PM +0100, Peter Zijlstra wrote: > On Sun, Nov 03, 2013 at 10:08:14AM -0800, Linus Torvalds wrote: > > On Sun, Nov 3, 2013 at 7:17 AM, Peter Zijlstra <peterz@infradead.org> wrote: > > > On Sun, Nov 03, 2013 at 06:40:17AM -0800, Paul E. McKenney wrote: > > >> If there was an smp_tmb(), I would likely use it in rcu_assign_pointer(). > > > > > > Well, I'm obviously all for introducing this new barrier, for it will > > > reduce a full mfence on x86 to a compiler barrier. And ppc can use > > > lwsync as opposed to sync afaict. Not sure ARM can do better. > > > > > > --- > > > Subject: arch: Introduce new TSO memory barrier smp_tmb() > > > > This is specialized enough that I would *really* like the name to be > > more descriptive. Compare to the special "smp_read_barrier_depends()" > > maco: it's unusual, and it has very specific semantics, so it gets a > > long and descriptive name. > > > > Memory ordering is subtle enough without then using names that are > > subtle in themselves. mb/rmb/wmb are conceptually pretty simple > > operations, and very basic when talking about memory ordering. > > "acquire" and "release" are less simple, but have descriptive names > > and have very specific uses in locking. > > > > In contrast "smp_tmb()" is a *horrible* name, because TSO is a > > description of the memory ordering, not of a particular barrier. It's > > also not even clear that you can have a "tso barrier", since the > > ordering (like acquire/release) presumably is really about one > > particular *store*, not about some kind of barrier between different > > operations. > > > > So please describe exactly what the semantics that barrier has, and > > then name the barrier that way. > > > > I assume that in this particular case, the semantics RCU wants is > > "write barrier, and no preceding reads can move past this point". Its semantics order prior reads against subsequent reads, prior reads against subsequent writes, and prior writes against subsequent writes. It does -not- order prior writes against subsequent reads. > > Calling that "smp_tmb()" is f*cking insane, imnsho. > > Fair enough; from what I could gather the proposed semantics are > RELEASE+WMB, such that neither reads not writes can cross over, writes > can't cross back, but reads could. > > Since both RELEASE and WMB are trivial under TSO the entire thing > collapses. And here are some candidate names, with no attempt to sort sanity from insanity: smp_storebuffer_mb() -- A barrier that enforces those orderings that do not invalidate the hardware store-buffer optimization. smp_not_w_r_mb() -- A barrier that orders everything except prior writes against subsequent reads. smp_acqrel_mb() -- A barrier that combines C/C++ acquire and release semantics. (C/C++ "acquire" orders a specific load against subsequent loads and stores, while C/C++ "release" orders a specific store against prior loads and stores.) Others? > Now I'm currently completely confused as to what C/C++ wrecks vs actual > proper memory order issues; let alone fully comprehend the case that > started all this. Each can result in similar wreckage. In either case, it is about failing to guarantee needed orderings. Thanx, Paul
WARNING: multiple messages have this Message-ID (diff)
From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> To: Peter Zijlstra <peterz@infradead.org> Cc: Michael Neuling <mikey@neuling.org>, Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>, Oleg Nesterov <oleg@redhat.com>, LKML <linux-kernel@vger.kernel.org>, Linux PPC dev <linuxppc-dev@ozlabs.org>, Anton Blanchard <anton@samba.org>, Frederic Weisbecker <fweisbec@gmail.com>, Victor Kaplansky <VICTORK@il.ibm.com>, Linus Torvalds <torvalds@linux-foundation.org> Subject: Re: [RFC] arch: Introduce new TSO memory barrier smp_tmb() Date: Sun, 3 Nov 2013 14:42:42 -0800 [thread overview] Message-ID: <20131103224242.GF3947@linux.vnet.ibm.com> (raw) In-Reply-To: <20131103200124.GK19466@laptop.lan> On Sun, Nov 03, 2013 at 09:01:24PM +0100, Peter Zijlstra wrote: > On Sun, Nov 03, 2013 at 10:08:14AM -0800, Linus Torvalds wrote: > > On Sun, Nov 3, 2013 at 7:17 AM, Peter Zijlstra <peterz@infradead.org> wrote: > > > On Sun, Nov 03, 2013 at 06:40:17AM -0800, Paul E. McKenney wrote: > > >> If there was an smp_tmb(), I would likely use it in rcu_assign_pointer(). > > > > > > Well, I'm obviously all for introducing this new barrier, for it will > > > reduce a full mfence on x86 to a compiler barrier. And ppc can use > > > lwsync as opposed to sync afaict. Not sure ARM can do better. > > > > > > --- > > > Subject: arch: Introduce new TSO memory barrier smp_tmb() > > > > This is specialized enough that I would *really* like the name to be > > more descriptive. Compare to the special "smp_read_barrier_depends()" > > maco: it's unusual, and it has very specific semantics, so it gets a > > long and descriptive name. > > > > Memory ordering is subtle enough without then using names that are > > subtle in themselves. mb/rmb/wmb are conceptually pretty simple > > operations, and very basic when talking about memory ordering. > > "acquire" and "release" are less simple, but have descriptive names > > and have very specific uses in locking. > > > > In contrast "smp_tmb()" is a *horrible* name, because TSO is a > > description of the memory ordering, not of a particular barrier. It's > > also not even clear that you can have a "tso barrier", since the > > ordering (like acquire/release) presumably is really about one > > particular *store*, not about some kind of barrier between different > > operations. > > > > So please describe exactly what the semantics that barrier has, and > > then name the barrier that way. > > > > I assume that in this particular case, the semantics RCU wants is > > "write barrier, and no preceding reads can move past this point". Its semantics order prior reads against subsequent reads, prior reads against subsequent writes, and prior writes against subsequent writes. It does -not- order prior writes against subsequent reads. > > Calling that "smp_tmb()" is f*cking insane, imnsho. > > Fair enough; from what I could gather the proposed semantics are > RELEASE+WMB, such that neither reads not writes can cross over, writes > can't cross back, but reads could. > > Since both RELEASE and WMB are trivial under TSO the entire thing > collapses. And here are some candidate names, with no attempt to sort sanity from insanity: smp_storebuffer_mb() -- A barrier that enforces those orderings that do not invalidate the hardware store-buffer optimization. smp_not_w_r_mb() -- A barrier that orders everything except prior writes against subsequent reads. smp_acqrel_mb() -- A barrier that combines C/C++ acquire and release semantics. (C/C++ "acquire" orders a specific load against subsequent loads and stores, while C/C++ "release" orders a specific store against prior loads and stores.) Others? > Now I'm currently completely confused as to what C/C++ wrecks vs actual > proper memory order issues; let alone fully comprehend the case that > started all this. Each can result in similar wreckage. In either case, it is about failing to guarantee needed orderings. Thanx, Paul
next prev parent reply other threads:[~2013-11-03 22:46 UTC|newest] Thread overview: 212+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-10-22 23:54 perf events ring buffer memory barrier on powerpc Michael Neuling 2013-10-23 7:39 ` Victor Kaplansky 2013-10-23 7:39 ` Victor Kaplansky 2013-10-23 14:19 ` Frederic Weisbecker 2013-10-23 14:19 ` Frederic Weisbecker 2013-10-23 14:25 ` Frederic Weisbecker 2013-10-23 14:25 ` Frederic Weisbecker 2013-10-25 17:37 ` Peter Zijlstra 2013-10-25 17:37 ` Peter Zijlstra 2013-10-25 20:31 ` Michael Neuling 2013-10-25 20:31 ` Michael Neuling 2013-10-27 9:00 ` Victor Kaplansky 2013-10-27 9:00 ` Victor Kaplansky 2013-10-28 9:22 ` Peter Zijlstra 2013-10-28 9:22 ` Peter Zijlstra 2013-10-28 10:02 ` Frederic Weisbecker 2013-10-28 10:02 ` Frederic Weisbecker 2013-10-28 12:38 ` Victor Kaplansky 2013-10-28 12:38 ` Victor Kaplansky 2013-10-28 13:26 ` Peter Zijlstra 2013-10-28 13:26 ` Peter Zijlstra 2013-10-28 16:34 ` Paul E. McKenney 2013-10-28 16:34 ` Paul E. McKenney 2013-10-28 20:17 ` Oleg Nesterov 2013-10-28 20:17 ` Oleg Nesterov 2013-10-28 20:58 ` Victor Kaplansky 2013-10-28 20:58 ` Victor Kaplansky 2013-10-29 10:21 ` Peter Zijlstra 2013-10-29 10:21 ` Peter Zijlstra 2013-10-29 10:30 ` Peter Zijlstra 2013-10-29 10:30 ` Peter Zijlstra 2013-10-29 10:35 ` Peter Zijlstra 2013-10-29 10:35 ` Peter Zijlstra 2013-10-29 20:15 ` Oleg Nesterov 2013-10-29 20:15 ` Oleg Nesterov 2013-10-29 19:27 ` Vince Weaver 2013-10-29 19:27 ` Vince Weaver 2013-10-30 10:42 ` Peter Zijlstra 2013-10-30 10:42 ` Peter Zijlstra 2013-10-30 11:48 ` James Hogan 2013-10-30 11:48 ` James Hogan 2013-10-30 12:48 ` Peter Zijlstra 2013-10-30 12:48 ` Peter Zijlstra 2013-11-06 13:19 ` [tip:perf/core] tools/perf: Add required memory barriers tip-bot for Peter Zijlstra 2013-11-06 13:50 ` Vince Weaver 2013-11-06 14:00 ` Peter Zijlstra 2013-11-06 14:28 ` Peter Zijlstra 2013-11-06 14:55 ` Vince Weaver 2013-11-06 15:10 ` Peter Zijlstra 2013-11-06 15:23 ` Peter Zijlstra 2013-11-06 14:44 ` Peter Zijlstra 2013-11-06 16:07 ` Peter Zijlstra 2013-11-06 17:31 ` Vince Weaver 2013-11-06 18:24 ` Peter Zijlstra 2013-11-07 8:21 ` Ingo Molnar 2013-11-07 14:27 ` Vince Weaver 2013-11-07 15:55 ` Ingo Molnar 2013-11-11 16:24 ` Peter Zijlstra 2013-11-11 21:10 ` Ingo Molnar 2013-10-29 21:23 ` perf events ring buffer memory barrier on powerpc Michael Neuling 2013-10-29 21:23 ` Michael Neuling 2013-10-30 9:27 ` Paul E. McKenney 2013-10-30 9:27 ` Paul E. McKenney 2013-10-30 11:25 ` Peter Zijlstra 2013-10-30 11:25 ` Peter Zijlstra 2013-10-30 14:52 ` Victor Kaplansky 2013-10-30 14:52 ` Victor Kaplansky 2013-10-30 15:39 ` Peter Zijlstra 2013-10-30 15:39 ` Peter Zijlstra 2013-10-30 17:14 ` Victor Kaplansky 2013-10-30 17:14 ` Victor Kaplansky 2013-10-30 17:44 ` Peter Zijlstra 2013-10-30 17:44 ` Peter Zijlstra 2013-10-31 6:16 ` Paul E. McKenney 2013-10-31 6:16 ` Paul E. McKenney 2013-11-01 13:12 ` Victor Kaplansky 2013-11-01 13:12 ` Victor Kaplansky 2013-11-02 16:36 ` Paul E. McKenney 2013-11-02 16:36 ` Paul E. McKenney 2013-11-02 17:26 ` Paul E. McKenney 2013-11-02 17:26 ` Paul E. McKenney 2013-10-31 6:40 ` Paul E. McKenney 2013-10-31 6:40 ` Paul E. McKenney 2013-11-01 14:25 ` Victor Kaplansky 2013-11-01 14:25 ` Victor Kaplansky 2013-11-02 17:28 ` Paul E. McKenney 2013-11-02 17:28 ` Paul E. McKenney 2013-11-01 14:56 ` Peter Zijlstra 2013-11-01 14:56 ` Peter Zijlstra 2013-11-02 17:32 ` Paul E. McKenney 2013-11-02 17:32 ` Paul E. McKenney 2013-11-03 14:40 ` Paul E. McKenney 2013-11-03 14:40 ` Paul E. McKenney 2013-11-03 15:17 ` [RFC] arch: Introduce new TSO memory barrier smp_tmb() Peter Zijlstra 2013-11-03 15:17 ` Peter Zijlstra 2013-11-03 18:08 ` Linus Torvalds 2013-11-03 18:08 ` Linus Torvalds 2013-11-03 20:01 ` Peter Zijlstra 2013-11-03 20:01 ` Peter Zijlstra 2013-11-03 22:42 ` Paul E. McKenney [this message] 2013-11-03 22:42 ` Paul E. McKenney 2013-11-03 23:34 ` Linus Torvalds 2013-11-03 23:34 ` Linus Torvalds 2013-11-04 10:51 ` Paul E. McKenney 2013-11-04 10:51 ` Paul E. McKenney 2013-11-04 11:22 ` Peter Zijlstra 2013-11-04 11:22 ` Peter Zijlstra 2013-11-04 16:27 ` Paul E. McKenney 2013-11-04 16:27 ` Paul E. McKenney 2013-11-04 16:48 ` Peter Zijlstra 2013-11-04 16:48 ` Peter Zijlstra 2013-11-04 19:11 ` Peter Zijlstra 2013-11-04 19:11 ` Peter Zijlstra 2013-11-04 19:18 ` Peter Zijlstra 2013-11-04 19:18 ` Peter Zijlstra 2013-11-04 20:54 ` Paul E. McKenney 2013-11-04 20:54 ` Paul E. McKenney 2013-11-04 20:53 ` Paul E. McKenney 2013-11-04 20:53 ` Paul E. McKenney 2013-11-05 14:05 ` Will Deacon 2013-11-05 14:05 ` Will Deacon 2013-11-05 14:49 ` Paul E. McKenney 2013-11-05 14:49 ` Paul E. McKenney 2013-11-05 18:49 ` Peter Zijlstra 2013-11-05 18:49 ` Peter Zijlstra 2013-11-06 11:00 ` Will Deacon 2013-11-06 11:00 ` Will Deacon 2013-11-06 12:39 ` Peter Zijlstra 2013-11-06 12:39 ` Peter Zijlstra 2013-11-06 12:51 ` Geert Uytterhoeven 2013-11-06 12:51 ` Geert Uytterhoeven 2013-11-06 13:57 ` Peter Zijlstra 2013-11-06 13:57 ` Peter Zijlstra 2013-11-06 18:48 ` Paul E. McKenney 2013-11-06 18:48 ` Paul E. McKenney 2013-11-06 19:42 ` Peter Zijlstra 2013-11-06 19:42 ` Peter Zijlstra 2013-11-07 11:17 ` Will Deacon 2013-11-07 11:17 ` Will Deacon 2013-11-07 13:36 ` Peter Zijlstra 2013-11-07 13:36 ` Peter Zijlstra 2013-11-07 23:50 ` Mathieu Desnoyers 2013-11-07 23:50 ` Mathieu Desnoyers 2013-11-04 11:05 ` Will Deacon 2013-11-04 11:05 ` Will Deacon 2013-11-04 16:34 ` Paul E. McKenney 2013-11-04 16:34 ` Paul E. McKenney 2013-11-03 20:59 ` Benjamin Herrenschmidt 2013-11-03 20:59 ` Benjamin Herrenschmidt 2013-11-03 22:43 ` Paul E. McKenney 2013-11-03 22:43 ` Paul E. McKenney 2013-11-03 17:07 ` perf events ring buffer memory barrier on powerpc Will Deacon 2013-11-03 22:47 ` Paul E. McKenney 2013-11-04 9:57 ` Will Deacon 2013-11-04 10:52 ` Paul E. McKenney 2013-11-01 16:11 ` Peter Zijlstra 2013-11-01 16:11 ` Peter Zijlstra 2013-11-02 17:46 ` Paul E. McKenney 2013-11-02 17:46 ` Paul E. McKenney 2013-11-01 16:18 ` Peter Zijlstra 2013-11-01 16:18 ` Peter Zijlstra 2013-11-02 17:49 ` Paul E. McKenney 2013-11-02 17:49 ` Paul E. McKenney 2013-10-30 13:28 ` Victor Kaplansky 2013-10-30 13:28 ` Victor Kaplansky 2013-10-30 15:51 ` Peter Zijlstra 2013-10-30 15:51 ` Peter Zijlstra 2013-10-30 18:29 ` Peter Zijlstra 2013-10-30 18:29 ` Peter Zijlstra 2013-10-30 19:11 ` Peter Zijlstra 2013-10-30 19:11 ` Peter Zijlstra 2013-10-31 4:33 ` Paul E. McKenney 2013-10-31 4:33 ` Paul E. McKenney 2013-10-31 4:32 ` Paul E. McKenney 2013-10-31 4:32 ` Paul E. McKenney 2013-10-31 9:04 ` Peter Zijlstra 2013-10-31 9:04 ` Peter Zijlstra 2013-10-31 15:07 ` Paul E. McKenney 2013-10-31 15:07 ` Paul E. McKenney 2013-10-31 15:19 ` Peter Zijlstra 2013-10-31 15:19 ` Peter Zijlstra 2013-11-01 9:28 ` Paul E. McKenney 2013-11-01 9:28 ` Paul E. McKenney 2013-11-01 10:30 ` Peter Zijlstra 2013-11-01 10:30 ` Peter Zijlstra 2013-11-02 15:20 ` Paul E. McKenney 2013-11-02 15:20 ` Paul E. McKenney 2013-11-04 9:07 ` Peter Zijlstra 2013-11-04 9:07 ` Peter Zijlstra 2013-11-04 10:00 ` Paul E. McKenney 2013-11-04 10:00 ` Paul E. McKenney 2013-10-31 9:59 ` Victor Kaplansky 2013-10-31 9:59 ` Victor Kaplansky 2013-10-31 12:28 ` David Laight 2013-10-31 12:28 ` David Laight 2013-10-31 12:55 ` Victor Kaplansky 2013-10-31 12:55 ` Victor Kaplansky 2013-10-31 15:25 ` Paul E. McKenney 2013-10-31 15:25 ` Paul E. McKenney 2013-11-01 16:06 ` Victor Kaplansky 2013-11-01 16:06 ` Victor Kaplansky 2013-11-01 16:25 ` David Laight 2013-11-01 16:25 ` David Laight 2013-11-01 16:30 ` Victor Kaplansky 2013-11-01 16:30 ` Victor Kaplansky 2013-11-03 20:57 ` Benjamin Herrenschmidt 2013-11-03 20:57 ` Benjamin Herrenschmidt 2013-11-02 15:46 ` Paul E. McKenney 2013-11-02 15:46 ` Paul E. McKenney 2013-10-28 19:09 ` Oleg Nesterov 2013-10-28 19:09 ` Oleg Nesterov 2013-10-29 14:06 ` [tip:perf/urgent] perf: Fix perf ring buffer memory ordering tip-bot for Peter Zijlstra
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