From: <Tudor.Ambarus@microchip.com> To: <john.garry@huawei.com>, <vigneshr@ti.com>, <richard@nod.at>, <miquel.raynal@bootlin.com> Cc: <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <Tudor.Ambarus@microchip.com> Subject: [PATCH] mtd: spi-nor: Fix the write Status Register on micron flashes Date: Tue, 3 Dec 2019 14:16:40 +0000 [thread overview] Message-ID: <20191203141625.13839-1-tudor.ambarus@microchip.com> (raw) In-Reply-To: <00cf6eab-9798-b0e9-e4a2-5b2f8374b698@huawei.com> From: Tudor Ambarus <tudor.ambarus@microchip.com> Micron flashes do not support 16 bit writes on the Status Register. According to micron datasheets, when using the Write Status Register (01h) command, the chip select should be driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. If CS is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. This fixes the lock operations on micron flashes. Reported-by: John Garry <john.garry@huawei.com> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index f1490c7b5cb9..7e41493f69d8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -4607,6 +4607,7 @@ static void sst_set_default_init(struct spi_nor *nor) static void st_micron_set_default_init(struct spi_nor *nor) { nor->flags |= SNOR_F_HAS_LOCK; + nor->flags &= ~SNOR_F_HAS_16BIT_SR; nor->params.quad_enable = NULL; nor->params.set_4byte = st_micron_set_4byte; } -- 2.14.5
WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com> To: <john.garry@huawei.com>, <vigneshr@ti.com>, <richard@nod.at>, <miquel.raynal@bootlin.com> Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor.Ambarus@microchip.com Subject: [PATCH] mtd: spi-nor: Fix the write Status Register on micron flashes Date: Tue, 3 Dec 2019 14:16:40 +0000 [thread overview] Message-ID: <20191203141625.13839-1-tudor.ambarus@microchip.com> (raw) In-Reply-To: <00cf6eab-9798-b0e9-e4a2-5b2f8374b698@huawei.com> From: Tudor Ambarus <tudor.ambarus@microchip.com> Micron flashes do not support 16 bit writes on the Status Register. According to micron datasheets, when using the Write Status Register (01h) command, the chip select should be driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. If CS is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. This fixes the lock operations on micron flashes. Reported-by: John Garry <john.garry@huawei.com> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index f1490c7b5cb9..7e41493f69d8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -4607,6 +4607,7 @@ static void sst_set_default_init(struct spi_nor *nor) static void st_micron_set_default_init(struct spi_nor *nor) { nor->flags |= SNOR_F_HAS_LOCK; + nor->flags &= ~SNOR_F_HAS_16BIT_SR; nor->params.quad_enable = NULL; nor->params.set_4byte = st_micron_set_4byte; } -- 2.14.5 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2019-12-03 14:16 UTC|newest] Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-02 17:28 flash_lock issue for n25q 128mb spi nor part John Garry 2019-12-03 9:45 ` Tudor.Ambarus 2019-12-03 10:31 ` John Garry 2019-12-03 11:07 ` Tudor.Ambarus 2019-12-03 11:44 ` John Garry 2019-12-03 12:05 ` Tudor.Ambarus 2019-12-03 12:27 ` Tudor.Ambarus 2019-12-03 12:35 ` John Garry 2019-12-03 13:57 ` John Garry 2019-12-03 14:44 ` Tudor.Ambarus 2019-12-03 15:29 ` John Garry 2019-12-04 11:10 ` John Garry 2019-12-16 18:09 ` Tudor.Ambarus 2019-12-17 8:57 ` Vignesh Raghavendra 2019-12-17 10:09 ` John Garry 2020-01-09 10:36 ` John Garry 2020-01-10 11:51 ` Tudor.Ambarus 2020-01-10 11:56 ` John Garry 2020-01-15 9:28 ` John Garry 2020-03-09 10:15 ` [RESEND PATCH 1/2] mtd: spi-nor: Clear WEL bit when erase or program errors occur Tudor.Ambarus 2020-03-09 10:15 ` [RESEND PATCH 2/2] mtd: spi-nor: Fix description of the sr_ready() return value Tudor.Ambarus 2020-03-09 15:04 ` [RESEND PATCH 1/2] mtd: spi-nor: Clear WEL bit when erase or program errors occur John Garry 2020-03-23 17:58 ` Tudor.Ambarus 2019-12-03 14:16 ` Tudor.Ambarus [this message] 2019-12-03 14:16 ` [PATCH] mtd: spi-nor: Fix the write Status Register on micron flashes Tudor.Ambarus 2019-12-03 14:50 ` [PATCH v2] mtd: spi-nor: Fix the writing of the " Tudor.Ambarus 2019-12-03 14:50 ` Tudor.Ambarus 2019-12-04 10:18 ` John Garry 2019-12-04 10:18 ` John Garry 2020-01-09 19:14 ` Miquel Raynal 2020-01-09 19:14 ` Miquel Raynal
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