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From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
To: u-boot@lists.denx.de
Subject: [v2, 05/16] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
Date: Thu,  1 Oct 2020 02:16:03 -0700	[thread overview]
Message-ID: <20201001091614.184612-6-elly.siew.chin.lim@intel.com> (raw)
In-Reply-To: <20201001091614.184612-1-elly.siew.chin.lim@intel.com>

From: Chee Hong Ang <chee.hong.ang@intel.com>

Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/Makefile              |  2 +
 arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 418f543b20..c63162a5c6 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -29,6 +29,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
 obj-y	+= mmu-arm64_s10.o
@@ -41,6 +42,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y	+= clock_manager_agilex.o
+obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
 obj-y	+= mmu-arm64_s10.o
diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
new file mode 100644
index 0000000000..612ea8a037
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+wait_for_atf:
+	ldr	x4, =CPU_RELEASE_ADDR
+	ldr	x5, [x4]
+	cbz	x5, slave_wait_atf
+	br	x5
+slave_wait_atf:
+	branch_if_slave x0, wait_for_atf
+#else
+	branch_if_slave x0, 1f
+#endif
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+	branch_if_master x0, x1, 2f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent slaves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All slaves will enter EL2 and optionally EL1.
+	 */
+	adr	x4, lowlevel_in_el2
+	ldr	x5, =ES_TO_AARCH64
+	bl	armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	adr	x4, lowlevel_in_el1
+	ldr	x5, =ES_TO_AARCH64
+	bl	armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
-- 
2.13.0

  parent reply	other threads:[~2020-10-01  9:16 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-01  9:15 [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
2020-10-01  9:15 ` [v2, 01/16] arm: socfpga: soc64: Remove CONFIG_OF_EMBED Siew Chin Lim
2020-10-01  9:16 ` [v2, 02/16] arm: socfpga: soc64: Add FIT generator script for pack itb with ATF Siew Chin Lim
2020-10-01  9:16 ` [v2, 03/16] arm: socfpga: Add function for checking description from FIT image Siew Chin Lim
2020-10-01  9:16 ` [v2, 04/16] arm: socfpga: soc64: Load FIT image with ATF support Siew Chin Lim
2020-10-01  9:16 ` Siew Chin Lim [this message]
2020-10-01  9:16 ` [v2, 06/16] arm: socfpga: Disable "spin-table" method for booting Linux Siew Chin Lim
2020-10-01  9:16 ` [v2, 07/16] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) Siew Chin Lim
2020-10-01  9:16 ` [v2, 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services Siew Chin Lim
2020-10-01  9:16 ` [v2, 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver Siew Chin Lim
2020-10-01  9:16 ` [v2, 10/16] net: designware: socfpga: Add ATF support for MAC driver Siew Chin Lim
2020-10-01  9:16 ` [v2, 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver Siew Chin Lim
2020-10-01  9:16 ` [v2, 12/16] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver Siew Chin Lim
2020-10-01  9:16 ` [v2, 13/16] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() Siew Chin Lim
2020-10-01  9:16 ` [v2, 14/16] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM Siew Chin Lim
2020-10-01  9:16 ` [v2, 15/16] arm: socfpga: soc64: Skip handoff data access in SSBL Siew Chin Lim
2020-10-01  9:16 ` [v2, 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim
2020-10-01 16:52 ` [v2, 00/16] Enable ARM Trusted Firmware for U-Boot Michal Simek
2020-10-01 18:37   ` Simon Glass
2020-10-01 18:48     ` Marek Vasut
2020-10-01 20:33       ` Tom Rini
2020-10-01 21:46       ` Simon Glass

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