* [igt-dev] [PATCH i-g-t v3 01/23] lib/igt_list: igt_hlist implementation.
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 02/23] lib/igt_map: Introduce igt_map Zbigniew Kempczyński
` (25 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Double linked lists with a single pointer list head implementation,
based on similar in the kernel.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_list.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++
lib/igt_list.h | 50 +++++++++++++++++++++++++++++++++--
2 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/lib/igt_list.c b/lib/igt_list.c
index 5e30b19b..60eb571c 100644
--- a/lib/igt_list.c
+++ b/lib/igt_list.c
@@ -75,3 +75,74 @@ bool igt_list_empty(const struct igt_list_head *head)
{
return head->next == head;
}
+
+void IGT_INIT_HLIST_NODE(struct igt_hlist_node *h)
+{
+ h->next = NULL;
+ h->pprev = NULL;
+}
+
+int igt_hlist_unhashed(const struct igt_hlist_node *h)
+{
+ return !h->pprev;
+}
+
+int igt_hlist_empty(const struct igt_hlist_head *h)
+{
+ return !h->first;
+}
+
+static void __igt_hlist_del(struct igt_hlist_node *n)
+{
+ struct igt_hlist_node *next = n->next;
+ struct igt_hlist_node **pprev = n->pprev;
+
+ *pprev = next;
+ if (next)
+ next->pprev = pprev;
+}
+
+void igt_hlist_del(struct igt_hlist_node *n)
+{
+ __igt_hlist_del(n);
+ n->next = NULL;
+ n->pprev = NULL;
+}
+
+void igt_hlist_del_init(struct igt_hlist_node *n)
+{
+ if (!igt_hlist_unhashed(n)) {
+ __igt_hlist_del(n);
+ IGT_INIT_HLIST_NODE(n);
+ }
+}
+
+void igt_hlist_add_head(struct igt_hlist_node *n, struct igt_hlist_head *h)
+{
+ struct igt_hlist_node *first = h->first;
+
+ n->next = first;
+ if (first)
+ first->pprev = &n->next;
+ h->first = n;
+ n->pprev = &h->first;
+}
+
+/* next must be != NULL */
+void igt_hlist_add_before(struct igt_hlist_node *n, struct igt_hlist_node *next)
+{
+ n->pprev = next->pprev;
+ n->next = next;
+ next->pprev = &n->next;
+ *(n->pprev) = n;
+}
+
+void igt_hlist_add_behind(struct igt_hlist_node *n, struct igt_hlist_node *prev)
+{
+ n->next = prev->next;
+ prev->next = n;
+ n->pprev = &prev->next;
+
+ if (n->next)
+ n->next->pprev = &n->next;
+}
diff --git a/lib/igt_list.h b/lib/igt_list.h
index dbf5f802..d910fde7 100644
--- a/lib/igt_list.h
+++ b/lib/igt_list.h
@@ -40,6 +40,10 @@
* igt_list is a doubly-linked list where an instance of igt_list_head is a
* head sentinel and has to be initialized.
*
+ * igt_hist is also an double linked lists, but with a single pointer list head.
+ * Mostly useful for hash tables where the two pointer list head is
+ * too wasteful. You lose the ability to access the tail in O(1).
+ *
* Example usage:
*
* |[<!-- language="C" -->
@@ -71,6 +75,13 @@ struct igt_list_head {
struct igt_list_head *next;
};
+struct igt_hlist_head {
+ struct igt_hlist_node *first;
+};
+
+struct igt_hlist_node {
+ struct igt_hlist_node *next, **pprev;
+};
void IGT_INIT_LIST_HEAD(struct igt_list_head *head);
void igt_list_add(struct igt_list_head *elem, struct igt_list_head *head);
@@ -80,6 +91,17 @@ void igt_list_move_tail(struct igt_list_head *elem, struct igt_list_head *list);
int igt_list_length(const struct igt_list_head *head);
bool igt_list_empty(const struct igt_list_head *head);
+void IGT_INIT_HLIST_NODE(struct igt_hlist_node *h);
+int igt_hlist_unhashed(const struct igt_hlist_node *h);
+int igt_hlist_empty(const struct igt_hlist_head *h);
+void igt_hlist_del(struct igt_hlist_node *n);
+void igt_hlist_del_init(struct igt_hlist_node *n);
+void igt_hlist_add_head(struct igt_hlist_node *n, struct igt_hlist_head *h);
+void igt_hlist_add_before(struct igt_hlist_node *n,
+ struct igt_hlist_node *next);
+void igt_hlist_add_behind(struct igt_hlist_node *n,
+ struct igt_hlist_node *prev);
+
#define igt_container_of(ptr, sample, member) \
(__typeof__(sample))((char *)(ptr) - \
offsetof(__typeof__(*sample), member))
@@ -95,9 +117,10 @@ bool igt_list_empty(const struct igt_list_head *head);
* Safe against removel of the *current* list element. To achive this it
* requires an extra helper variable `tmp` with the same type as `pos`.
*/
-#define igt_list_for_each_entry_safe(pos, tmp, head, member) \
+
+#define igt_list_for_each_entry_safe(pos, tmp, head, member) \
for (pos = igt_container_of((head)->next, pos, member), \
- tmp = igt_container_of((pos)->member.next, tmp, member); \
+ tmp = igt_container_of((pos)->member.next, tmp, member); \
&pos->member != (head); \
pos = tmp, \
tmp = igt_container_of((pos)->member.next, tmp, member))
@@ -107,6 +130,27 @@ bool igt_list_empty(const struct igt_list_head *head);
&pos->member != (head); \
pos = igt_container_of((pos)->member.prev, pos, member))
+#define igt_list_for_each_entry_safe_reverse(pos, tmp, head, member) \
+ for (pos = igt_container_of((head)->prev, pos, member), \
+ tmp = igt_container_of((pos)->member.prev, tmp, member); \
+ &pos->member != (head); \
+ pos = tmp, \
+ tmp = igt_container_of((pos)->member.prev, tmp, member))
+
+#define igt_hlist_entry_safe(ptr, sample, member) \
+ ({ typeof(ptr) ____ptr = (ptr); \
+ ____ptr ? igt_container_of(____ptr, sample, member) : NULL; \
+ })
+
+#define igt_hlist_for_each_entry(pos, head, member) \
+ for (pos = igt_hlist_entry_safe((head)->first, pos, member); \
+ pos; \
+ pos = igt_hlist_entry_safe((pos)->member.next, pos, member))
+
+#define igt_hlist_for_each_entry_safe(pos, n, head, member) \
+ for (pos = igt_hlist_entry_safe((head)->first, pos, member); \
+ pos && ({ n = pos->member.next; 1; }); \
+ pos = igt_hlist_entry_safe(n, pos, member))
/* IGT custom helpers */
@@ -126,4 +170,6 @@ bool igt_list_empty(const struct igt_list_head *head);
#define igt_list_last_entry(head, type, member) \
igt_container_of((head)->prev, (type), member)
+#define IGT_INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
+
#endif /* IGT_LIST_H */
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 02/23] lib/igt_map: Introduce igt_map
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 01/23] lib/igt_list: igt_hlist implementation Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 03/23] lib/igt_core: Track child process pid and tid Zbigniew Kempczyński
` (24 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Implementation of generic, non-thread safe, dynamic size hash map.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
.../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
lib/Makefile.sources | 2 +
lib/igt_map.c | 150 ++++++++++++++++++
lib/igt_map.h | 121 ++++++++++++++
lib/meson.build | 1 +
5 files changed, 275 insertions(+)
create mode 100644 lib/igt_map.c
create mode 100644 lib/igt_map.h
diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
index 9c9aa8f1..bf5ac542 100644
--- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
+++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
@@ -33,6 +33,7 @@
<xi:include href="xml/igt_kmod.xml"/>
<xi:include href="xml/igt_kms.xml"/>
<xi:include href="xml/igt_list.xml"/>
+ <xi:include href="xml/igt_map.xml"/>
<xi:include href="xml/igt_pm.xml"/>
<xi:include href="xml/igt_primes.xml"/>
<xi:include href="xml/igt_rand.xml"/>
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 67b38645..27019a77 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -47,6 +47,8 @@ lib_source_list = \
igt_infoframe.h \
igt_list.c \
igt_list.h \
+ igt_map.c \
+ igt_map.h \
igt_matrix.c \
igt_matrix.h \
igt_params.c \
diff --git a/lib/igt_map.c b/lib/igt_map.c
new file mode 100644
index 00000000..aa330dbf
--- /dev/null
+++ b/lib/igt_map.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <sys/ioctl.h>
+#include <stdlib.h>
+#include "igt_map.h"
+#include "igt.h"
+#include "igt_x86.h"
+
+#define MIN_CAPACITY_BITS 2
+
+static bool igt_map_filled(struct igt_map *map)
+{
+ return map->capacity_bits == 0 ||
+ (IGT_MAP_CAPACITY(map) * 4 / 5 < map->size);
+}
+
+static void igt_map_extend(struct igt_map *map)
+{
+ struct igt_hlist_head *new_heads;
+ struct igt_map_entry *pos;
+ struct igt_hlist_node *tmp;
+ uint32_t new_bits = map->capacity_bits + 1;
+ int i;
+
+ new_heads = calloc(1ULL << new_bits,
+ sizeof(struct igt_hlist_head));
+ igt_assert(new_heads);
+
+ igt_map_for_each_safe(map, i, tmp, pos)
+ igt_hlist_add_head(&pos->link, &new_heads[map->hash_fn(pos->key, new_bits)]);
+
+ free(map->heads);
+ map->capacity_bits++;
+
+ map->heads = new_heads;
+}
+
+static bool equal_4bytes(const void *key1, const void *key2)
+{
+ const uint32_t *k1 = key1, *k2 = key2;
+ return *k1 == *k2;
+}
+
+/* 2^63 + 2^61 - 2^57 + 2^54 - 2^51 - 2^18 + 1 */
+#define GOLDEN_RATIO_PRIME_64 0x9e37fffffffc0001UL
+
+static inline uint64_t hash_64_4bytes(const void *val, unsigned int bits)
+{
+ uint64_t hash = *(uint32_t *)val;
+
+ hash = hash * GOLDEN_RATIO_PRIME_64;
+ /* High bits are more random, so use them. */
+ return hash >> (64 - bits);
+}
+
+void igt_map_init(struct igt_map *map, igt_map_equal_fn eq_fn,
+ igt_map_hash_fn hash_fn, uint32_t initial_bits)
+{
+ map->equal_fn = eq_fn == NULL ? equal_4bytes : eq_fn;
+ map->hash_fn = hash_fn == NULL ? hash_64_4bytes : hash_fn;
+ map->capacity_bits = initial_bits > 0 ? initial_bits
+ : MIN_CAPACITY_BITS;
+ map->heads = calloc(IGT_MAP_CAPACITY(map),
+ sizeof(struct igt_hlist_head));
+
+ igt_assert(map->heads);
+ map->size = 0;
+}
+
+void igt_map_add(struct igt_map *map, const void *key, void *value)
+{
+ struct igt_map_entry *entry;
+
+ if (igt_map_filled(map))
+ igt_map_extend(map);
+
+ entry = calloc(1, sizeof(struct igt_map_entry));
+ entry->value = value;
+ entry->key = key;
+ igt_hlist_add_head(&entry->link,
+ &map->heads[map->hash_fn(key, map->capacity_bits)]);
+ map->size++;
+}
+
+void *igt_map_del(struct igt_map *map, const void *key)
+{
+ struct igt_map_entry *pos;
+ struct igt_hlist_node *tmp;
+ void *val = NULL;
+
+ igt_map_for_each_possible_safe(map, pos, tmp, key) {
+ if (map->equal_fn(pos->key, key)) {
+ igt_hlist_del(&pos->link);
+ val = pos->value;
+ free(pos);
+ }
+ }
+ return val;
+}
+
+void *igt_map_find(struct igt_map *map, const void *key)
+{
+ struct igt_map_entry *pos = NULL;
+
+ igt_map_for_each_possible(map, pos, key)
+ if (pos && map->equal_fn(pos->key, key))
+ break;
+
+ return pos ? pos->value : NULL;
+}
+
+void igt_map_free(struct igt_map *map)
+{
+ struct igt_map_entry *pos;
+ struct igt_hlist_node *tmp;
+ int i;
+
+ igt_map_for_each_safe(map, i, tmp, pos) {
+ igt_hlist_del(&pos->link);
+ free(pos);
+ }
+
+ free(map->heads);
+}
+
+bool igt_map_empty(struct igt_map *map)
+{
+ return !!map->size;
+}
diff --git a/lib/igt_map.h b/lib/igt_map.h
new file mode 100644
index 00000000..5c767afa
--- /dev/null
+++ b/lib/igt_map.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef IGT_MAP_H
+#define IGT_MAP_H
+
+#include <stdint.h>
+#include "igt_list.h"
+
+/**
+ * SECTION:igt_map
+ * @short_description: a dynamic sized hashmap implementation
+ * @title: IGT Map
+ * @include: igt_map.h
+ *
+ * igt_map is a dynamic sized, non-thread-safe implementation of a hashmap.
+ * This map grows exponentially when it's over 80% filled. The structure allows
+ * indexing records by any key through the hash and equal functions.
+ * By default, hashmap compares and hashes the first four bytes of a key.
+ *
+ * Example usage:
+ *
+ * |[<!-- language="C" -->
+ * struct igt_map *map;
+ *
+ * struct record {
+ * int foo;
+ * uint32_t unique_identifier;
+ * };
+ *
+ * struct record r1, r2, *r_ptr;
+ *
+ * map = malloc(sizeof(*map));
+ * igt_map_init(map, NULL, NULL, 4); // initiaize the map with size (1 << 4)
+ * igt_map_add(map, &r1.unique_identifier, &r1);
+ * igt_map_add(map, &r2.unique_identifier, &r2);
+ *
+ * struct igt_map_entry *pos; int i;
+ * igt_map_for_each(map, i, pos) {
+ * r_ptr = pos->value;
+ * printf("key: %u, foo: %d\n", *(uint32_t*) pos->key, r_ptr->foo);
+ * }
+ *
+ * uint32_t key = r1.unique_identifier;
+ * r_ptr = igt_map_find(map, &key); // get r1
+ *
+ * r_ptr = igt_map_del(map, &r2.unique_identifier);
+ * if (r_ptr)
+ * printf("record with key %u deleted\n", r_ptr->unique_identifier);
+ *
+ * igt_map_free(map);
+ * free(map);
+ * ]|
+ */
+
+typedef bool (*igt_map_equal_fn)(const void *key1, const void *key2);
+typedef uint64_t (*igt_map_hash_fn)(const void *val, unsigned int bits);
+struct igt_map {
+ uint32_t size;
+ uint32_t capacity_bits;
+ igt_map_equal_fn equal_fn;
+ igt_map_hash_fn hash_fn;
+ struct igt_hlist_head *heads;
+};
+
+struct igt_map_entry {
+ const void *key;
+ void *value;
+ struct igt_hlist_node link;
+};
+
+void igt_map_init(struct igt_map *map, igt_map_equal_fn eq_fn,
+ igt_map_hash_fn hash_fn, uint32_t initial_bits);
+void igt_map_add(struct igt_map *map, const void *key, void *value);
+void *igt_map_del(struct igt_map *map, const void *key);
+void *igt_map_find(struct igt_map *map, const void *key);
+void igt_map_free(struct igt_map *map);
+bool igt_map_empty(struct igt_map *map);
+
+#define IGT_MAP_CAPACITY(map) (1ULL << map->capacity_bits)
+
+#define igt_map_for_each_safe(map, bkt, tmp, obj) \
+ for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < IGT_MAP_CAPACITY(map); \
+ (bkt)++)\
+ igt_hlist_for_each_entry_safe(obj, tmp, &map->heads[bkt], link)
+
+#define igt_map_for_each(map, bkt, obj) \
+ for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < IGT_MAP_CAPACITY(map); \
+ (bkt)++)\
+ igt_hlist_for_each_entry(obj, &map->heads[bkt], link)
+
+#define igt_map_for_each_possible(map, obj, key) \
+ igt_hlist_for_each_entry(obj, \
+ &map->heads[map->hash_fn(key, map->capacity_bits)], link)
+
+#define igt_map_for_each_possible_safe(map, obj, tmp, key) \
+ igt_hlist_for_each_entry_safe(obj, tmp, \
+ &map->heads[map->hash_fn(key, map->capacity_bits)], link)
+
+#endif /* IGT_MAP_H */
diff --git a/lib/meson.build b/lib/meson.build
index 090a10cd..484d3c7b 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -59,6 +59,7 @@ lib_sources = [
'igt_core.c',
'igt_draw.c',
'igt_list.c',
+ 'igt_map.c',
'igt_pm.c',
'igt_dummyload.c',
'uwildmat/uwildmat.c',
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 03/23] lib/igt_core: Track child process pid and tid
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 01/23] lib/igt_list: igt_hlist implementation Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 02/23] lib/igt_map: Introduce igt_map Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 04/23] lib/intel_allocator_simple: Add simple allocator Zbigniew Kempczyński
` (23 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Petri Latvala, Chris Wilson
Introduce variables which can decrease number of getpid()/gettid()
calls, especially for allocator which must be aware of method
acquiring addresses.
When child is spawned using igt_fork() we can control its initialization
and prepare child_pid implicitly. Tracking child_tid requires our
intervention in the code and do something like this:
if (child_tid == -1)
child_tid = gettid()
Variable was created for using in TLS so each thread is created
with variable set to -1. This will give each thread it's own "copy"
and there's no risk to use other thread tid. For each forked child
we reassign -1 to child_tid to avoid using already set variable.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
---
lib/igt_core.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index b358173f..1f725d00 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -58,6 +58,7 @@
#include <glib.h>
#include "drmtest.h"
+#include "intel_allocator.h"
#include "intel_chipset.h"
#include "intel_io.h"
#include "igt_debugfs.h"
@@ -306,6 +307,10 @@ int num_test_children;
int test_children_sz;
bool test_child;
+/* For allocator purposes */
+pid_t child_pid = -1;
+__thread pid_t child_tid = -1;
+
enum {
/*
* Let the first values be used by individual tests so options don't
@@ -2303,6 +2308,8 @@ bool __igt_fork(void)
case 0:
test_child = true;
pthread_mutex_init(&print_mutex, NULL);
+ child_pid = getpid();
+ child_tid = -1;
exit_handler_count = 0;
reset_helper_process_list();
oom_adjust_for_doom();
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 04/23] lib/intel_allocator_simple: Add simple allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (2 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 03/23] lib/igt_core: Track child process pid and tid Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 05/23] lib/intel_allocator_random: Add random allocator Zbigniew Kempczyński
` (22 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Simple allocator borrowed from Mesa adopted for IGT use.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_allocator_simple.c | 730 +++++++++++++++++++++++++++++++++++
1 file changed, 730 insertions(+)
create mode 100644 lib/intel_allocator_simple.c
diff --git a/lib/intel_allocator_simple.c b/lib/intel_allocator_simple.c
new file mode 100644
index 00000000..1f52db3f
--- /dev/null
+++ b/lib/intel_allocator_simple.c
@@ -0,0 +1,730 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <sys/ioctl.h>
+#include <stdlib.h>
+#include "igt.h"
+#include "igt_x86.h"
+#include "intel_allocator.h"
+#include "intel_bufops.h"
+#include "igt_map.h"
+
+/* Avoid compilation warning */
+struct intel_allocator *intel_allocator_simple_create(int fd, uint32_t ctx);
+
+struct simple_vma_heap {
+ struct igt_list_head holes;
+
+ /* If true, simple_vma_heap_alloc will prefer high addresses
+ *
+ * Default is true.
+ */
+ bool alloc_high;
+};
+
+struct simple_vma_hole {
+ struct igt_list_head link;
+ uint64_t offset;
+ uint64_t size;
+};
+
+struct intel_allocator_simple {
+ struct igt_map objects;
+ struct igt_map reserved;
+ struct simple_vma_heap heap;
+
+ uint64_t gtt_size;
+ uint64_t bias;
+ uint64_t start;
+ uint64_t end;
+
+ /* statistics */
+ uint64_t total_size;
+ uint64_t allocated_size;
+ uint64_t allocated_objects;
+ uint64_t reserved_size;
+ uint64_t reserved_areas;
+};
+
+struct intel_allocator_record {
+ uint32_t handle;
+ uint64_t offset;
+ uint64_t size;
+};
+
+#define simple_vma_foreach_hole(_hole, _heap) \
+ igt_list_for_each_entry(_hole, &(_heap)->holes, link)
+
+#define simple_vma_foreach_hole_safe(_hole, _heap, _tmp) \
+ igt_list_for_each_entry_safe(_hole, _tmp, &(_heap)->holes, link)
+
+#define simple_vma_foreach_hole_safe_rev(_hole, _heap, _tmp) \
+ igt_list_for_each_entry_safe_reverse(_hole, _tmp, &(_heap)->holes, link)
+
+#define DECANONICAL(offset) (offset & ((1ull << 48) - 1))
+
+static uint64_t get_bias(int fd)
+{
+ (void) fd;
+
+ return 256 << 10;
+}
+
+static void simple_vma_heap_validate(struct simple_vma_heap *heap)
+{
+ uint64_t prev_offset = 0;
+ struct simple_vma_hole *hole;
+
+ simple_vma_foreach_hole(hole, heap) {
+ igt_assert(hole->size > 0);
+
+ if (&hole->link == heap->holes.next) {
+ /* This must be the top-most hole. Assert that,
+ * if it overflows, it overflows to 0, i.e. 2^64.
+ */
+ igt_assert(hole->size + hole->offset == 0 ||
+ hole->size + hole->offset > hole->offset);
+ } else {
+ /* This is not the top-most hole so it must not overflow and,
+ * in fact, must be strictly lower than the top-most hole. If
+ * hole->size + hole->offset == prev_offset, then we failed to
+ * join holes during a simple_vma_heap_free.
+ */
+ igt_assert(hole->size + hole->offset > hole->offset &&
+ hole->size + hole->offset < prev_offset);
+ }
+ prev_offset = hole->offset;
+ }
+}
+
+
+static void simple_vma_heap_free(struct simple_vma_heap *heap,
+ uint64_t offset, uint64_t size)
+{
+ struct simple_vma_hole *high_hole = NULL, *low_hole = NULL, *hole;
+ bool high_adjacent, low_adjacent;
+
+ /* Freeing something with a size of 0 is not valid. */
+ igt_assert(size > 0);
+
+ /* It's possible for offset + size to wrap around if we touch the top of
+ * the 64-bit address space, but we cannot go any higher than 2^64.
+ */
+ igt_assert(offset + size == 0 || offset + size > offset);
+
+ simple_vma_heap_validate(heap);
+
+ /* Find immediately higher and lower holes if they exist. */
+ simple_vma_foreach_hole(hole, heap) {
+ if (hole->offset <= offset) {
+ low_hole = hole;
+ break;
+ }
+ high_hole = hole;
+ }
+
+ if (high_hole)
+ igt_assert(offset + size <= high_hole->offset);
+ high_adjacent = high_hole && offset + size == high_hole->offset;
+
+ if (low_hole) {
+ igt_assert(low_hole->offset + low_hole->size > low_hole->offset);
+ igt_assert(low_hole->offset + low_hole->size <= offset);
+ }
+ low_adjacent = low_hole && low_hole->offset + low_hole->size == offset;
+
+ if (low_adjacent && high_adjacent) {
+ /* Merge the two holes */
+ low_hole->size += size + high_hole->size;
+ igt_list_del(&high_hole->link);
+ free(high_hole);
+ } else if (low_adjacent) {
+ /* Merge into the low hole */
+ low_hole->size += size;
+ } else if (high_adjacent) {
+ /* Merge into the high hole */
+ high_hole->offset = offset;
+ high_hole->size += size;
+ } else {
+ /* Neither hole is adjacent; make a new one */
+ hole = calloc(1, sizeof(*hole));
+ igt_assert(hole);
+
+ hole->offset = offset;
+ hole->size = size;
+ /* Add it after the high hole so we maintain high-to-low
+ * ordering
+ */
+ if (high_hole)
+ igt_list_add(&hole->link, &high_hole->link);
+ else
+ igt_list_add(&hole->link, &heap->holes);
+ }
+
+ simple_vma_heap_validate(heap);
+}
+
+static void simple_vma_heap_init(struct simple_vma_heap *heap,
+ uint64_t start, uint64_t size)
+{
+ IGT_INIT_LIST_HEAD(&heap->holes);
+ simple_vma_heap_free(heap, start, size);
+
+ /* Default to using high addresses */
+ heap->alloc_high = true;
+}
+
+static void simple_vma_heap_finish(struct simple_vma_heap *heap)
+{
+ struct simple_vma_hole *hole, *tmp;
+
+ simple_vma_foreach_hole_safe(hole, heap, tmp)
+ free(hole);
+}
+
+static void simple_vma_hole_alloc(struct simple_vma_hole *hole,
+ uint64_t offset, uint64_t size)
+{
+ struct simple_vma_hole *high_hole;
+ uint64_t waste;
+
+ igt_assert(hole->offset <= offset);
+ igt_assert(hole->size >= offset - hole->offset + size);
+
+ if (offset == hole->offset && size == hole->size) {
+ /* Just get rid of the hole. */
+ igt_list_del(&hole->link);
+ free(hole);
+ return;
+ }
+
+ igt_assert(offset - hole->offset <= hole->size - size);
+ waste = (hole->size - size) - (offset - hole->offset);
+ if (waste == 0) {
+ /* We allocated at the top-> Shrink the hole down. */
+ hole->size -= size;
+ return;
+ }
+
+ if (offset == hole->offset) {
+ /* We allocated at the bottom. Shrink the hole up-> */
+ hole->offset += size;
+ hole->size -= size;
+ return;
+ }
+
+ /* We allocated in the middle. We need to split the old hole into two
+ * holes, one high and one low.
+ */
+ high_hole = calloc(1, sizeof(*hole));
+ igt_assert(high_hole);
+
+ high_hole->offset = offset + size;
+ high_hole->size = waste;
+
+ /* Adjust the hole to be the amount of space left at he bottom of the
+ * original hole.
+ */
+ hole->size = offset - hole->offset;
+
+ /* Place the new hole before the old hole so that the list is in order
+ * from high to low.
+ */
+ igt_list_add_tail(&high_hole->link, &hole->link);
+}
+
+static bool simple_vma_heap_alloc(struct simple_vma_heap *heap,
+ uint64_t *offset, uint64_t size,
+ uint64_t alignment)
+{
+ struct simple_vma_hole *hole, *tmp;
+ uint64_t misalign;
+
+ /* The caller is expected to reject zero-size allocations */
+ igt_assert(size > 0);
+ igt_assert(alignment > 0);
+
+ simple_vma_heap_validate(heap);
+
+ if (heap->alloc_high) {
+ simple_vma_foreach_hole_safe(hole, heap, tmp) {
+ if (size > hole->size)
+ continue;
+
+ /* Compute the offset as the highest address where a chunk of the
+ * given size can be without going over the top of the hole.
+ *
+ * This calculation is known to not overflow because we know that
+ * hole->size + hole->offset can only overflow to 0 and size > 0.
+ */
+ *offset = (hole->size - size) + hole->offset;
+
+ /* Align the offset. We align down and not up because we are
+ *
+ * allocating from the top of the hole and not the bottom.
+ */
+ *offset = (*offset / alignment) * alignment;
+
+ if (*offset < hole->offset)
+ continue;
+
+ simple_vma_hole_alloc(hole, *offset, size);
+ simple_vma_heap_validate(heap);
+ return true;
+ }
+ } else {
+ simple_vma_foreach_hole_safe_rev(hole, heap, tmp) {
+ if (size > hole->size)
+ continue;
+
+ *offset = hole->offset;
+
+ /* Align the offset */
+ misalign = *offset % alignment;
+ if (misalign) {
+ uint64_t pad = alignment - misalign;
+
+ if (pad > hole->size - size)
+ continue;
+
+ *offset += pad;
+ }
+
+ simple_vma_hole_alloc(hole, *offset, size);
+ simple_vma_heap_validate(heap);
+ return true;
+ }
+ }
+
+ /* Failed to allocate */
+ return false;
+}
+
+static void intel_allocator_simple_get_address_range(struct intel_allocator *ial,
+ uint64_t *startp,
+ uint64_t *endp)
+{
+ struct intel_allocator_simple *ials = ial->priv;
+
+ if (startp)
+ *startp = ials->start;
+
+ if (endp)
+ *endp = ials->end;
+}
+
+static bool simple_vma_heap_alloc_addr(struct intel_allocator_simple *ials,
+ uint64_t offset, uint64_t size)
+{
+ struct simple_vma_heap *heap = &ials->heap;
+ struct simple_vma_hole *hole, *tmp;
+ /* Allocating something with a size of 0 is not valid. */
+ igt_assert(size > 0);
+
+ /* It's possible for offset + size to wrap around if we touch the top of
+ * the 64-bit address space, but we cannot go any higher than 2^64.
+ */
+ igt_assert(offset + size == 0 || offset + size > offset);
+
+ /* Find the hole if one exists. */
+ simple_vma_foreach_hole_safe(hole, heap, tmp) {
+ if (hole->offset > offset)
+ continue;
+
+ /* Holes are ordered high-to-low so the first hole we find with
+ * hole->offset <= is our hole. If it's not big enough to contain the
+ * requested range, then the allocation fails.
+ */
+ igt_assert(hole->offset <= offset);
+ if (hole->size < offset - hole->offset + size)
+ return false;
+
+ simple_vma_hole_alloc(hole, offset, size);
+ return true;
+ }
+
+ /* We didn't find a suitable hole */
+ return false;
+}
+
+static uint64_t intel_allocator_simple_alloc(struct intel_allocator *ial,
+ uint32_t handle, uint64_t size,
+ uint64_t alignment)
+{
+ struct intel_allocator_record *rec;
+ struct intel_allocator_simple *ials;
+ uint64_t offset;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ igt_assert(ials);
+ igt_assert(handle);
+ alignment = alignment > 0 ? alignment : 1;
+ rec = igt_map_find(&ials->objects, &handle);
+ if (rec) {
+ offset = rec->offset;
+ igt_assert(rec->size == size);
+ } else {
+ igt_assert(simple_vma_heap_alloc(&ials->heap, &offset,
+ size, alignment));
+ rec = malloc(sizeof(*rec));
+ rec->handle = handle;
+ rec->offset = offset;
+ rec->size = size;
+
+ igt_map_add(&ials->objects, &rec->handle, rec);
+ ials->allocated_objects++;
+ ials->allocated_size += size;
+ }
+
+ return offset;
+}
+
+static bool intel_allocator_simple_free(struct intel_allocator *ial, uint32_t handle)
+{
+ struct intel_allocator_record *rec = NULL;
+ struct intel_allocator_simple *ials;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ igt_assert(ials);
+
+ rec = igt_map_del(&ials->objects, &handle);
+ if (rec) {
+ simple_vma_heap_free(&ials->heap, rec->offset, rec->size);
+ ials->allocated_objects--;
+ ials->allocated_size -= rec->size;
+ free(rec);
+
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool __same(const struct intel_allocator_record *rec,
+ uint32_t handle, uint64_t size, uint64_t offset)
+{
+ return rec->handle == handle && rec->size == size &&
+ DECANONICAL(rec->offset) == DECANONICAL(offset);
+}
+
+static bool intel_allocator_simple_is_allocated(struct intel_allocator *ial,
+ uint32_t handle, uint64_t size,
+ uint64_t offset)
+{
+ struct intel_allocator_record *rec;
+ struct intel_allocator_simple *ials;
+ bool same = false;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ igt_assert(ials);
+ igt_assert(handle);
+
+ rec = igt_map_find(&ials->objects, &handle);
+ if (rec && __same(rec, handle, size, offset))
+ same = true;
+
+ return same;
+}
+
+static bool intel_allocator_simple_reserve(struct intel_allocator *ial,
+ uint32_t handle,
+ uint64_t start, uint64_t end)
+{
+ uint64_t size = end - start;
+ struct intel_allocator_record *rec = NULL;
+ struct intel_allocator_simple *ials;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ igt_assert(ials);
+
+ /* clear [63:48] bits to get rid of canonical form */
+ start = DECANONICAL(start);
+ end = DECANONICAL(end);
+ igt_assert(end > start || end == 0);
+
+ if (simple_vma_heap_alloc_addr(ials, start, size)) {
+ rec = malloc(sizeof(*rec));
+ rec->handle = handle;
+ rec->offset = start;
+ rec->size = size;
+
+ igt_map_add(&ials->reserved, &rec->offset, rec);
+
+ ials->reserved_areas++;
+ ials->reserved_size += rec->size;
+ return true;
+ }
+
+ return false;
+}
+
+static bool intel_allocator_simple_unreserve(struct intel_allocator *ial,
+ uint32_t handle,
+ uint64_t start, uint64_t end)
+{
+ uint64_t size = end - start;
+ struct intel_allocator_record *rec = NULL;
+ struct intel_allocator_simple *ials;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ igt_assert(ials);
+
+ /* clear [63:48] bits to get rid of canonical form */
+ start = DECANONICAL(start);
+ end = DECANONICAL(end);
+
+ igt_assert(end > start || end == 0);
+
+ rec = igt_map_find(&ials->reserved, &start);
+
+ if (!rec) {
+ igt_warn("Only reserved blocks can be unreserved\n");
+ return false;
+ }
+
+ if (rec->size != size) {
+ igt_warn("Only the whole block unreservation allowed\n");
+ return false;
+ }
+
+ if (rec->handle != handle) {
+ igt_warn("Handle %u doesn't match reservation handle: %u\n",
+ rec->handle, handle);
+ return false;
+ }
+
+ igt_map_del(&ials->reserved, &start);
+
+ ials->reserved_areas--;
+ ials->reserved_size -= rec->size;
+ free(rec);
+ simple_vma_heap_free(&ials->heap, start, size);
+
+ return true;
+}
+
+static bool intel_allocator_simple_is_reserved(struct intel_allocator *ial,
+ uint64_t start, uint64_t end)
+{
+ uint64_t size = end - start;
+ struct intel_allocator_record *rec = NULL;
+ struct intel_allocator_simple *ials;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ igt_assert(ials);
+
+ /* clear [63:48] bits to get rid of canonical form */
+ start = DECANONICAL(start);
+ end = DECANONICAL(end);
+
+ igt_assert(end > start || end == 0);
+
+ rec = igt_map_find(&ials->reserved, &start);
+
+ if (!rec)
+ return false;
+
+ if (rec->offset == start && rec->size == size)
+ return true;
+
+ return false;
+}
+
+static bool equal_8bytes(const void *key1, const void *key2)
+{
+ const uint64_t *k1 = key1, *k2 = key2;
+ return *k1 == *k2;
+}
+
+static void intel_allocator_simple_destroy(struct intel_allocator *ial)
+{
+ struct intel_allocator_simple *ials;
+ struct igt_map_entry *pos;
+ struct igt_map *map;
+ int i;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ simple_vma_heap_finish(&ials->heap);
+
+ map = &ials->objects;
+ igt_map_for_each(map, i, pos)
+ free(pos->value);
+ igt_map_free(&ials->objects);
+
+ map = &ials->reserved;
+ igt_map_for_each(map, i, pos)
+ free(pos->value);
+ igt_map_free(&ials->reserved);
+
+ free(ial->priv);
+ free(ial);
+}
+
+#define RESERVE (1024 * 64)
+
+static bool intel_allocator_simple_is_empty(struct intel_allocator *ial)
+{
+ struct intel_allocator_simple *ials = ial->priv;
+
+ igt_debug("<fd: %d, ctx: %u> objects: %" PRId64 ", reserved_areas: %" PRId64 "\n",
+ ial->fd, ial->ctx, ials->allocated_objects, ials->reserved_areas);
+
+ return !ials->allocated_objects && !ials->reserved_areas;
+}
+
+static void intel_allocator_simple_print(struct intel_allocator *ial, bool full)
+{
+ struct intel_allocator_simple *ials;
+ struct simple_vma_hole *hole;
+ struct simple_vma_heap *heap;
+ struct igt_map_entry *pos;
+ struct igt_map *map;
+ uint64_t total_free = 0, allocated_size = 0, allocated_objects = 0;
+ uint64_t reserved_size = 0, reserved_areas = 0;
+ int i;
+
+ igt_assert(ial);
+ ials = (struct intel_allocator_simple *) ial->priv;
+ igt_assert(ials);
+ heap = &ials->heap;
+
+ igt_info("intel_allocator_simple <fd:%d ctx:%d> on "
+ "[0x%"PRIx64" : 0x%"PRIx64"]:\n", ial->fd, ial->ctx,
+ ials->bias, ials->gtt_size - RESERVE);
+
+ if (full) {
+ igt_info("holes:\n");
+ simple_vma_foreach_hole(hole, heap) {
+ igt_info("offset = %"PRIu64" (0x%"PRIx64", "
+ "size = %"PRIu64" (0x%"PRIx64")\n",
+ hole->offset, hole->offset, hole->size,
+ hole->size);
+ total_free += hole->size;
+ }
+ igt_assert(total_free <= ials->total_size);
+ igt_info("total_free: %" PRIx64
+ ", total_size: %" PRIx64
+ ", allocated_size: %" PRIx64
+ ", reserved_size: %" PRIx64 "\n",
+ total_free, ials->total_size, ials->allocated_size,
+ ials->reserved_size);
+ igt_assert(total_free ==
+ ials->total_size - ials->allocated_size - ials->reserved_size);
+
+ igt_info("objects:\n");
+ map = &ials->objects;
+ igt_map_for_each(map, i, pos) {
+ struct intel_allocator_record *rec = pos->value;
+
+ igt_info("handle = %d, offset = %"PRIu64" "
+ "(0x%"PRIx64", size = %"PRIu64" (0x%"PRIx64")\n",
+ rec->handle, rec->offset, rec->offset,
+ rec->size, rec->size);
+ allocated_objects++;
+ allocated_size += rec->size;
+ }
+ igt_assert(ials->allocated_size == allocated_size);
+ igt_assert(ials->allocated_objects == allocated_objects);
+
+ igt_info("reserved areas:\n");
+ map = &ials->reserved;
+ igt_map_for_each(map, i, pos) {
+ struct intel_allocator_record *rec = pos->value;
+
+ igt_info("offset = %"PRIu64" (0x%"PRIx64", "
+ "size = %"PRIu64" (0x%"PRIx64")\n",
+ rec->offset, rec->offset,
+ rec->size, rec->size);
+ reserved_areas++;
+ reserved_size += rec->size;
+ }
+ igt_assert(ials->reserved_areas == reserved_areas);
+ igt_assert(ials->reserved_size == reserved_size);
+ } else
+ simple_vma_foreach_hole(hole, heap)
+ total_free += hole->size;
+
+
+ igt_info("free space: %"PRIu64"B (0x%"PRIx64") (%.2f%% full)\n"
+ "allocated objects: %"PRIu64", reserved areas: %"PRIu64"\n",
+ total_free, total_free,
+ ((double) (ials->total_size - total_free) /
+ (double) ials->total_size) * 100,
+ ials->allocated_objects, ials->reserved_areas);
+}
+
+struct intel_allocator *intel_allocator_simple_create(int fd, uint32_t ctx)
+{
+ struct intel_allocator *ial;
+ struct intel_allocator_simple *ials;
+
+ igt_debug("Using simple allocator <fd: %d, ctx: %u>\n", fd, ctx);
+
+ ial = calloc(1, sizeof(*ial));
+ igt_assert(ial);
+
+ ial->fd = fd;
+ ial->ctx = ctx;
+ ial->get_address_range = intel_allocator_simple_get_address_range;
+ ial->alloc = intel_allocator_simple_alloc;
+ ial->free = intel_allocator_simple_free;
+ ial->is_allocated = intel_allocator_simple_is_allocated;
+ ial->reserve = intel_allocator_simple_reserve;
+ ial->unreserve = intel_allocator_simple_unreserve;
+ ial->is_reserved = intel_allocator_simple_is_reserved;
+ ial->destroy = intel_allocator_simple_destroy;
+ ial->is_empty = intel_allocator_simple_is_empty;
+ ial->print = intel_allocator_simple_print;
+ ials = ial->priv = malloc(sizeof(struct intel_allocator_simple));
+ igt_assert(ials);
+
+ igt_map_init(&ials->objects, NULL, NULL, 8);
+ /* Reserved addresses hashtable is indexed by an offset */
+ igt_map_init(&ials->reserved, equal_8bytes, NULL, 3);
+
+ ials->gtt_size = gem_aperture_size(fd);
+ igt_debug("Gtt size: %" PRId64 "\n", ials->gtt_size);
+ if (!gem_uses_full_ppgtt(fd))
+ ials->gtt_size /= 2;
+
+ ials->bias = get_bias(fd);
+ ials->total_size = ials->gtt_size - ials->bias - RESERVE;
+ ials->start = ials->bias;
+ ials->end = ials->gtt_size - RESERVE;
+ simple_vma_heap_init(&ials->heap, ials->bias, ials->total_size);
+
+ ials->allocated_size = 0;
+ ials->allocated_objects = 0;
+ ials->reserved_size = 0;
+ ials->reserved_areas = 0;
+
+ return ial;
+}
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 05/23] lib/intel_allocator_random: Add random allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (3 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 04/23] lib/intel_allocator_simple: Add simple allocator Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 06/23] lib/intel_allocator: Add intel_allocator core Zbigniew Kempczyński
` (21 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
Sometimes we want to experiment with addresses so randomizing can help
us a little.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_allocator_random.c | 223 +++++++++++++++++++++++++++++++++++
1 file changed, 223 insertions(+)
create mode 100644 lib/intel_allocator_random.c
diff --git a/lib/intel_allocator_random.c b/lib/intel_allocator_random.c
new file mode 100644
index 00000000..23cf7c4e
--- /dev/null
+++ b/lib/intel_allocator_random.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <sys/ioctl.h>
+#include <stdlib.h>
+#include "igt.h"
+#include "igt_x86.h"
+#include "igt_rand.h"
+#include "intel_allocator.h"
+
+struct intel_allocator *intel_allocator_random_create(int fd, uint32_t ctx);
+
+struct intel_allocator_random {
+ uint64_t bias;
+ uint32_t prng;
+ uint64_t gtt_size;
+ uint64_t start;
+ uint64_t end;
+
+ /* statistics */
+ uint64_t allocated_objects;
+};
+
+#define GEN8_HIGH_ADDRESS_BIT 47
+static uint64_t gen8_canonical_addr(uint64_t address)
+{
+ int shift = 63 - GEN8_HIGH_ADDRESS_BIT;
+
+ return (int64_t)(address << shift) >> shift;
+}
+
+static uint64_t get_bias(int fd)
+{
+ (void) fd;
+
+ return 256 << 10;
+}
+
+static void intel_allocator_random_get_address_range(struct intel_allocator *ial,
+ uint64_t *startp,
+ uint64_t *endp)
+{
+ struct intel_allocator_random *ialr = ial->priv;
+
+ if (startp)
+ *startp = ialr->start;
+
+ if (endp)
+ *endp = ialr->end;
+}
+
+static uint64_t intel_allocator_random_alloc(struct intel_allocator *ial,
+ uint32_t handle, uint64_t size,
+ uint64_t alignment)
+{
+ struct intel_allocator_random *ialr = ial->priv;
+ uint64_t offset;
+
+ (void) handle;
+
+ /* randomize the address, we try to avoid relocations */
+ offset = hars_petruska_f54_1_random64(&ialr->prng);
+ offset += ialr->bias; /* Keep the low 256k clear, for negative deltas */
+ offset &= ialr->gtt_size - 1;
+ offset &= ~(alignment - 1);
+ offset = gen8_canonical_addr(offset);
+
+ ialr->allocated_objects++;
+
+ return offset;
+}
+
+static bool intel_allocator_random_free(struct intel_allocator *ial,
+ uint32_t handle)
+{
+ struct intel_allocator_random *ialr = ial->priv;
+
+ (void) handle;
+
+ ialr->allocated_objects--;
+
+ return false;
+}
+
+static bool intel_allocator_random_is_allocated(struct intel_allocator *ial,
+ uint32_t handle, uint64_t size,
+ uint64_t offset)
+{
+ (void) ial;
+ (void) handle;
+ (void) size;
+ (void) offset;
+
+ return false;
+}
+
+static void intel_allocator_random_destroy(struct intel_allocator *ial)
+{
+ igt_assert(ial);
+
+ free(ial->priv);
+ free(ial);
+}
+
+static bool intel_allocator_random_reserve(struct intel_allocator *ial,
+ uint32_t handle,
+ uint64_t start, uint64_t end)
+{
+ (void) ial;
+ (void) handle;
+ (void) start;
+ (void) end;
+
+ return false;
+}
+
+static bool intel_allocator_random_unreserve(struct intel_allocator *ial,
+ uint32_t handle,
+ uint64_t start, uint64_t end)
+{
+ (void) ial;
+ (void) handle;
+ (void) start;
+ (void) end;
+
+ return false;
+}
+
+static bool intel_allocator_random_is_reserved(struct intel_allocator *ial,
+ uint64_t start, uint64_t end)
+{
+ (void) ial;
+ (void) start;
+ (void) end;
+
+ return false;
+}
+
+static void intel_allocator_random_print(struct intel_allocator *ial, bool full)
+{
+ struct intel_allocator_random *ialr = ial->priv;
+
+ (void) full;
+
+ igt_info("<fd: %d, ctx: %u> allocated objects: %" PRIx64 "\n",
+ ial->fd, ial->ctx, ialr->allocated_objects);
+}
+
+static bool intel_allocator_random_is_empty(struct intel_allocator *ial)
+{
+ struct intel_allocator_random *ialr = ial->priv;
+
+ return !ialr->allocated_objects;
+}
+
+struct intel_allocator *intel_allocator_random_create(int fd, uint32_t ctx)
+{
+ struct intel_allocator *ial;
+ struct intel_allocator_random *ialr;
+
+ igt_debug("Using random allocator\n");
+ ial = calloc(1, sizeof(*ial));
+ igt_assert(ial);
+
+ ial->fd = fd;
+ ial->ctx = ctx;
+ ial->get_address_range = intel_allocator_random_get_address_range;
+ ial->alloc = intel_allocator_random_alloc;
+ ial->free = intel_allocator_random_free;
+ ial->is_allocated = intel_allocator_random_is_allocated;
+ ial->reserve = intel_allocator_random_reserve;
+ ial->unreserve = intel_allocator_random_unreserve;
+ ial->is_reserved = intel_allocator_random_is_reserved;
+ ial->destroy = intel_allocator_random_destroy;
+ ial->print = intel_allocator_random_print;
+ ial->is_empty = intel_allocator_random_is_empty;
+
+ ialr = ial->priv = calloc(1, sizeof(*ialr));
+ igt_assert(ial->priv);
+ ialr->prng = (uint32_t) to_user_pointer(ial);
+ ialr->gtt_size = gem_aperture_size(fd);
+ igt_debug("Gtt size: %" PRId64 "\n", ialr->gtt_size);
+ if (!gem_uses_full_ppgtt(fd))
+ ialr->gtt_size /= 2;
+
+ if ((ialr->gtt_size - 1) >> 32) {
+ /*
+ * We're not aware of bo sizes, so limiting to 46 bit make us
+ * sure we won't enter to addresses with 47-bit set
+ * (we use 32-bit size now so still we fit 47-bit address space).
+ */
+ if (ialr->gtt_size & (3ull << 47))
+ ialr->gtt_size = (1ull << 46);
+ }
+ ialr->bias = get_bias(fd);
+ ialr->start = ialr->bias;
+ ialr->end = ialr->gtt_size;
+
+ ialr->allocated_objects = 0;
+
+ return ial;
+}
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 06/23] lib/intel_allocator: Add intel_allocator core
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (4 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 05/23] lib/intel_allocator_random: Add random allocator Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 07/23] lib/intel_allocator: Try to stop smoothly instead of deinit Zbigniew Kempczyński
` (20 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Petri Latvala, Chris Wilson
For discrete gens we have to cease of using relocations when batch
buffers are submitted to GPU. Cards which have ppgtt can use softpin
and establish addresses on our own.
We added simple allocator (taken from Mesa; works on lists) and added
random allocator to exercise batches with different addresses. All
of that works for single VM (context) so we have to add additional
layer (intel_allocator) to support multiprocessing / multithreading.
For main IGT process (also for threads created in it) intel_allocator
resolves addresses "locally", just by mutexing access to global
allocator data (allocators map). When fork() is in use children cannot
establish addresses on they own and have to contact to the thread
spawned within main IGT process. Currently SysV IPC message queue was
chosen as a communication channel between children and allocator thread.
Child calls same functions as main IGT process, only communication path
will be chosen instead of acquiring addresses locally.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
---
.../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
lib/igt_core.c | 13 +
lib/intel_allocator.c | 939 ++++++++++++++++++
lib/intel_allocator.h | 136 +++
lib/intel_allocator_msgchannel.c | 182 ++++
lib/intel_allocator_msgchannel.h | 140 +++
lib/intel_allocator_simple.c | 2 -
lib/meson.build | 4 +
8 files changed, 1415 insertions(+), 2 deletions(-)
create mode 100644 lib/intel_allocator.c
create mode 100644 lib/intel_allocator.h
create mode 100644 lib/intel_allocator_msgchannel.c
create mode 100644 lib/intel_allocator_msgchannel.h
diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
index bf5ac542..192d1df7 100644
--- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
+++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
@@ -43,6 +43,7 @@
<xi:include href="xml/igt_vc4.xml"/>
<xi:include href="xml/igt_vgem.xml"/>
<xi:include href="xml/igt_x86.xml"/>
+ <xi:include href="xml/intel_allocator.xml"/>
<xi:include href="xml/intel_batchbuffer.xml"/>
<xi:include href="xml/intel_bufops.xml"/>
<xi:include href="xml/intel_chipset.xml"/>
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 1f725d00..9f80d1d6 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -1414,6 +1414,19 @@ static void exit_subtest(const char *result)
}
num_test_children = 0;
+ /*
+ * When test completes - mostly in fail state it can leave allocated
+ * objects. An allocator is not an exception as it is global IGT
+ * entity and when test will allocate some ranges and then it will
+ * fail no free/close likely will be called (controling potential
+ * fails and clearing before assertions in IGT is not common).
+ *
+ * We call intel_allocator_init() then to prepare the allocator
+ * infrastructure from scratch for each test. Init also removes
+ * remnants from previous allocator run (if any).
+ */
+ intel_allocator_init();
+
if (!in_dynamic_subtest)
_igt_dynamic_tests_executed = -1;
diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
new file mode 100644
index 00000000..b0ae1d8b
--- /dev/null
+++ b/lib/intel_allocator.c
@@ -0,0 +1,939 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ipc.h>
+#include <sys/msg.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include "igt.h"
+#include "igt_map.h"
+#include "intel_allocator.h"
+#include "intel_allocator_msgchannel.h"
+
+//#define ALLOCDBG
+#ifdef ALLOCDBG
+#define alloc_info igt_info
+#define alloc_debug igt_debug
+static const char *reqtype_str[] = {
+ [REQ_STOP] = "stop",
+ [REQ_OPEN] = "open",
+ [REQ_CLOSE] = "close",
+ [REQ_REMOVE_HANDLE] = "remove handle",
+ [REQ_ADDRESS_RANGE] = "address range",
+ [REQ_ALLOC] = "alloc",
+ [REQ_FREE] = "free",
+ [REQ_IS_ALLOCATED] = "is allocated",
+ [REQ_RESERVE] = "reserve",
+ [REQ_UNRESERVE] = "unreserve",
+ [REQ_RESERVE_IF_NOT_ALLOCATED] = "reserve-ina",
+ [REQ_IS_RESERVED] = "is reserved",
+};
+static inline const char *reqstr(enum reqtype request_type)
+{
+ igt_assert(request_type >= REQ_STOP && request_type <= REQ_IS_RESERVED);
+ return reqtype_str[request_type];
+}
+#else
+#define alloc_info(...) {}
+#define alloc_debug(...) {}
+#endif
+
+struct intel_allocator *intel_allocator_random_create(int fd, uint32_t ctx);
+struct intel_allocator *intel_allocator_simple_create(int fd, uint32_t ctx);
+
+static struct igt_map *allocators_map;
+static pthread_mutex_t map_mutex = PTHREAD_MUTEX_INITIALIZER;
+static bool multiprocess;
+static pthread_t allocator_thread;
+
+static bool warn_if_not_empty;
+
+/* For allocator purposes we need to track pid/tid */
+static pid_t allocator_pid = -1;
+extern pid_t child_pid;
+extern __thread pid_t child_tid;
+
+static struct msg_channel *channel;
+
+static int send_alloc_stop(struct msg_channel *msgchan)
+{
+ struct alloc_req req = {0};
+
+ req.request_type = REQ_STOP;
+
+ return msgchan->send_req(msgchan, &req);
+}
+
+static int send_req(struct msg_channel *msgchan, pid_t tid,
+ struct alloc_req *request)
+{
+ request->tid = tid;
+ return msgchan->send_req(msgchan, request);
+}
+
+static int recv_req(struct msg_channel *msgchan, struct alloc_req *request)
+{
+ return msgchan->recv_req(msgchan, request);
+}
+
+static int send_resp(struct msg_channel *msgchan,
+ pid_t tid, struct alloc_resp *response)
+{
+ response->tid = tid;
+ return msgchan->send_resp(msgchan, response);
+}
+
+static int recv_resp(struct msg_channel *msgchan,
+ pid_t tid, struct alloc_resp *response)
+{
+ response->tid = tid;
+ return msgchan->recv_resp(msgchan, response);
+}
+
+static struct intel_allocator *intel_allocator_create(int fd, uint32_t ctx,
+ uint8_t allocator_type)
+{
+ struct intel_allocator *ial;
+
+ switch (allocator_type) {
+ case INTEL_ALLOCATOR_NONE:
+ igt_assert_f(allocator_type != INTEL_ALLOCATOR_NONE,
+ "Bug, trying to use allocator with relocations");
+ break;
+ case INTEL_ALLOCATOR_RANDOM:
+ ial = intel_allocator_random_create(fd, ctx);
+ break;
+ case INTEL_ALLOCATOR_SIMPLE:
+ ial = intel_allocator_simple_create(fd, ctx);
+ break;
+ default:
+ igt_assert_f(ial, "Allocator type %d not implemented\n",
+ allocator_type);
+ break;
+ }
+
+ ial->type = allocator_type;
+ atomic_fetch_add(&ial->refcount, 1);
+ pthread_mutex_init(&ial->mutex, NULL);
+
+ igt_map_add(allocators_map, ial, ial);
+
+ return ial;
+}
+
+static void intel_allocator_destroy(struct intel_allocator *ial)
+{
+ alloc_info("Destroying allocator (empty: %d)\n",
+ ial->is_empty(ial));
+
+ ial->destroy(ial);
+}
+
+static struct intel_allocator *__allocator_get(int fd, uint32_t ctx)
+{
+ struct intel_allocator *ial, ials = { .fd = fd, .ctx = ctx };
+ int refcount;
+
+ ial = igt_map_find(allocators_map, &ials);
+ if (!ial)
+ goto out_get;
+
+ refcount = atomic_fetch_add(&ial->refcount, 1);
+ igt_assert(refcount > 0);
+
+out_get:
+
+ return ial;
+}
+
+static bool __allocator_put(struct intel_allocator *ial)
+{
+ struct intel_allocator ials = { .fd = ial->fd, .ctx = ial->ctx };
+ bool released = false;
+ int refcount;
+
+ ial = igt_map_find(allocators_map, &ials);
+ igt_assert(ial);
+
+ refcount = atomic_fetch_sub(&ial->refcount, 1);
+ alloc_debug("Refcount: %d\n", refcount);
+ igt_assert(refcount >= 1);
+ if (refcount == 1) {
+ igt_map_del(allocators_map, ial);
+
+ if (!ial->is_empty(ial) && warn_if_not_empty)
+ igt_warn("Allocator not clear before destroy!\n");
+
+ released = true;
+ }
+
+ return released;
+}
+
+static struct intel_allocator *allocator_open(int fd, uint32_t ctx,
+ uint8_t allocator_type)
+{
+ struct intel_allocator *ial;
+
+ pthread_mutex_lock(&map_mutex);
+
+ ial = __allocator_get(fd, ctx);
+ if (ial) {
+ if (ial->type != allocator_type)
+ pthread_mutex_unlock(&map_mutex);
+ igt_assert_f(ial->type == allocator_type,
+ "Allocator must be same type for fd/ctx\n");
+ } else {
+ alloc_debug("Allocator fd: %d, ctx: %u not found, creating one\n",
+ fd, ctx);
+ ial = intel_allocator_create(fd, ctx, allocator_type);
+ }
+
+ pthread_mutex_unlock(&map_mutex);
+
+ return ial;
+}
+
+static bool allocator_close(uint64_t allocator_handle)
+{
+ struct intel_allocator *ial = from_user_pointer(allocator_handle);
+ bool released, is_empty = false;
+
+ igt_assert(ial);
+
+ pthread_mutex_lock(&map_mutex);
+
+ released = __allocator_put(ial);
+ if (released) {
+ is_empty = ial->is_empty(ial);
+ intel_allocator_destroy(ial);
+ }
+
+ pthread_mutex_unlock(&map_mutex);
+
+ return is_empty;
+}
+
+static int send_req_recv_resp(struct msg_channel *msgchan,
+ struct alloc_req *request,
+ struct alloc_resp *response)
+{
+ int ret;
+
+ ret = send_req(msgchan, child_tid, request);
+ if (ret < 0) {
+ igt_warn("Error sending request [type: %d]: err = %d [%s]\n",
+ request->request_type, errno, strerror(errno));
+
+ return ret;
+ }
+
+ ret = recv_resp(msgchan, child_tid, response);
+ if (ret < 0)
+ igt_warn("Error receiving response [type: %d]: err = %d [%s]\n",
+ request->request_type, errno, strerror(errno));
+
+ /*
+ * This is main assumption - we receive message which size must be > 0.
+ * If this is fulfilled we return 0 as a success.
+ */
+ if (ret > 0)
+ ret = 0;
+
+ return ret;
+}
+
+static int handle_request(struct alloc_req *req, struct alloc_resp *resp)
+{
+ bool same_process = child_pid == -1;
+ int ret;
+
+ memset(resp, 0, sizeof(*resp));
+
+ if (same_process) {
+ struct intel_allocator *ial;
+ uint64_t start, end, size;
+ bool allocated, reserved, unreserved;
+
+ /* Mutex only work on allocator instance, not stop/open/close */
+ if (req->request_type > REQ_CLOSE) {
+ ial = from_user_pointer(req->allocator_handle);
+ igt_assert(ial);
+
+ pthread_mutex_lock(&ial->mutex);
+ }
+
+ switch (req->request_type) {
+ case REQ_STOP:
+ alloc_info("<stop>\n");
+ break;
+
+ case REQ_OPEN:
+ ial = allocator_open(req->open.fd, req->open.ctx,
+ req->open.allocator_type);
+ igt_assert(ial);
+
+ resp->response_type = RESP_OPEN;
+ resp->open.allocator_handle = to_user_pointer(ial);
+ alloc_info("<open> [tid: %ld] fd: %d, ctx: %u, alloc_type: %u, "
+ "ahnd: %p, refcnt: %d\n",
+ (long) req->tid, req->open.fd, req->open.ctx,
+ req->open.allocator_type, ial,
+ atomic_load(&ial->refcount));
+ break;
+
+ case REQ_CLOSE:
+ ial = from_user_pointer(req->allocator_handle);
+ igt_assert(ial);
+
+ resp->response_type = RESP_CLOSE;
+ ret = atomic_load(&ial->refcount);
+ resp->close.is_empty = allocator_close(req->allocator_handle);
+ alloc_info("<close> [tid: %ld] ahnd: %p, is_empty: %d, refcnt: %d\n",
+ (long) req->tid, ial, resp->close.is_empty, ret);
+ break;
+
+ case REQ_ADDRESS_RANGE:
+ resp->response_type = RESP_ADDRESS_RANGE;
+ ial->get_address_range(ial, &start, &end);
+ resp->address_range.start = start;
+ resp->address_range.end = end;
+ alloc_info("<address range> [tid: %ld] start: %" PRIx64
+ ", end: %" PRId64 "\n", (long) req->tid,
+ start, end);
+ break;
+
+ case REQ_ALLOC:
+ resp->response_type = RESP_ALLOC;
+ resp->alloc.offset = ial->alloc(ial,
+ req->alloc.handle,
+ req->alloc.size,
+ req->alloc.alignment);
+ alloc_info("<alloc> [tid: %ld] handle: %u, offset: %" PRIx64
+ ", alignment: %" PRIx64 "\n",
+ (long) req->tid, req->alloc.handle,
+ resp->alloc.offset, req->alloc.alignment);
+ break;
+
+ case REQ_FREE:
+ resp->response_type = RESP_FREE;
+ resp->free.freed = ial->free(ial, req->free.handle);
+ alloc_info("<free> [tid: %ld] handle: %u, freed: %d\n",
+ (long) req->tid, req->free.handle, resp->free.freed);
+ break;
+
+ case REQ_IS_ALLOCATED:
+ resp->response_type = RESP_IS_ALLOCATED;
+ allocated = ial->is_allocated(ial,
+ req->is_allocated.handle,
+ req->is_allocated.size,
+ req->is_allocated.offset);
+ resp->is_allocated.allocated = allocated;
+ alloc_info("<is allocated> [tid: %ld] offset: %" PRIx64
+ ", allocated: %d\n", (long) req->tid,
+ req->is_allocated.offset, allocated);
+ break;
+
+ case REQ_RESERVE:
+ resp->response_type = RESP_RESERVE;
+ reserved = ial->reserve(ial,
+ req->reserve.handle,
+ req->reserve.start,
+ req->reserve.end);
+ resp->reserve.reserved = reserved;
+ alloc_info("<reserve> [tid: %ld] handle: %u, start: %" PRIx64
+ ", end: %" PRIx64 ", reserved: %d\n",
+ (long) req->tid, req->reserve.handle,
+ req->reserve.start, req->reserve.end, reserved);
+ break;
+
+ case REQ_UNRESERVE:
+ resp->response_type = RESP_UNRESERVE;
+ unreserved = ial->unreserve(ial,
+ req->unreserve.handle,
+ req->unreserve.start,
+ req->unreserve.end);
+ resp->unreserve.unreserved = unreserved;
+ alloc_info("<unreserve> [tid: %ld] handle: %u, start: %" PRIx64
+ ", end: %" PRIx64 ", unreserved: %d\n",
+ (long) req->tid, req->unreserve.handle,
+ req->unreserve.start, req->unreserve.end,
+ unreserved);
+ break;
+
+ case REQ_IS_RESERVED:
+ resp->response_type = RESP_IS_RESERVED;
+ reserved = ial->is_reserved(ial,
+ req->is_reserved.start,
+ req->is_reserved.end);
+ resp->is_reserved.reserved = reserved;
+ alloc_info("<is reserved> [tid: %ld] start: %" PRIx64
+ ", end: %" PRIx64 ", reserved: %d\n",
+ (long) req->tid, req->is_reserved.start,
+ req->is_reserved.end, reserved);
+ break;
+
+ case REQ_RESERVE_IF_NOT_ALLOCATED:
+ resp->response_type = RESP_RESERVE_IF_NOT_ALLOCATED;
+ size = DECANONICAL(req->reserve.end) - DECANONICAL(req->reserve.start);
+
+ allocated = ial->is_allocated(ial, req->reserve.handle,
+ size, req->reserve.start);
+ if (allocated) {
+ resp->reserve_if_not_allocated.allocated = allocated;
+ alloc_info("<reserve if not allocated> [tid: %ld] handle: %u "
+ "size: %lx, start: %" PRIx64
+ ", end: %" PRIx64 ", allocated: %d, reserved: %d\n",
+ (long) req->tid, req->reserve.handle,
+ (long) size, req->reserve.start,
+ req->reserve.end, allocated, false);
+ break;
+ }
+
+ reserved = ial->reserve(ial,
+ req->reserve.handle,
+ req->reserve.start,
+ req->reserve.end);
+ resp->reserve_if_not_allocated.reserved = reserved;
+ alloc_info("<reserve if not allocated> [tid: %ld] handle: %u"
+ ", start: %" PRIx64
+ ", end: %" PRIx64 ", allocated: %d, reserved: %d\n",
+ (long) req->tid, req->reserve.handle,
+ req->reserve.start, req->reserve.end,
+ false, reserved);
+ break;
+
+ }
+
+ if (req->request_type > REQ_CLOSE)
+ pthread_mutex_unlock(&ial->mutex);
+
+ return 0;
+ }
+
+ ret = send_req_recv_resp(channel, req, resp);
+
+ if (ret < 0)
+ exit(0);
+
+ return ret;
+}
+
+static void kill_children(int sig)
+{
+ signal(sig, SIG_IGN);
+ kill(-getpgrp(), sig);
+ signal(sig, SIG_DFL);
+}
+
+static void *allocator_thread_loop(void *data)
+{
+ struct alloc_req req;
+ struct alloc_resp resp;
+ int ret;
+ (void) data;
+
+ alloc_info("Allocator pid: %ld, tid: %ld\n",
+ (long) allocator_pid, (long) gettid());
+ alloc_info("Entering allocator loop\n");
+
+ while (1) {
+ ret = recv_req(channel, &req);
+
+ if (ret == -1) {
+ igt_warn("Error receiving request in thread, ret = %d [%s]\n",
+ ret, strerror(errno));
+ kill_children(SIGINT);
+ return (void *) -1;
+ }
+
+ /* Fake message to stop the thread */
+ if (req.request_type == REQ_STOP) {
+ alloc_info("<stop request>\n");
+ break;
+ }
+
+ ret = handle_request(&req, &resp);
+ if (ret) {
+ igt_warn("Error handling request in thread, ret = %d [%s]\n",
+ ret, strerror(errno));
+ break;
+ }
+
+ ret = send_resp(channel, req.tid, &resp);
+ if (ret) {
+ igt_warn("Error sending response in thread, ret = %d [%s]\n",
+ ret, strerror(errno));
+
+ kill_children(SIGINT);
+ return (void *) -1;
+ }
+ }
+
+ return NULL;
+}
+
+/**
+ * intel_allocator_multiprocess_start:
+ *
+ * Function turns on intel_allocator multiprocess mode what means
+ * all allocations from children processes are performed in a separate thread
+ * within main igt process. Children are aware of the situation and use
+ * some interprocess communication channel to send/receive messages
+ * (open, close, alloc, free, ...) to/from allocator thread.
+ *
+ * Must be used when you want to use an allocator in non single-process code.
+ * All allocations in threads spawned in main igt process are handled by
+ * mutexing, not by sending/receiving messages to/from allocator thread.
+ *
+ * Note. This destroys all previously created allocators and theirs content.
+ */
+void intel_allocator_multiprocess_start(void)
+{
+ alloc_info("allocator multiprocess start\n");
+
+ intel_allocator_init();
+
+ multiprocess = true;
+ channel->init(channel);
+
+ pthread_create(&allocator_thread, NULL,
+ allocator_thread_loop, NULL);
+}
+
+/**
+ * intel_allocator_multiprocess_stop:
+ *
+ * Function turns off intel_allocator multiprocess mode what means means
+ * stopping allocator thread and deinitializing its data.
+ */
+void intel_allocator_multiprocess_stop(void)
+{
+ alloc_info("allocator multiprocess stop\n");
+
+ if (multiprocess) {
+ send_alloc_stop(channel);
+ /* Deinit, this should stop all blocked syscalls, if any */
+ channel->deinit(channel);
+ pthread_join(allocator_thread, NULL);
+ /* But we're not sure does child will stuck */
+ kill_children(SIGINT);
+ igt_waitchildren_timeout(5, "Stopping children");
+ multiprocess = false;
+ }
+}
+
+/**
+ * intel_allocator_open:
+ * @fd: i915 descriptor
+ * @ctx: context
+ * @allocator_type: one of INTEL_ALLOCATOR_* define
+ *
+ * Function opens an allocator instance for given @fd and @ctx and returns
+ * its handle. If the allocator for such pair doesn't exist it is created
+ * with refcount = 1. Parallel opens returns same handle bumping its refcount.
+ *
+ * Returns: unique handle to the currently opened allocator.
+ */
+uint64_t intel_allocator_open(int fd, uint32_t ctx, uint8_t allocator_type)
+{
+ struct alloc_req req = { .request_type = REQ_OPEN,
+ .open.fd = fd,
+ .open.ctx = ctx,
+ .open.allocator_type = allocator_type };
+ struct alloc_resp resp;
+
+ /* Get child_tid only once at open() */
+ if (child_tid == -1)
+ child_tid = gettid();
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.open.allocator_handle);
+ igt_assert(resp.response_type == RESP_OPEN);
+
+ return resp.open.allocator_handle;
+}
+
+/**
+ * intel_allocator_close:
+ * @allocator_handle: handle to the allocator that will be closed
+ *
+ * Function decreases an allocator refcount for the given @handle.
+ * When refcount reaches zero allocator is closed (destroyed) and all
+ * allocated / reserved areas are freed.
+ *
+ * Returns: true if closed allocator was empty, false otherwise.
+ */
+bool intel_allocator_close(uint64_t allocator_handle)
+{
+ struct alloc_req req = { .request_type = REQ_CLOSE,
+ .allocator_handle = allocator_handle };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_CLOSE);
+
+ return resp.close.is_empty;
+}
+
+/**
+ * intel_allocator_get_address_range:
+ * @allocator_handle: handle to an allocator
+ * @startp: pointer to the variable where function writes starting offset
+ * @endp: pointer to the variable where function writes ending offset
+ *
+ * Function fills @startp, @endp with respectively, starting and ending offset
+ * of the allocator working virtual address space range.
+ *
+ * Note. Allocators working ranges can differ depending on the device or
+ * the allocator type so before reserving a specific offset a good practise
+ * is to ensure that address is between accepted range.
+ */
+void intel_allocator_get_address_range(uint64_t allocator_handle,
+ uint64_t *startp, uint64_t *endp)
+{
+ struct alloc_req req = { .request_type = REQ_ADDRESS_RANGE,
+ .allocator_handle = allocator_handle };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_ADDRESS_RANGE);
+
+ if (startp)
+ *startp = resp.address_range.start;
+
+ if (endp)
+ *endp = resp.address_range.end;
+}
+
+/**
+ * intel_allocator_alloc:
+ * @allocator_handle: handle to an allocator
+ * @handle: handle to an object
+ * @size: size of an object
+ * @alignment: determines object alignment
+ *
+ * Function finds and returns the most suitable offset with given @alignment
+ * for an object with @size identified by the @handle.
+ *
+ * Returns: currently assigned address for a given object. If an object was
+ * already allocated returns same address.
+ */
+uint64_t intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t alignment)
+{
+ struct alloc_req req = { .request_type = REQ_ALLOC,
+ .allocator_handle = allocator_handle,
+ .alloc.handle = handle,
+ .alloc.size = size,
+ .alloc.alignment = alignment };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_ALLOC);
+
+ return resp.alloc.offset;
+}
+
+/**
+ * intel_allocator_free:
+ * @allocator_handle: handle to an allocator
+ * @handle: handle to an object to be freed
+ *
+ * Function free object identified by the @handle in allocator what makes it
+ * offset again allocable.
+ *
+ * Note. Reserved objects can only be freed by an #intel_allocator_unreserve
+ * function.
+ *
+ * Returns: true if the object was successfully freed, otherwise false.
+ */
+bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle)
+{
+ struct alloc_req req = { .request_type = REQ_FREE,
+ .allocator_handle = allocator_handle,
+ .free.handle = handle };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_FREE);
+
+ return resp.free.freed;
+}
+
+/**
+ * intel_allocator_is_allocated:
+ * @allocator_handle: handle to an allocator
+ * @handle: handle to an object
+ * @size: size of an object
+ * @offset: address of an object
+ *
+ * Function checks whether the object identified by the @handle and @size
+ * is allocated at the @offset.
+ *
+ * Returns: true if the object is currently allocated at the @offset,
+ * otherwise false.
+ */
+bool intel_allocator_is_allocated(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t offset)
+{
+ struct alloc_req req = { .request_type = REQ_IS_ALLOCATED,
+ .allocator_handle = allocator_handle,
+ .is_allocated.handle = handle,
+ .is_allocated.size = size,
+ .is_allocated.offset = offset };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_IS_ALLOCATED);
+
+ return resp.is_allocated.allocated;
+}
+
+/**
+ * intel_allocator_reserve:
+ * @allocator_handle: handle to an allocator
+ * @handle: handle to an object
+ * @size: size of an object
+ * @offset: address of an object
+ *
+ * Function reserves space that starts at the @offset and has @size.
+ * Optionally we can pass @handle to mark that space is for a specific
+ * object, otherwise pass -1.
+ *
+ * Note. Reserved space is identified by offset and size, not a handle.
+ * So an object can have multiple reserved spaces with its handle.
+ *
+ * Returns: true if space is successfully reserved, otherwise false.
+ */
+bool intel_allocator_reserve(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t offset)
+{
+ struct alloc_req req = { .request_type = REQ_RESERVE,
+ .allocator_handle = allocator_handle,
+ .reserve.handle = handle,
+ .reserve.start = offset,
+ .reserve.end = offset + size };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_RESERVE);
+
+ return resp.reserve.reserved;
+}
+
+/**
+ * intel_allocator_unreserve:
+ * @allocator_handle: handle to an allocator
+ * @handle: handle to an object
+ * @size: size of an object
+ * @offset: address of an object
+ *
+ * Function unreserves space that starts at the @offset, @size and @handle.
+ *
+ * Note. @handle, @size and @offset have to match those used in reservation.
+ * i.e. check with the same offset but even smaller size will fail.
+ *
+ * Returns: true if the space is successfully unreserved, otherwise false.
+ */
+bool intel_allocator_unreserve(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t offset)
+{
+ struct alloc_req req = { .request_type = REQ_UNRESERVE,
+ .allocator_handle = allocator_handle,
+ .unreserve.handle = handle,
+ .unreserve.start = offset,
+ .unreserve.end = offset + size };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_UNRESERVE);
+
+ return resp.unreserve.unreserved;
+}
+
+/**
+ * intel_allocator_is_reserved:
+ * @allocator_handle: handle to an allocator
+ * @size: size of an object
+ * @offset: address of an object
+ *
+ * Function checks whether space starting at the @offset and @size is
+ * currently under reservation.
+ *
+ * Note. @size and @offset have to match those used in reservation,
+ * i.e. check with the same offset but even smaller size will fail.
+ *
+ * Returns: true if space is reserved, othwerise false.
+ */
+bool intel_allocator_is_reserved(uint64_t allocator_handle,
+ uint64_t size, uint64_t offset)
+{
+ struct alloc_req req = { .request_type = REQ_IS_RESERVED,
+ .allocator_handle = allocator_handle,
+ .is_reserved.start = offset,
+ .is_reserved.end = offset + size };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_IS_RESERVED);
+
+ return resp.is_reserved.reserved;
+}
+
+/**
+ * intel_allocator_reserve_if_not_allocated:
+ * @allocator_handle: handle to an allocator
+ * @handle: handle to an object
+ * @size: size of an object
+ * @offset: address of an object
+ * @is_allocatedp: if not NULL function writes there object allocation status
+ * (true/false)
+ *
+ * Function checks whether the object identified by the @handle and @size
+ * is allocated at the @offset and writes the result to @is_allocatedp.
+ * If it's not it reserves it at the given @offset.
+ *
+ * Returns: true if the space for an object was reserved, otherwise false.
+ */
+bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle,
+ uint32_t handle,
+ uint64_t size, uint64_t offset,
+ bool *is_allocatedp)
+{
+ struct alloc_req req = { .request_type = REQ_RESERVE_IF_NOT_ALLOCATED,
+ .allocator_handle = allocator_handle,
+ .reserve.handle = handle,
+ .reserve.start = offset,
+ .reserve.end = offset + size };
+ struct alloc_resp resp;
+
+ igt_assert(handle_request(&req, &resp) == 0);
+ igt_assert(resp.response_type == RESP_RESERVE_IF_NOT_ALLOCATED);
+
+ if (is_allocatedp)
+ *is_allocatedp = resp.reserve_if_not_allocated.allocated;
+
+ return resp.reserve_if_not_allocated.reserved;
+}
+
+/**
+ * intel_allocator_print:
+ * @allocator_handle: handle to an allocator
+ *
+ * Function prints statistics and content of the allocator.
+ * Mainly for debugging purposes.
+ *
+ * Note. Printing possible only in the main process.
+ **/
+void intel_allocator_print(uint64_t allocator_handle)
+{
+ bool same_process;
+
+ igt_assert(allocator_handle);
+
+ same_process = child_pid == -1;
+
+ if (!multiprocess || same_process) {
+ struct intel_allocator *ial = from_user_pointer(allocator_handle);
+ pthread_mutex_lock(&map_mutex);
+ ial->print(ial, true);
+ pthread_mutex_unlock(&map_mutex);
+ } else {
+ igt_warn("Print stats is in main process only\n");
+ }
+}
+
+static bool equal_allocators(const void *key1, const void *key2)
+{
+ const struct intel_allocator *a1 = key1, *a2 = key2;
+
+ alloc_debug("a1: <fd: %d, ctx: %u>, a2 <fd: %d, ctx: %u>\n",
+ a1->fd, a1->ctx, a2->fd, a2->ctx);
+
+ return a1->fd == a2->fd && a1->ctx == a2->ctx;
+}
+
+/* 2^63 + 2^61 - 2^57 + 2^54 - 2^51 - 2^18 + 1 */
+#define GOLDEN_RATIO_PRIME_64 0x9e37fffffffc0001UL
+
+static inline uint64_t hash_allocators(const void *val, unsigned int bits)
+{
+ uint64_t hash = ((struct intel_allocator *) val)->fd;
+
+ hash = hash * GOLDEN_RATIO_PRIME_64;
+ return hash >> (64 - bits);
+}
+
+static void __free_allocators(void)
+{
+ struct igt_map_entry *pos;
+ struct intel_allocator *ial;
+ int i;
+
+ if (allocators_map) {
+ igt_map_for_each(allocators_map, i, pos) {
+ ial = pos->value;
+ ial->destroy(ial);
+ }
+ }
+
+ igt_map_free(allocators_map);
+}
+
+/**
+ * intel_allocator_init:
+ *
+ * Function initializes the allocators infrastructure. The second call will
+ * override current infra and destroy existing there allocators. It is called
+ * in igt_constructor.
+ **/
+void intel_allocator_init(void)
+{
+ alloc_info("Prepare an allocator infrastructure\n");
+
+ allocator_pid = getpid();
+ alloc_info("Allocator pid: %ld\n", (long) allocator_pid);
+
+ if (allocators_map) {
+ __free_allocators();
+ free(allocators_map);
+ }
+
+ allocators_map = calloc(sizeof(*allocators_map), 1);
+ igt_assert(allocators_map);
+
+ igt_map_init(allocators_map, equal_allocators, hash_allocators, 8);
+
+ channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE);
+}
+
+igt_constructor {
+ intel_allocator_init();
+}
diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h
new file mode 100644
index 00000000..f3747a8b
--- /dev/null
+++ b/lib/intel_allocator.h
@@ -0,0 +1,136 @@
+#ifndef __INTEL_ALLOCATOR_H__
+#define __INTEL_ALLOCATOR_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <pthread.h>
+#include <stdint.h>
+#include <stdatomic.h>
+
+/**
+ * SECTION:intel_allocator
+ * @short_description: igt implementation of allocator
+ * @title: Intel allocator
+ * @include: intel_allocator.h
+ *
+ * # Intel allocator
+ *
+ * Since GPU devices driver has abandoned relocations for newer generations,
+ * we are facing the need to manage addresses in userspace. Intel allocator
+ * supply out of the box mechanisms providing correct virtual addresses.
+ * Specifically, intel_allocator is a multi-threading infrastructure wrapping
+ * a proper single-thread allocator, that can be the one of the following:
+ *
+ * * INTEL_ALLOCATOR_SIMPLE - ported from Mesa, list-based, simple allocator
+ * * INTEL_ALLOCATOR_RANDOM - stateless allocator, that provides random addresses
+ * (sometime in the future the list can grow)
+ *
+ * Usage example:
+ *
+ * |[<!-- language="c" -->
+ * struct object {
+ * uint32_t handle;
+ * uint64_t offset;
+ * uint64_t size;
+ * };
+ *
+ * struct object obj1, obj2;
+ * uint64_t ahnd, startp, endp;
+ * int fd = -1;
+ *
+ * fd = drm_open_driver(DRIVER_INTEL);
+ * ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+ *
+ * obj1.handle = gem_create(4096);
+ * obj2.handle = gem_create(4096);
+ *
+ * // Reserve hole for an object in given address.
+ * // In this example the first possible address.
+ * intel_allocator_get_address_range(ahnd, &startp, &endp);
+ * obj1.offset = startp;
+ * igt_assert(intel_allocator_reserve(ahnd, obj1.handle, 4096, startp));
+ *
+ * // Get the most suitable offset for the object. Prefered way.
+ * obj2.offset = intel_allocator_alloc(ahnd, obj2.handle, 4096, 1 << 13);
+ *
+ * ...
+ *
+ * // Reserved addresses can be only freed by unreserve.
+ * intel_allocator_unreserve(ahnd, obj1.handle, 4096, obj1.offset);
+ * intel_allocator_free(ahnd, obj2.handle);
+ *
+ * gem_close(obj1.handle);
+ * gem_close(obj2.handle);
+ * ]|
+ *
+ */
+
+struct intel_allocator {
+ int fd;
+ uint32_t ctx;
+ uint8_t type;
+ _Atomic(int32_t) refcount;
+ pthread_mutex_t mutex;
+
+ /* allocator's private structure */
+ void *priv;
+
+ void (*get_address_range)(struct intel_allocator *ial,
+ uint64_t *startp, uint64_t *endp);
+ uint64_t (*alloc)(struct intel_allocator *ial, uint32_t handle,
+ uint64_t size, uint64_t alignment);
+ bool (*is_allocated) (struct intel_allocator *ial, uint32_t handle,
+ uint64_t size, uint64_t alignment);
+ bool (*reserve)(struct intel_allocator *ial,
+ uint32_t handle, uint64_t start, uint64_t size);
+ bool (*unreserve)(struct intel_allocator *ial,
+ uint32_t handle, uint64_t start, uint64_t size);
+ bool (*is_reserved) (struct intel_allocator *ial,
+ uint64_t start, uint64_t size);
+ bool (*free)(struct intel_allocator *ial, uint32_t handle);
+
+ void (*destroy)(struct intel_allocator *ial);
+
+ bool (*is_empty)(struct intel_allocator *ial);
+
+ void (*print)(struct intel_allocator *ial, bool full);
+};
+
+void intel_allocator_init(void);
+void intel_allocator_multiprocess_start(void);
+void intel_allocator_multiprocess_stop(void);
+
+uint64_t intel_allocator_open(int fd, uint32_t ctx, uint8_t allocator_type);
+bool intel_allocator_close(uint64_t allocator_handle);
+void intel_allocator_get_address_range(uint64_t allocator_handle,
+ uint64_t *startp, uint64_t *endp);
+uint64_t intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t alignment);
+bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle);
+bool intel_allocator_is_allocated(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t offset);
+bool intel_allocator_reserve(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t offset);
+bool intel_allocator_unreserve(uint64_t allocator_handle, uint32_t handle,
+ uint64_t size, uint64_t offset);
+bool intel_allocator_is_reserved(uint64_t allocator_handle,
+ uint64_t start, uint64_t size);
+bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle,
+ uint32_t handle,
+ uint64_t size, uint64_t offset,
+ bool *is_allocatedp);
+
+void intel_allocator_print(uint64_t allocator_handle);
+
+#define INTEL_ALLOCATOR_NONE 0
+#define INTEL_ALLOCATOR_RANDOM 1
+#define INTEL_ALLOCATOR_SIMPLE 2
+
+static inline uint64_t CANONICAL(uint64_t address)
+{
+ return (int64_t)(address << 16) >> 16;
+}
+
+#define DECANONICAL(offset) (offset & ((1ull << 48) - 1))
+
+#endif
diff --git a/lib/intel_allocator_msgchannel.c b/lib/intel_allocator_msgchannel.c
new file mode 100644
index 00000000..084a977d
--- /dev/null
+++ b/lib/intel_allocator_msgchannel.c
@@ -0,0 +1,182 @@
+#include <sys/types.h>
+#include <sys/ipc.h>
+#include <sys/msg.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include "igt.h"
+#include "intel_allocator_msgchannel.h"
+
+extern __thread pid_t child_tid;
+
+/* ----- SYSVIPC MSGQUEUE ----- */
+
+#define FTOK_IGT_ALLOCATOR_KEY "/tmp/igt.allocator.key"
+#define FTOK_IGT_ALLOCATOR_PROJID 2020
+
+#define ALLOCATOR_REQUEST 1
+
+struct msgqueue_data {
+ key_t key;
+ int queue;
+};
+
+struct msgqueue_buf {
+ long mtype;
+ union {
+ struct alloc_req request;
+ struct alloc_resp response;
+ } data;
+};
+
+static void msgqueue_init(struct msg_channel *channel)
+{
+ struct msgqueue_data *msgdata;
+ struct msqid_ds qstat;
+ key_t key;
+ int fd, queue;
+
+ igt_debug("Init msgqueue\n");
+
+ /* Create ftok key only if not exists */
+ fd = open(FTOK_IGT_ALLOCATOR_KEY, O_CREAT | O_EXCL | O_WRONLY, 0600);
+ igt_assert(fd >= 0 || errno == EEXIST);
+ if (fd >= 0)
+ close(fd);
+
+ key = ftok(FTOK_IGT_ALLOCATOR_KEY, FTOK_IGT_ALLOCATOR_PROJID);
+ igt_assert(key != -1);
+ igt_debug("Queue key: %x\n", (int) key);
+
+ queue = msgget(key, 0);
+ if (queue != -1) {
+ igt_assert(msgctl(queue, IPC_STAT, &qstat) == 0);
+ igt_debug("old messages: %lu\n", qstat.msg_qnum);
+ igt_assert(msgctl(queue, IPC_RMID, NULL) == 0);
+ }
+
+ queue = msgget(key, IPC_CREAT);
+ igt_debug("msg queue: %d\n", queue);
+
+ msgdata = calloc(1, sizeof(*msgdata));
+ igt_assert(msgdata);
+ msgdata->key = key;
+ msgdata->queue = queue;
+ channel->priv = msgdata;
+}
+
+static void msgqueue_deinit(struct msg_channel *channel)
+{
+ struct msgqueue_data *msgdata = channel->priv;
+
+ igt_debug("Deinit msgqueue\n");
+ msgctl(msgdata->queue, IPC_RMID, NULL);
+ free(channel->priv);
+}
+
+static int msgqueue_send_req(struct msg_channel *channel,
+ struct alloc_req *request)
+{
+ struct msgqueue_data *msgdata = channel->priv;
+ struct msgqueue_buf buf = {0};
+ int ret;
+
+ buf.mtype = ALLOCATOR_REQUEST;
+ buf.data.request.request_type = 1;
+ memcpy(&buf.data.request, request, sizeof(*request));
+
+retry:
+ ret = msgsnd(msgdata->queue, &buf, sizeof(buf) - sizeof(long), 0);
+ if (ret == -1 && errno == EINTR)
+ goto retry;
+
+ if (ret == -1)
+ igt_warn("Error: %s\n", strerror(errno));
+
+ return ret;
+}
+
+static int msgqueue_recv_req(struct msg_channel *channel,
+ struct alloc_req *request)
+{
+ struct msgqueue_data *msgdata = channel->priv;
+ struct msgqueue_buf buf = {0};
+ int ret, size = sizeof(buf) - sizeof(long);
+
+retry:
+ ret = msgrcv(msgdata->queue, &buf, size, ALLOCATOR_REQUEST, 0);
+ if (ret == -1 && errno == EINTR)
+ goto retry;
+
+ if (ret == size)
+ memcpy(request, &buf.data.request, sizeof(*request));
+ else if (ret == -1)
+ igt_warn("Error: %s\n", strerror(errno));
+
+ return ret;
+}
+
+static int msgqueue_send_resp(struct msg_channel *channel,
+ struct alloc_resp *response)
+{
+ struct msgqueue_data *msgdata = channel->priv;
+ struct msgqueue_buf buf = {0};
+ int ret;
+
+ buf.mtype = response->tid;
+ memcpy(&buf.data.response, response, sizeof(*response));
+
+retry:
+ ret = msgsnd(msgdata->queue, &buf, sizeof(buf) - sizeof(long), 0);
+ if (ret == -1 && errno == EINTR)
+ goto retry;
+
+ if (ret == -1)
+ igt_warn("Error: %s\n", strerror(errno));
+
+ return ret;
+}
+
+static int msgqueue_recv_resp(struct msg_channel *channel,
+ struct alloc_resp *response)
+{
+ struct msgqueue_data *msgdata = channel->priv;
+ struct msgqueue_buf buf = {0};
+ int ret, size = sizeof(buf) - sizeof(long);
+
+retry:
+ ret = msgrcv(msgdata->queue, &buf, sizeof(buf) - sizeof(long),
+ response->tid, 0);
+ if (ret == -1 && errno == EINTR)
+ goto retry;
+
+ if (ret == size)
+ memcpy(response, &buf.data.response, sizeof(*response));
+ else if (ret == -1)
+ igt_warn("Error: %s\n", strerror(errno));
+
+ return ret;
+}
+
+static struct msg_channel msgqueue_channel = {
+ .priv = NULL,
+ .init = msgqueue_init,
+ .deinit = msgqueue_deinit,
+ .send_req = msgqueue_send_req,
+ .recv_req = msgqueue_recv_req,
+ .send_resp = msgqueue_send_resp,
+ .recv_resp = msgqueue_recv_resp,
+};
+
+struct msg_channel *intel_allocator_get_msgchannel(enum msg_channel_type type)
+{
+ struct msg_channel *channel = NULL;
+
+ switch (type) {
+ case CHANNEL_SYSVIPC_MSGQUEUE:
+ channel = &msgqueue_channel;
+ }
+
+ igt_assert(channel);
+
+ return channel;
+}
diff --git a/lib/intel_allocator_msgchannel.h b/lib/intel_allocator_msgchannel.h
new file mode 100644
index 00000000..ab46d9ea
--- /dev/null
+++ b/lib/intel_allocator_msgchannel.h
@@ -0,0 +1,140 @@
+#ifndef __INTEL_ALLOCATOR_MSGCHANNEL_H__
+#define __INTEL_ALLOCATOR_MSGCHANNEL_H__
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdint.h>
+
+enum reqtype {
+ REQ_STOP,
+ REQ_OPEN,
+ REQ_CLOSE,
+ REQ_ADDRESS_RANGE,
+ REQ_ALLOC,
+ REQ_FREE,
+ REQ_IS_ALLOCATED,
+ REQ_RESERVE,
+ REQ_UNRESERVE,
+ REQ_RESERVE_IF_NOT_ALLOCATED,
+ REQ_IS_RESERVED,
+};
+
+enum resptype {
+ RESP_OPEN,
+ RESP_CLOSE,
+ RESP_ADDRESS_RANGE,
+ RESP_ALLOC,
+ RESP_FREE,
+ RESP_IS_ALLOCATED,
+ RESP_RESERVE,
+ RESP_UNRESERVE,
+ RESP_IS_RESERVED,
+ RESP_RESERVE_IF_NOT_ALLOCATED,
+};
+
+struct alloc_req {
+ enum reqtype request_type;
+
+ /* Common */
+ pid_t tid;
+ uint64_t allocator_handle;
+
+ union {
+ struct {
+ int fd;
+ uint32_t ctx;
+ uint8_t allocator_type;
+ } open;
+
+ struct {
+ uint32_t handle;
+ uint64_t size;
+ uint64_t alignment;
+ } alloc;
+
+ struct {
+ uint32_t handle;
+ } free;
+
+ struct {
+ uint32_t handle;
+ uint64_t size;
+ uint64_t offset;
+ } is_allocated;
+
+ struct {
+ uint32_t handle;
+ uint64_t start;
+ uint64_t end;
+ } reserve, unreserve;
+
+ struct {
+ uint64_t start;
+ uint64_t end;
+ } is_reserved;
+
+ };
+};
+
+struct alloc_resp {
+ enum resptype response_type;
+ pid_t tid;
+
+ union {
+ struct {
+ uint64_t allocator_handle;
+ } open;
+
+ struct {
+ bool is_empty;
+ } close;
+
+ struct {
+ uint64_t start;
+ uint64_t end;
+ } address_range;
+
+ struct {
+ uint64_t offset;
+ } alloc;
+
+ struct {
+ bool freed;
+ } free;
+
+ struct {
+ bool allocated;
+ } is_allocated;
+
+ struct {
+ bool reserved;
+ } reserve, is_reserved;
+
+ struct {
+ bool unreserved;
+ } unreserve;
+
+ struct {
+ bool allocated;
+ bool reserved;
+ } reserve_if_not_allocated;
+ };
+};
+
+struct msg_channel {
+ void *priv;
+ void (*init)(struct msg_channel *channel);
+ void (*deinit)(struct msg_channel *channel);
+ int (*send_req)(struct msg_channel *channel, struct alloc_req *request);
+ int (*recv_req)(struct msg_channel *channel, struct alloc_req *request);
+ int (*send_resp)(struct msg_channel *channel, struct alloc_resp *response);
+ int (*recv_resp)(struct msg_channel *channel, struct alloc_resp *response);
+};
+
+enum msg_channel_type {
+ CHANNEL_SYSVIPC_MSGQUEUE
+};
+
+struct msg_channel *intel_allocator_get_msgchannel(enum msg_channel_type type);
+
+#endif
diff --git a/lib/intel_allocator_simple.c b/lib/intel_allocator_simple.c
index 1f52db3f..1d0e117d 100644
--- a/lib/intel_allocator_simple.c
+++ b/lib/intel_allocator_simple.c
@@ -82,8 +82,6 @@ struct intel_allocator_record {
#define simple_vma_foreach_hole_safe_rev(_hole, _heap, _tmp) \
igt_list_for_each_entry_safe_reverse(_hole, _tmp, &(_heap)->holes, link)
-#define DECANONICAL(offset) (offset & ((1ull << 48) - 1))
-
static uint64_t get_bias(int fd)
{
(void) fd;
diff --git a/lib/meson.build b/lib/meson.build
index 484d3c7b..7a322a44 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -32,6 +32,10 @@ lib_sources = [
'igt_vgem.c',
'igt_x86.c',
'instdone.c',
+ 'intel_allocator.c',
+ 'intel_allocator_msgchannel.c',
+ 'intel_allocator_random.c',
+ 'intel_allocator_simple.c',
'intel_batchbuffer.c',
'intel_bufops.c',
'intel_chipset.c',
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 07/23] lib/intel_allocator: Try to stop smoothly instead of deinit
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (5 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 06/23] lib/intel_allocator: Add intel_allocator core Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 08/23] lib/intel_allocator_msgchannel: Scale to 4k of parallel clients Zbigniew Kempczyński
` (19 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
Avoid race when stop was send to allocator thread. We wait around
100 ms to give thread chance to stop smoothly instead of removing
queue and enforcing exiting all blocked message syscalls.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_allocator.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
index b0ae1d8b..ee64a418 100644
--- a/lib/intel_allocator.c
+++ b/lib/intel_allocator.c
@@ -71,6 +71,7 @@ static struct igt_map *allocators_map;
static pthread_mutex_t map_mutex = PTHREAD_MUTEX_INITIALIZER;
static bool multiprocess;
static pthread_t allocator_thread;
+static bool allocator_thread_running;
static bool warn_if_not_empty;
@@ -463,6 +464,8 @@ static void *allocator_thread_loop(void *data)
(long) allocator_pid, (long) gettid());
alloc_info("Entering allocator loop\n");
+ WRITE_ONCE(allocator_thread_running, true);
+
while (1) {
ret = recv_req(channel, &req);
@@ -496,6 +499,8 @@ static void *allocator_thread_loop(void *data)
}
}
+ WRITE_ONCE(allocator_thread_running, false);
+
return NULL;
}
@@ -533,15 +538,30 @@ void intel_allocator_multiprocess_start(void)
* Function turns off intel_allocator multiprocess mode what means means
* stopping allocator thread and deinitializing its data.
*/
+#define STOP_TIMEOUT_MS 100
void intel_allocator_multiprocess_stop(void)
{
+ int time_left = STOP_TIMEOUT_MS;
+
alloc_info("allocator multiprocess stop\n");
if (multiprocess) {
send_alloc_stop(channel);
- /* Deinit, this should stop all blocked syscalls, if any */
- channel->deinit(channel);
- pthread_join(allocator_thread, NULL);
+
+ /* We prefer joining thread when it is stopped */
+ while (time_left-- > 0 && READ_ONCE(allocator_thread_running))
+ usleep(1000); /* coarse calculation */
+
+ /* Thread has stuck somewhere */
+ if (READ_ONCE(allocator_thread_running)) {
+ /* Deinit, this should stop all blocked syscalls, if any */
+ channel->deinit(channel);
+ pthread_join(allocator_thread, NULL);
+ } else {
+ pthread_join(allocator_thread, NULL);
+ channel->deinit(channel);
+ }
+
/* But we're not sure does child will stuck */
kill_children(SIGINT);
igt_waitchildren_timeout(5, "Stopping children");
--
2.26.0
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 08/23] lib/intel_allocator_msgchannel: Scale to 4k of parallel clients
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (6 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 07/23] lib/intel_allocator: Try to stop smoothly instead of deinit Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 09/23] lib/intel_bufops: Removes handle from allocator, change size Zbigniew Kempczyński
` (18 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
When playing with multiprocess mode in allocator we're currently
using sysvipc message queues in blocking mode (request/response).
We can calculate then what is maximum depth for the queue for
requested number of children. Change alters kernel queue depth
to cover 4k users (1 is main thread and 4095 are children).
We're still prone to unlimited wait in allocator thread
(more than 4095 children successfully send the messages)
but we're going to address this later.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Andrzej Turko <andrzej.turko@linux.intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_allocator_msgchannel.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/lib/intel_allocator_msgchannel.c b/lib/intel_allocator_msgchannel.c
index 084a977d..9927e44c 100644
--- a/lib/intel_allocator_msgchannel.c
+++ b/lib/intel_allocator_msgchannel.c
@@ -12,6 +12,7 @@ extern __thread pid_t child_tid;
#define FTOK_IGT_ALLOCATOR_KEY "/tmp/igt.allocator.key"
#define FTOK_IGT_ALLOCATOR_PROJID 2020
+#define MAXQLEN 4096
#define ALLOCATOR_REQUEST 1
@@ -57,6 +58,13 @@ static void msgqueue_init(struct msg_channel *channel)
queue = msgget(key, IPC_CREAT);
igt_debug("msg queue: %d\n", queue);
+ igt_assert(msgctl(queue, IPC_STAT, &qstat) == 0);
+ igt_debug("msg size in bytes: %lu\n", qstat.msg_qbytes);
+ qstat.msg_qbytes = MAXQLEN * sizeof(struct msgqueue_buf);
+ igt_debug("resizing queue to support %d requests\n", MAXQLEN);
+ igt_assert_f(msgctl(queue, IPC_SET, &qstat) == 0,
+ "Couldn't change queue size to %lu\n", qstat.msg_qbytes);
+
msgdata = calloc(1, sizeof(*msgdata));
igt_assert(msgdata);
msgdata->key = key;
--
2.26.0
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 09/23] lib/intel_bufops: Removes handle from allocator, change size
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (7 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 08/23] lib/intel_allocator_msgchannel: Scale to 4k of parallel clients Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 10/23] lib/intel_bufops: Add init with handle and size function Zbigniew Kempczyński
` (17 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
1. When buffer is destroyed we don't know in how many allocators it
was registered. Remove it from any allocator.
2 Additionally buffer size from 32 -> 64 bit was changed to be
consistent with drm code.
3. Remember buffer creation size to avoid recalculation.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_bufops.c | 21 +++++++++++----------
lib/intel_bufops.h | 7 +++++--
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index a1e9ba55..60a818cf 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -709,7 +709,7 @@ static void __intel_buf_init(struct buf_ops *bops,
uint32_t req_tiling, uint32_t compression)
{
uint32_t tiling = req_tiling;
- uint32_t size;
+ uint64_t size;
uint32_t devid;
int tile_width;
int align_h = 1;
@@ -774,6 +774,9 @@ static void __intel_buf_init(struct buf_ops *bops,
size = buf->surface[0].stride * ALIGN(height, align_h);
}
+ /* Store real bo size to avoid mistakes in calculating it again */
+ buf->size = size;
+
if (handle)
buf->handle = handle;
else
@@ -823,8 +826,10 @@ void intel_buf_close(struct buf_ops *bops, struct intel_buf *buf)
igt_assert(bops);
igt_assert(buf);
- if (buf->is_owner)
+ if (buf->is_owner) {
+ intel_allocator_remove_handle(bops->fd, buf->handle);
gem_close(bops->fd, buf->handle);
+ }
}
/**
@@ -999,8 +1004,8 @@ void intel_buf_flush_and_unmap(struct intel_buf *buf)
void intel_buf_print(const struct intel_buf *buf)
{
igt_info("[name: %s]\n", buf->name);
- igt_info("[%u]: w: %u, h: %u, stride: %u, size: %u, bo-size: %u, "
- "bpp: %u, tiling: %u, compress: %u\n",
+ igt_info("[%u]: w: %u, h: %u, stride: %u, size: %" PRIx64
+ ", bo-size: %" PRIx64 ", bpp: %u, tiling: %u, compress: %u\n",
buf->handle, intel_buf_width(buf), intel_buf_height(buf),
buf->surface[0].stride, buf->surface[0].size,
intel_buf_bo_size(buf), buf->bpp,
@@ -1206,13 +1211,9 @@ static void idempotency_selftest(struct buf_ops *bops, uint32_t tiling)
buf_ops_set_software_tiling(bops, tiling, false);
}
-uint32_t intel_buf_bo_size(const struct intel_buf *buf)
+uint64_t intel_buf_bo_size(const struct intel_buf *buf)
{
- int offset = CCS_OFFSET(buf) ?: buf->surface[0].size;
- int ccs_size =
- buf->compression ? CCS_SIZE(buf->bops->intel_gen, buf) : 0;
-
- return offset + ccs_size;
+ return buf->size;
}
static struct buf_ops *__buf_ops_create(int fd, bool check_idempotency)
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 8debe7f2..5619fc6f 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -9,10 +9,13 @@ struct buf_ops;
#define INTEL_BUF_INVALID_ADDRESS (-1ull)
#define INTEL_BUF_NAME_MAXSIZE 32
+#define INVALID_ADDR(x) ((x) == INTEL_BUF_INVALID_ADDRESS)
+
struct intel_buf {
struct buf_ops *bops;
bool is_owner;
uint32_t handle;
+ uint64_t size;
uint32_t tiling;
uint32_t bpp;
uint32_t compression;
@@ -23,7 +26,7 @@ struct intel_buf {
struct {
uint32_t offset;
uint32_t stride;
- uint32_t size;
+ uint64_t size;
} surface[2];
struct {
uint32_t offset;
@@ -88,7 +91,7 @@ intel_buf_ccs_height(int gen, const struct intel_buf *buf)
return DIV_ROUND_UP(intel_buf_height(buf), 512) * 32;
}
-uint32_t intel_buf_bo_size(const struct intel_buf *buf);
+uint64_t intel_buf_bo_size(const struct intel_buf *buf);
struct buf_ops *buf_ops_create(int fd);
struct buf_ops *buf_ops_create_with_selftest(int fd);
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 10/23] lib/intel_bufops: Add init with handle and size function
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (8 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 09/23] lib/intel_bufops: Removes handle from allocator, change size Zbigniew Kempczyński
@ 2020-10-23 12:41 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 11/23] lib/intel_batchbuffer: Integrate intel_bb with allocator Zbigniew Kempczyński
` (16 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:41 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
For some cases (fb with compression) fb size is bigger than calculated
intel_buf what lead to execbuf failure when allocator is used
along with EXEC_OBJECT_PINNED flag set for all objects.
We need to create intel_buf with size equal to fb so new function
in which we pass handle and size is required.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_bufops.c | 33 ++++++++++++++++++++++++++++-----
lib/intel_bufops.h | 7 +++++++
2 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 60a818cf..c0d2ea4f 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -706,7 +706,8 @@ static void __intel_buf_init(struct buf_ops *bops,
uint32_t handle,
struct intel_buf *buf,
int width, int height, int bpp, int alignment,
- uint32_t req_tiling, uint32_t compression)
+ uint32_t req_tiling, uint32_t compression,
+ uint64_t bo_size)
{
uint32_t tiling = req_tiling;
uint64_t size;
@@ -756,7 +757,7 @@ static void __intel_buf_init(struct buf_ops *bops,
buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32);
buf->ccs[0].stride = aux_width;
- size = buf->ccs[0].offset + aux_width * aux_height;
+ size = max(bo_size, buf->ccs[0].offset + aux_width * aux_height);
} else {
if (tiling) {
devid = intel_get_drm_devid(bops->fd);
@@ -771,7 +772,7 @@ static void __intel_buf_init(struct buf_ops *bops,
buf->tiling = tiling;
buf->bpp = bpp;
- size = buf->surface[0].stride * ALIGN(height, align_h);
+ size = max(bo_size, buf->surface[0].stride * ALIGN(height, align_h));
}
/* Store real bo size to avoid mistakes in calculating it again */
@@ -807,7 +808,7 @@ void intel_buf_init(struct buf_ops *bops,
uint32_t tiling, uint32_t compression)
{
__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
- tiling, compression);
+ tiling, compression, 0);
intel_buf_set_ownership(buf, true);
}
@@ -858,7 +859,7 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
uint32_t req_tiling, uint32_t compression)
{
__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
- req_tiling, compression);
+ req_tiling, compression, 0);
}
/**
@@ -927,6 +928,28 @@ struct intel_buf *intel_buf_create_using_handle(struct buf_ops *bops,
return buf;
}
+struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
+ uint32_t handle,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling,
+ uint32_t compression,
+ uint64_t size)
+{
+ struct intel_buf *buf;
+
+ igt_assert(bops);
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ __intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
+ req_tiling, compression, size);
+
+ return buf;
+}
+
+
/**
* intel_buf_destroy
* @buf: intel_buf
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 5619fc6f..54480bff 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -139,6 +139,13 @@ struct intel_buf *intel_buf_create_using_handle(struct buf_ops *bops,
uint32_t req_tiling,
uint32_t compression);
+struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
+ uint32_t handle,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling,
+ uint32_t compression,
+ uint64_t size);
void intel_buf_destroy(struct intel_buf *buf);
void *intel_buf_cpu_map(struct intel_buf *buf, bool write);
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 11/23] lib/intel_batchbuffer: Integrate intel_bb with allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (9 preceding siblings ...)
2020-10-23 12:41 ` [igt-dev] [PATCH i-g-t v3 10/23] lib/intel_bufops: Add init with handle and size function Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 12/23] lib/intel_batchbuffer: Add tracking intel_buf to intel_bb Zbigniew Kempczyński
` (15 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
v2: fix leak in cache tree (Dominik)
v3: remove decanonisation of addresses and truncating gtt_size
for non ppgtt gens (Zbigniew)
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_batchbuffer.c | 497 ++++++++++++++++++++++++++++------------
lib/intel_batchbuffer.h | 23 +-
2 files changed, 370 insertions(+), 150 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index fc73495c..22d27376 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -49,7 +49,6 @@
#include "media_spin.h"
#include "gpgpu_fill.h"
#include "igt_aux.h"
-#include "igt_rand.h"
#include "i830_reg.h"
#include "huc_copy.h"
#include <glib.h>
@@ -1206,23 +1205,9 @@ static void __reallocate_objects(struct intel_bb *ibb)
}
}
-/*
- * gen8_canonical_addr
- * Used to convert any address into canonical form, i.e. [63:48] == [47].
- * Based on kernel's sign_extend64 implementation.
- * @address - a virtual address
- */
-#define GEN8_HIGH_ADDRESS_BIT 47
-static uint64_t gen8_canonical_addr(uint64_t address)
-{
- int shift = 63 - GEN8_HIGH_ADDRESS_BIT;
-
- return (int64_t)(address << shift) >> shift;
-}
-
static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
uint32_t handle,
- uint32_t size,
+ uint64_t size,
uint32_t alignment)
{
uint64_t offset;
@@ -1230,33 +1215,77 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
if (ibb->enforce_relocs)
return 0;
- /* randomize the address, we try to avoid relocations */
- offset = hars_petruska_f54_1_random64(&ibb->prng);
- offset += 256 << 10; /* Keep the low 256k clear, for negative deltas */
- offset &= ibb->gtt_size - 1;
- offset &= ~(ibb->alignment - 1);
- offset = gen8_canonical_addr(offset);
+ offset = intel_allocator_alloc(ibb->allocator_handle,
+ handle, size, alignment);
- return offset;
+ return CANONICAL(offset);
}
/**
- * intel_bb_create:
+ * __intel_bb_create:
* @i915: drm fd
+ * @ctx: context
* @size: size of the batchbuffer
+ * @do_relocs: use relocations or allocator
+ * @allocator_type: allocator type, must be INTEL_ALLOCATOR_NONE for relocations
+ *
+ * intel-bb assumes it will work in one of two modes - with relocations or
+ * with using allocator (currently RANDOM and SIMPLE are implemented).
+ * Some description is required to describe how they maintain the addresses.
+ *
+ * Before entering into each scenarios generic rule is intel-bb keeps objects
+ * and their offsets in the internal cache and reuses in subsequent execs.
+ *
+ * 1. intel-bb with relocations
+ *
+ * Creating new intel-bb adds handle to cache implicitly and sets its address
+ * to 0. Objects added to intel-bb later also have address 0 set for first run.
+ * After calling execbuf cache is altered with new addresses. As intel-bb
+ * works in reloc mode addresses are only suggestion to the driver and we
+ * cannot be sure they won't change at next exec.
+ *
+ * 2. with allocator
+ *
+ * This mode is valid only for ppgtt. Addresses are acquired from allocator
+ * and softpinned. intel-bb cache must be then coherent with allocator
+ * (simple is coherent, random is not due to fact we don't keep its state).
+ * When we do intel-bb reset with purging cache it has to reacquire addresses
+ * from allocator (allocator should return same address - what is true for
+ * simple allocator and false for random as mentioned before).
+ *
+ * If we do reset without purging caches we use addresses from intel-bb cache
+ * during execbuf objects construction.
*
* Returns:
*
* Pointer the intel_bb, asserts on failure.
*/
static struct intel_bb *
-__intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs)
+__intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
+ uint8_t allocator_type)
{
+ struct drm_i915_gem_exec_object2 *object;
struct intel_bb *ibb = calloc(1, sizeof(*ibb));
- uint64_t gtt_size;
igt_assert(ibb);
+ ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
+
+ /*
+ * If we don't have full ppgtt driver can change our addresses
+ * so allocator is useless in this case. Just enforce relocations
+ * for such gens and don't use allocator at all.
+ */
+ if (!ibb->uses_full_ppgtt) {
+ do_relocs = true;
+ allocator_type = INTEL_ALLOCATOR_NONE;
+ }
+
+ if (!do_relocs)
+ ibb->allocator_handle = intel_allocator_open(i915, ctx, allocator_type);
+ else
+ igt_assert(allocator_type == INTEL_ALLOCATOR_NONE);
+ ibb->allocator_type = allocator_type;
ibb->i915 = i915;
ibb->devid = intel_get_drm_devid(i915);
ibb->gen = intel_gen(ibb->devid);
@@ -1268,41 +1297,43 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs)
ibb->batch = calloc(1, size);
igt_assert(ibb->batch);
ibb->ptr = ibb->batch;
- ibb->prng = (uint32_t) to_user_pointer(ibb);
ibb->fence = -1;
- gtt_size = gem_aperture_size(i915);
- if (!gem_uses_full_ppgtt(i915))
- gtt_size /= 2;
- if ((gtt_size - 1) >> 32) {
+ ibb->gtt_size = gem_aperture_size(i915);
+ if ((ibb->gtt_size - 1) >> 32)
ibb->supports_48b_address = true;
- /*
- * Until we develop IGT address allocator we workaround
- * playing with canonical addresses with 47-bit set to 1
- * just by limiting gtt size to 46-bit when gtt is 47 or 48
- * bit size. Current interface doesn't pass bo size, so
- * limiting to 46 bit make us sure we won't enter to
- * addresses with 47-bit set (we use 32-bit size now so
- * still we fit 47-bit address space).
- */
- if (gtt_size & (3ull << 47))
- gtt_size = (1ull << 46);
- }
- ibb->gtt_size = gtt_size;
-
- ibb->batch_offset = __intel_bb_get_offset(ibb,
- ibb->handle,
- ibb->size,
- ibb->alignment);
- intel_bb_add_object(ibb, ibb->handle, ibb->size,
- ibb->batch_offset, false);
+ object = intel_bb_add_object(ibb, ibb->handle, ibb->size,
+ INTEL_BUF_INVALID_ADDRESS, ibb->alignment,
+ false);
+ ibb->batch_offset = object->offset;
ibb->refcount = 1;
return ibb;
}
+/**
+ * intel_bb_create_full:
+ * @i915: drm fd
+ * @ctx: context
+ * @size: size of the batchbuffer
+ * @allocator_type: allocator type, SIMPLE, RANDOM, ...
+ *
+ * Creates bb with context passed in @ctx, size in @size and allocator type
+ * in @allocator_type. Relocations are set to false because IGT allocator
+ * is not used in that case.
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx, uint32_t size,
+ uint8_t allocator_type)
+{
+ return __intel_bb_create(i915, ctx, size, false, allocator_type);
+}
+
/**
* intel_bb_create:
* @i915: drm fd
@@ -1316,7 +1347,7 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs)
*/
struct intel_bb *intel_bb_create(int i915, uint32_t size)
{
- return __intel_bb_create(i915, 0, size, false);
+ return __intel_bb_create(i915, 0, size, false, INTEL_ALLOCATOR_SIMPLE);
}
/**
@@ -1334,7 +1365,7 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
struct intel_bb *
intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size)
{
- return __intel_bb_create(i915, ctx, size, false);
+ return __intel_bb_create(i915, ctx, size, false, INTEL_ALLOCATOR_SIMPLE);
}
/**
@@ -1351,7 +1382,7 @@ intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size)
*/
struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
{
- return __intel_bb_create(i915, 0, size, true);
+ return __intel_bb_create(i915, 0, size, true, INTEL_ALLOCATOR_NONE);
}
/**
@@ -1370,7 +1401,7 @@ struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
struct intel_bb *
intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size)
{
- return __intel_bb_create(i915, ctx, size, true);
+ return __intel_bb_create(i915, ctx, size, true, INTEL_ALLOCATOR_NONE);
}
static void __intel_bb_destroy_relocations(struct intel_bb *ibb)
@@ -1424,6 +1455,10 @@ void intel_bb_destroy(struct intel_bb *ibb)
__intel_bb_destroy_objects(ibb);
__intel_bb_destroy_cache(ibb);
+ if (ibb->allocator_type != INTEL_ALLOCATOR_NONE) {
+ intel_allocator_free(ibb->allocator_handle, ibb->handle);
+ intel_allocator_close(ibb->allocator_handle);
+ }
gem_close(ibb->i915, ibb->handle);
if (ibb->fence >= 0)
@@ -1440,6 +1475,7 @@ void intel_bb_destroy(struct intel_bb *ibb)
*
* Recreate batch bo when there's no additional reference.
*/
+
void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
{
uint32_t i;
@@ -1463,28 +1499,32 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
__intel_bb_destroy_objects(ibb);
__reallocate_objects(ibb);
- if (purge_objects_cache) {
+ if (purge_objects_cache)
__intel_bb_destroy_cache(ibb);
+
+ /*
+ * When we use allocators we're in no-reloc mode so we have to free
+ * and reacquire offset (ibb->handle can change in multiprocess
+ * environment). We also have to remove and add it again to
+ * objects and cache tree.
+ */
+ if (ibb->allocator_type != INTEL_ALLOCATOR_NONE && !purge_objects_cache)
+ intel_bb_remove_object(ibb, ibb->handle, ibb->batch_offset,
+ ibb->size);
+
+ gem_close(ibb->i915, ibb->handle);
+ ibb->handle = gem_create(ibb->i915, ibb->size);
+
+ /* Keep address for bb in reloc mode and RANDOM allocator */
+ if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE)
ibb->batch_offset = __intel_bb_get_offset(ibb,
ibb->handle,
ibb->size,
ibb->alignment);
- } else {
- struct drm_i915_gem_exec_object2 *object;
-
- object = intel_bb_find_object(ibb, ibb->handle);
- ibb->batch_offset = object ? object->offset :
- __intel_bb_get_offset(ibb,
- ibb->handle,
- ibb->size,
- ibb->alignment);
- }
-
- gem_close(ibb->i915, ibb->handle);
- ibb->handle = gem_create(ibb->i915, ibb->size);
intel_bb_add_object(ibb, ibb->handle, ibb->size,
- ibb->batch_offset, false);
+ CANONICAL(ibb->batch_offset),
+ ibb->alignment, false);
ibb->ptr = ibb->batch;
memset(ibb->batch, 0, ibb->size);
}
@@ -1523,8 +1563,8 @@ void intel_bb_print(struct intel_bb *ibb)
ibb->i915, ibb->gen, ibb->devid, ibb->debug);
igt_info("handle: %u, size: %u, batch: %p, ptr: %p\n",
ibb->handle, ibb->size, ibb->batch, ibb->ptr);
- igt_info("prng: %u, gtt_size: %" PRIu64 ", supports 48bit: %d\n",
- ibb->prng, ibb->gtt_size, ibb->supports_48b_address);
+ igt_info("gtt_size: %" PRIu64 ", supports 48bit: %d\n",
+ ibb->gtt_size, ibb->supports_48b_address);
igt_info("ctx: %u\n", ibb->ctx);
igt_info("root: %p\n", ibb->root);
igt_info("objects: %p, num_objects: %u, allocated obj: %u\n",
@@ -1598,7 +1638,7 @@ __add_to_cache(struct intel_bb *ibb, uint32_t handle)
if (*found == object) {
memset(object, 0, sizeof(*object));
object->handle = handle;
- object->alignment = ibb->alignment;
+ object->offset = INTEL_BUF_INVALID_ADDRESS;
} else {
free(object);
object = *found;
@@ -1607,6 +1647,25 @@ __add_to_cache(struct intel_bb *ibb, uint32_t handle)
return object;
}
+static bool __remove_from_cache(struct intel_bb *ibb, uint32_t handle)
+{
+ struct drm_i915_gem_exec_object2 **found, *object;
+
+ object = intel_bb_find_object(ibb, handle);
+ if (!object) {
+ igt_warn("Object: handle: %u not found\n", handle);
+ return false;
+ }
+
+ found = tdelete((void *) object, &ibb->root, __compare_objects);
+ if (!found)
+ return false;
+
+ free(object);
+
+ return true;
+}
+
static int __compare_handles(const void *p1, const void *p2)
{
return (int) (*(int32_t *) p1 - *(int32_t *) p2);
@@ -1630,12 +1689,54 @@ static void __add_to_objects(struct intel_bb *ibb,
}
}
+static void __remove_from_objects(struct intel_bb *ibb,
+ struct drm_i915_gem_exec_object2 *object)
+{
+ uint32_t i, **handle, *to_free;
+ bool found = false;
+
+ for (i = 0; i < ibb->num_objects; i++) {
+ if (ibb->objects[i] == object) {
+ found = true;
+ break;
+ }
+ }
+
+ /*
+ * When we reset bb (without purging) we have:
+ * 1. cache which contains all cached objects
+ * 2. objects array which contains only bb object (cleared in reset
+ * path with bb object added at the end)
+ * So !found is normal situation and no warning is added here.
+ */
+ if (!found)
+ return;
+
+ ibb->num_objects--;
+ if (i < ibb->num_objects)
+ memmove(&ibb->objects[i], &ibb->objects[i + 1],
+ sizeof(object) * (ibb->num_objects - i));
+
+ handle = tfind((void *) &object->handle,
+ &ibb->current, __compare_handles);
+ if (!handle) {
+ igt_warn("Object %u doesn't exist in the tree, can't remove",
+ object->handle);
+ return;
+ }
+
+ to_free = *handle;
+ tdelete((void *) &object->handle, &ibb->current, __compare_handles);
+ free(to_free);
+}
+
/**
* intel_bb_add_object:
* @ibb: pointer to intel_bb
* @handle: which handle to add to objects array
* @size: object size
* @offset: presumed offset of the object when no relocation is enforced
+ * @alignment: alignment of the object, if 0 it will be set to page size
* @write: does a handle is a render target
*
* Function adds or updates execobj slot in bb objects array and
@@ -1643,23 +1744,73 @@ static void __add_to_objects(struct intel_bb *ibb,
* be marked with EXEC_OBJECT_WRITE flag.
*/
struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
- uint64_t offset, bool write)
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
+ uint64_t offset, uint64_t alignment, bool write)
{
struct drm_i915_gem_exec_object2 *object;
+ igt_assert(INVALID_ADDR(offset) || alignment == 0
+ || ALIGN(offset, alignment) == offset);
+
object = __add_to_cache(ibb, handle);
+ object->alignment = alignment ?: 4096;
__add_to_objects(ibb, object);
- /* Limit current offset to gtt size */
+ /*
+ * If object->offset == INVALID_ADDRESS we added freshly object to the
+ * cache. In that case we have two choices:
+ * a) get new offset (passed offset was invalid)
+ * b) use offset passed in the call (valid)
+ */
+ if (INVALID_ADDR(object->offset)) {
+ if (INVALID_ADDR(offset)) {
+ offset = __intel_bb_get_offset(ibb, handle, size,
+ object->alignment);
+ } else {
+ offset = CANONICAL(offset & (ibb->gtt_size - 1));
+
+ /*
+ * For simple allocator check entry consistency
+ * - reserve if it is not already allocated.
+ */
+ if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE) {
+ bool allocated, reserved;
+
+ reserved = intel_allocator_reserve_if_not_allocated(ibb->allocator_handle,
+ handle, size, offset,
+ &allocated);
+ igt_assert_f(allocated || reserved,
+ "Can't get offset, allocated: %d, reserved: %d\n",
+ allocated, reserved);
+ }
+ }
+ } else {
+ /*
+ * This assertion makes sense only when we have to be consistent
+ * with underlying allocator. For relocations and when !ppgtt
+ * we can expect addresses passed by the user can be moved
+ * within the driver.
+ */
+ if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE)
+ igt_assert_f(object->offset == CANONICAL(offset),
+ "(pid: %ld) handle: %u, offset not match: %" PRIx64 " <> %" PRIx64 "\n",
+ (long) getpid(), handle,
+ (uint64_t) object->offset,
+ CANONICAL(offset));
+ }
+
object->offset = offset;
- if (offset != INTEL_BUF_INVALID_ADDRESS)
+
+ /* Limit current offset to gtt size */
+ if (offset != INTEL_BUF_INVALID_ADDRESS) {
object->offset = gen8_canonical_addr(offset & (ibb->gtt_size - 1));
- if (object->offset == INTEL_BUF_INVALID_ADDRESS)
+
+ } else {
object->offset = __intel_bb_get_offset(ibb,
handle, size,
object->alignment);
+ }
if (write)
object->flags |= EXEC_OBJECT_WRITE;
@@ -1667,40 +1818,95 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
if (ibb->supports_48b_address)
object->flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ if (ibb->uses_full_ppgtt && ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE)
+ object->flags |= EXEC_OBJECT_PINNED;
+
return object;
}
-struct drm_i915_gem_exec_object2 *
-intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write)
+bool intel_bb_remove_object(struct intel_bb *ibb, uint32_t handle,
+ uint64_t offset, uint64_t size)
{
- struct drm_i915_gem_exec_object2 *obj;
+ struct drm_i915_gem_exec_object2 *object;
+ bool is_reserved;
- obj = intel_bb_add_object(ibb, buf->handle,
- intel_buf_bo_size(buf),
- buf->addr.offset, write);
+ object = intel_bb_find_object(ibb, handle);
+ if (!object)
+ return false;
- /* For compressed surfaces ensure address is aligned to 64KB */
- if (ibb->gen >= 12 && buf->compression) {
- obj->offset &= ~(0x10000 - 1);
- obj->alignment = 0x10000;
+ if (ibb->allocator_type != INTEL_ALLOCATOR_NONE) {
+ intel_allocator_free(ibb->allocator_handle, handle);
+ is_reserved = intel_allocator_is_reserved(ibb->allocator_handle,
+ size, offset);
+ if (is_reserved)
+ intel_allocator_unreserve(ibb->allocator_handle, handle,
+ size, offset);
}
- /* For gen3 ensure tiled buffers are aligned to power of two size */
- if (ibb->gen == 3 && buf->tiling) {
- uint64_t alignment = 1024 * 1024;
+ __remove_from_objects(ibb, object);
+ __remove_from_cache(ibb, handle);
- while (alignment < buf->surface[0].size)
- alignment <<= 1;
- obj->offset &= ~(alignment - 1);
- obj->alignment = alignment;
+ return true;
+}
+
+static struct drm_i915_gem_exec_object2 *
+__intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf,
+ uint64_t alignment, bool write)
+{
+ struct drm_i915_gem_exec_object2 *obj;
+
+ igt_assert(ALIGN(alignment, 4096) == alignment);
+
+ if (!alignment) {
+ alignment = 0x1000;
+
+ if (ibb->gen >= 12 && buf->compression)
+ alignment = 0x10000;
+
+ /* For gen3 ensure tiled buffers are aligned to power of two size */
+ if (ibb->gen == 3 && buf->tiling) {
+ alignment = 1024 * 1024;
+
+ while (alignment < buf->surface[0].size)
+ alignment <<= 1;
+ }
}
- /* Update address in intel_buf buffer */
+ obj = intel_bb_add_object(ibb, buf->handle, intel_buf_bo_size(buf),
+ buf->addr.offset, alignment, write);
buf->addr.offset = obj->offset;
+ if (!ibb->enforce_relocs)
+ obj->alignment = alignment;
+
return obj;
}
+struct drm_i915_gem_exec_object2 *
+intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write)
+{
+ return __intel_bb_add_intel_buf(ibb, buf, 0, write);
+}
+
+struct drm_i915_gem_exec_object2 *
+intel_bb_add_intel_buf_with_alignment(struct intel_bb *ibb, struct intel_buf *buf,
+ uint64_t alignment, bool write)
+{
+ return __intel_bb_add_intel_buf(ibb, buf, alignment, write);
+}
+
+bool intel_bb_remove_intel_buf(struct intel_bb *ibb, struct intel_buf *buf)
+{
+ bool removed = intel_bb_remove_object(ibb, buf->handle,
+ buf->addr.offset,
+ intel_buf_bo_size(buf));
+
+ if (removed)
+ buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
+
+ return removed;
+}
+
struct drm_i915_gem_exec_object2 *
intel_bb_find_object(struct intel_bb *ibb, uint32_t handle)
{
@@ -1708,6 +1914,8 @@ intel_bb_find_object(struct intel_bb *ibb, uint32_t handle)
struct drm_i915_gem_exec_object2 **found;
found = tfind((void *) &object, &ibb->root, __compare_objects);
+ if (!found)
+ return NULL;
return *found;
}
@@ -1718,6 +1926,8 @@ intel_bb_object_set_flag(struct intel_bb *ibb, uint32_t handle, uint64_t flag)
struct drm_i915_gem_exec_object2 object = { .handle = handle };
struct drm_i915_gem_exec_object2 **found;
+ igt_assert_f(ibb->root, "Trying to search in null tree\n");
+
found = tfind((void *) &object, &ibb->root, __compare_objects);
if (!found) {
igt_warn("Trying to set fence on not found handle: %u\n",
@@ -1757,14 +1967,9 @@ intel_bb_object_clear_flag(struct intel_bb *ibb, uint32_t handle, uint64_t flag)
* @write_domain: gem domain bit for the relocation
* @delta: delta value to add to @buffer's gpu address
* @offset: offset within bb to be patched
- * @presumed_offset: address of the object in address space. If -1 is passed
- * then final offset of the object will be randomized (for no-reloc bb) or
- * 0 (for reloc bb, in that case reloc.presumed_offset will be -1). In
- * case address is known it should passed in @presumed_offset (for no-reloc).
*
* Function allocates additional relocation slot in reloc array for a handle.
- * It also implicitly adds handle in the objects array if object doesn't
- * exists but doesn't mark it as a render target.
+ * Object must be previously added to bb.
*/
static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
uint32_t to_handle,
@@ -1779,13 +1984,8 @@ static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
struct drm_i915_gem_exec_object2 *object, *to_object;
uint32_t i;
- if (ibb->enforce_relocs) {
- object = intel_bb_add_object(ibb, handle, 0,
- presumed_offset, false);
- } else {
- object = intel_bb_find_object(ibb, handle);
- igt_assert(object);
- }
+ object = intel_bb_find_object(ibb, handle);
+ igt_assert(object);
/* For ibb we have relocs allocated in chunks */
if (to_handle == ibb->handle) {
@@ -1979,45 +2179,47 @@ static void intel_bb_dump_execbuf(struct intel_bb *ibb,
int i, j;
uint64_t address;
- igt_info("execbuf batch len: %u, start offset: 0x%x, "
- "DR1: 0x%x, DR4: 0x%x, "
- "num clip: %u, clipptr: 0x%llx, "
- "flags: 0x%llx, rsvd1: 0x%llx, rsvd2: 0x%llx\n",
- execbuf->batch_len, execbuf->batch_start_offset,
- execbuf->DR1, execbuf->DR4,
- execbuf->num_cliprects, execbuf->cliprects_ptr,
- execbuf->flags, execbuf->rsvd1, execbuf->rsvd2);
-
- igt_info("execbuf buffer_count: %d\n", execbuf->buffer_count);
+ igt_debug("execbuf [pid: %ld, fd: %d, ctx: %u]\n",
+ (long) getpid(), ibb->i915, ibb->ctx);
+ igt_debug("execbuf batch len: %u, start offset: 0x%x, "
+ "DR1: 0x%x, DR4: 0x%x, "
+ "num clip: %u, clipptr: 0x%llx, "
+ "flags: 0x%llx, rsvd1: 0x%llx, rsvd2: 0x%llx\n",
+ execbuf->batch_len, execbuf->batch_start_offset,
+ execbuf->DR1, execbuf->DR4,
+ execbuf->num_cliprects, execbuf->cliprects_ptr,
+ execbuf->flags, execbuf->rsvd1, execbuf->rsvd2);
+
+ igt_debug("execbuf buffer_count: %d\n", execbuf->buffer_count);
for (i = 0; i < execbuf->buffer_count; i++) {
objects = &((struct drm_i915_gem_exec_object2 *)
from_user_pointer(execbuf->buffers_ptr))[i];
relocs = from_user_pointer(objects->relocs_ptr);
address = objects->offset;
- igt_info(" [%d] handle: %u, reloc_count: %d, reloc_ptr: %p, "
- "align: 0x%llx, offset: 0x%" PRIx64 ", flags: 0x%llx, "
- "rsvd1: 0x%llx, rsvd2: 0x%llx\n",
- i, objects->handle, objects->relocation_count,
- relocs,
- objects->alignment,
- address,
- objects->flags,
- objects->rsvd1, objects->rsvd2);
+ igt_debug(" [%d] handle: %u, reloc_count: %d, reloc_ptr: %p, "
+ "align: 0x%llx, offset: 0x%" PRIx64 ", flags: 0x%llx, "
+ "rsvd1: 0x%llx, rsvd2: 0x%llx\n",
+ i, objects->handle, objects->relocation_count,
+ relocs,
+ objects->alignment,
+ address,
+ objects->flags,
+ objects->rsvd1, objects->rsvd2);
if (objects->relocation_count) {
- igt_info("\texecbuf relocs:\n");
+ igt_debug("\texecbuf relocs:\n");
for (j = 0; j < objects->relocation_count; j++) {
reloc = &relocs[j];
address = reloc->presumed_offset;
- igt_info("\t [%d] target handle: %u, "
- "offset: 0x%llx, delta: 0x%x, "
- "presumed_offset: 0x%" PRIx64 ", "
- "read_domains: 0x%x, "
- "write_domain: 0x%x\n",
- j, reloc->target_handle,
- reloc->offset, reloc->delta,
- address,
- reloc->read_domains,
- reloc->write_domain);
+ igt_debug("\t [%d] target handle: %u, "
+ "offset: 0x%llx, delta: 0x%x, "
+ "presumed_offset: 0x%" PRIx64 ", "
+ "read_domains: 0x%x, "
+ "write_domain: 0x%x\n",
+ j, reloc->target_handle,
+ reloc->offset, reloc->delta,
+ address,
+ reloc->read_domains,
+ reloc->write_domain);
}
}
}
@@ -2060,6 +2262,12 @@ static void print_node(const void *node, VISIT which, int depth)
}
}
+void intel_bb_dump_cache(struct intel_bb *ibb)
+{
+ igt_info("[pid: %ld] dump cache\n", (long) getpid());
+ twalk(ibb->root, print_node);
+}
+
static struct drm_i915_gem_exec_object2 *
create_objects_array(struct intel_bb *ibb)
{
@@ -2086,6 +2294,9 @@ static void update_offsets(struct intel_bb *ibb,
igt_assert(object);
object->offset = objects[i].offset;
+
+ if (i == 0)
+ ibb->batch_offset = object->offset;
}
}
@@ -2197,7 +2408,6 @@ uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle)
{
struct drm_i915_gem_exec_object2 object = { .handle = handle };
struct drm_i915_gem_exec_object2 **found;
- uint64_t address;
igt_assert(ibb);
@@ -2205,12 +2415,7 @@ uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle)
if (!found)
return INTEL_BUF_INVALID_ADDRESS;
- address = (*found)->offset;
-
- if (address == INTEL_BUF_INVALID_ADDRESS)
- return address;
-
- return address & (ibb->gtt_size - 1);
+ return (*found)->offset;
}
/**
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ab1b0c28..029b7e23 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -8,6 +8,7 @@
#include "igt_core.h"
#include "intel_reg.h"
#include "drmtest.h"
+#include "intel_allocator.h"
#define BATCH_SZ 4096
#define BATCH_RESERVED 16
@@ -435,6 +436,9 @@ igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
* Batchbuffer without libdrm dependency
*/
struct intel_bb {
+ uint64_t allocator_handle;
+ uint8_t allocator_type;
+
int i915;
unsigned int gen;
bool debug;
@@ -448,9 +452,9 @@ struct intel_bb {
uint64_t alignment;
int fence;
- uint32_t prng;
uint64_t gtt_size;
bool supports_48b_address;
+ bool uses_full_ppgtt;
uint32_t ctx;
@@ -478,6 +482,8 @@ struct intel_bb {
int32_t refcount;
};
+struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx, uint32_t size,
+ uint8_t allocator_type);
struct intel_bb *intel_bb_create(int i915, uint32_t size);
struct intel_bb *
intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
@@ -504,6 +510,7 @@ void intel_bb_dump(struct intel_bb *ibb, const char *filename);
void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
void intel_bb_set_dump_base64(struct intel_bb *ibb, bool dump);
+/*
static inline uint64_t
intel_bb_set_default_object_alignment(struct intel_bb *ibb, uint64_t alignment)
{
@@ -519,6 +526,7 @@ intel_bb_get_default_object_alignment(struct intel_bb *ibb)
{
return ibb->alignment;
}
+*/
static inline uint32_t intel_bb_offset(struct intel_bb *ibb)
{
@@ -568,11 +576,16 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
}
struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
- uint64_t offset, bool write);
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
+ uint64_t offset, uint64_t alignment, bool write);
+bool intel_bb_remove_object(struct intel_bb *ibb, uint32_t handle,
+ uint64_t offset, uint64_t size);
struct drm_i915_gem_exec_object2 *
intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write);
-
+struct drm_i915_gem_exec_object2 *
+intel_bb_add_intel_buf_with_alignment(struct intel_bb *ibb, struct intel_buf *buf,
+ uint64_t alignment, bool write);
+bool intel_bb_remove_intel_buf(struct intel_bb *ibb, struct intel_buf *buf);
struct drm_i915_gem_exec_object2 *
intel_bb_find_object(struct intel_bb *ibb, uint32_t handle);
@@ -619,6 +632,8 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
uint32_t offset,
uint64_t presumed_offset);
+void intel_bb_dump_cache(struct intel_bb *ibb);
+
void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
uint64_t flags, bool sync);
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 12/23] lib/intel_batchbuffer: Add tracking intel_buf to intel_bb
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (10 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 11/23] lib/intel_batchbuffer: Integrate intel_bb with allocator Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 13/23] lib/intel_aux_pgtable: Get addresses for aux table from an allocator Zbigniew Kempczyński
` (14 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
From now on intel_bb starts tracking added/removed intel_bufs.
We're safe now regardless order of intel_buf close/destroy
or intel_bb destroy paths.
When intel_buf is closed/destroyed first and it was previously added
to intel_bb it calls the code which removes itself from intel_bb.
When intel_bb is destroyed first it goes over all tracked intel_bufs
and clears tracking information and clears previous buffer offset
(it sets to INTEL_BUF_INVALID_ADDRESS).
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_batchbuffer.c | 82 +++++++++++++++++++++++++++++++----------
lib/intel_batchbuffer.h | 5 +++
lib/intel_bufops.c | 15 ++++++--
lib/intel_bufops.h | 6 +++
4 files changed, 85 insertions(+), 23 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 22d27376..da52014c 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1308,6 +1308,8 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
false);
ibb->batch_offset = object->offset;
+ IGT_INIT_LIST_HEAD(&ibb->intel_bufs);
+
ibb->refcount = 1;
return ibb;
@@ -1438,6 +1440,15 @@ static void __intel_bb_destroy_cache(struct intel_bb *ibb)
ibb->root = NULL;
}
+static void __intel_bb_remove_intel_bufs(struct intel_bb *ibb)
+{
+ struct intel_buf *entry, *tmp;
+
+ igt_list_for_each_entry_safe(entry, tmp, &ibb->intel_bufs, link) {
+ intel_bb_remove_intel_buf(ibb, entry);
+ }
+}
+
/**
* intel_bb_destroy:
* @ibb: pointer to intel_bb
@@ -1454,6 +1465,7 @@ void intel_bb_destroy(struct intel_bb *ibb)
__intel_bb_destroy_relocations(ibb);
__intel_bb_destroy_objects(ibb);
__intel_bb_destroy_cache(ibb);
+ __intel_bb_remove_intel_bufs(ibb);
if (ibb->allocator_type != INTEL_ALLOCATOR_NONE) {
intel_allocator_free(ibb->allocator_handle, ibb->handle);
@@ -1801,24 +1813,13 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
object->offset = offset;
- /* Limit current offset to gtt size */
- if (offset != INTEL_BUF_INVALID_ADDRESS) {
- object->offset = gen8_canonical_addr(offset & (ibb->gtt_size - 1));
-
-
- } else {
- object->offset = __intel_bb_get_offset(ibb,
- handle, size,
- object->alignment);
- }
-
if (write)
object->flags |= EXEC_OBJECT_WRITE;
if (ibb->supports_48b_address)
object->flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- if (ibb->uses_full_ppgtt && ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE)
+ if (ibb->uses_full_ppgtt && !ibb->enforce_relocs)
object->flags |= EXEC_OBJECT_PINNED;
return object;
@@ -1854,7 +1855,12 @@ __intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf,
uint64_t alignment, bool write)
{
struct drm_i915_gem_exec_object2 *obj;
+ struct intel_buf *entry;
+ bool found = false;
+ igt_assert(ibb);
+ igt_assert(buf);
+ igt_assert(!buf->ibb || buf->ibb == ibb);
igt_assert(ALIGN(alignment, 4096) == alignment);
if (!alignment) {
@@ -1875,10 +1881,21 @@ __intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf,
obj = intel_bb_add_object(ibb, buf->handle, intel_buf_bo_size(buf),
buf->addr.offset, alignment, write);
buf->addr.offset = obj->offset;
+ buf->ibb = ibb;
if (!ibb->enforce_relocs)
obj->alignment = alignment;
+ igt_list_for_each_entry(entry, &ibb->intel_bufs, link) {
+ if (buf->handle == entry->handle) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found)
+ igt_list_add_tail(&buf->link, &ibb->intel_bufs);
+
return obj;
}
@@ -1897,16 +1914,40 @@ intel_bb_add_intel_buf_with_alignment(struct intel_bb *ibb, struct intel_buf *bu
bool intel_bb_remove_intel_buf(struct intel_bb *ibb, struct intel_buf *buf)
{
- bool removed = intel_bb_remove_object(ibb, buf->handle,
- buf->addr.offset,
- intel_buf_bo_size(buf));
+ struct intel_buf *entry, *tmp;
+ bool removed;
- if (removed)
- buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
+ igt_assert(ibb);
+ igt_assert(buf);
+ igt_assert(!buf->ibb || buf->ibb == ibb);
+
+ removed = intel_bb_remove_object(ibb, buf->handle,
+ buf->addr.offset,
+ intel_buf_bo_size(buf));
+
+ igt_list_for_each_entry_safe(entry, tmp, &ibb->intel_bufs, link) {
+ if (entry->handle == buf->handle) {
+ buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
+ buf->ibb = NULL;
+ igt_list_del(&entry->link);
+ break;
+ }
+ }
return removed;
}
+void intel_bb_intel_buf_list(struct intel_bb *ibb)
+{
+ struct intel_buf *entry;
+
+ igt_list_for_each_entry(entry, &ibb->intel_bufs, link) {
+ igt_info("handle: %u, ibb: %p, offset: %lx\n",
+ entry->handle, entry->ibb,
+ (long) entry->addr.offset);
+ }
+}
+
struct drm_i915_gem_exec_object2 *
intel_bb_find_object(struct intel_bb *ibb, uint32_t handle)
{
@@ -2302,7 +2343,7 @@ static void update_offsets(struct intel_bb *ibb,
#define LINELEN 76
/*
- * @__intel_bb_exec:
+ * __intel_bb_exec:
* @ibb: pointer to intel_bb
* @end_offset: offset of the last instruction in the bb
* @flags: flags passed directly to execbuf
@@ -2341,6 +2382,9 @@ static int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
if (ibb->dump_base64)
intel_bb_dump_base64(ibb, LINELEN);
+ /* For debugging on CI, remove in final series */
+ intel_bb_dump_execbuf(ibb, &execbuf);
+
ret = __gem_execbuf_wr(ibb->i915, &execbuf);
if (ret) {
intel_bb_dump_execbuf(ibb, &execbuf);
@@ -2442,7 +2486,7 @@ bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf)
return false;
}
- buf->addr.offset = (*found)->offset & (ibb->gtt_size - 1);
+ buf->addr.offset = (*found)->offset;
buf->addr.ctx = ibb->ctx;
return true;
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 029b7e23..497ca551 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -6,6 +6,7 @@
#include <i915_drm.h>
#include "igt_core.h"
+#include "igt_list.h"
#include "intel_reg.h"
#include "drmtest.h"
#include "intel_allocator.h"
@@ -474,6 +475,9 @@ struct intel_bb {
uint32_t num_relocs;
uint32_t allocated_relocs;
+ /* Tracked intel_bufs */
+ struct igt_list_head intel_bufs;
+
/*
* BO recreate in reset path only when refcount == 0
* Currently we don't need to use atomics because intel_bb
@@ -586,6 +590,7 @@ struct drm_i915_gem_exec_object2 *
intel_bb_add_intel_buf_with_alignment(struct intel_bb *ibb, struct intel_buf *buf,
uint64_t alignment, bool write);
bool intel_bb_remove_intel_buf(struct intel_bb *ibb, struct intel_buf *buf);
+void intel_bb_intel_buf_list(struct intel_bb *ibb);
struct drm_i915_gem_exec_object2 *
intel_bb_find_object(struct intel_bb *ibb, uint32_t handle);
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index c0d2ea4f..5833c3f6 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -820,17 +820,24 @@ void intel_buf_init(struct buf_ops *bops,
*
* Function closes gem BO inside intel_buf if bo is owned by intel_buf.
* For handle passed from the caller intel_buf doesn't take ownership and
- * doesn't close it in close()/destroy() paths.
+ * doesn't close it in close()/destroy() paths. When intel_buf was previously
+ * added to intel_bb (intel_bb_add_intel_buf() call) it is tracked there and
+ * must be removed from its internal structures.
*/
void intel_buf_close(struct buf_ops *bops, struct intel_buf *buf)
{
igt_assert(bops);
igt_assert(buf);
- if (buf->is_owner) {
- intel_allocator_remove_handle(bops->fd, buf->handle);
- gem_close(bops->fd, buf->handle);
+ /* If buf is tracked by some intel_bb ensure it will be removed there */
+ if (buf->ibb) {
+ intel_bb_remove_intel_buf(buf->ibb, buf);
+ buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
+ buf->ibb = NULL;
}
+
+ if (buf->is_owner)
+ gem_close(bops->fd, buf->handle);
}
/**
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 54480bff..1a3d8692 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -2,6 +2,7 @@
#define __INTEL_BUFOPS_H__
#include <stdint.h>
+#include "igt_list.h"
#include "igt_aux.h"
#include "intel_batchbuffer.h"
@@ -13,6 +14,7 @@ struct buf_ops;
struct intel_buf {
struct buf_ops *bops;
+
bool is_owner;
uint32_t handle;
uint64_t size;
@@ -40,6 +42,10 @@ struct intel_buf {
uint32_t ctx;
} addr;
+ /* Tracking */
+ struct intel_bb *ibb;
+ struct igt_list_head link;
+
/* CPU mapping */
uint32_t *ptr;
bool cpu_write;
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 13/23] lib/intel_aux_pgtable: Get addresses for aux table from an allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (11 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 12/23] lib/intel_batchbuffer: Add tracking intel_buf to intel_bb Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 14/23] lib/igt_fb: Initialize intel_buf with same size as fb Zbigniew Kempczyński
` (13 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
Use intel_buf which now allows passing expected alignment required
for aux table and acquire appropriate address from an allocator.
With simple allocator we try to use high offsets from default
to exercise canonizing/decanonizing is working properly.
Alter pgtable to allow proper calculation on such offsets.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_aux_pgtable.c | 45 ++++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index ef6a9fef..a970b708 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -68,7 +68,7 @@ static uint64_t last_buf_surface_end(struct intel_buf *buf)
int i;
for (i = 0; i < num_surfaces; i++) {
- uint64_t surface_end = buf->surface[i].offset +
+ uint64_t surface_end = DECANONICAL(buf->surface[i].offset) +
buf->surface[i].size;
if (surface_end > end_offset)
@@ -89,18 +89,20 @@ pgt_table_count(int address_bits, struct intel_buf **bufs, int buf_count)
end = 0;
for (i = 0; i < buf_count; i++) {
struct intel_buf *buf = bufs[i];
- uint64_t start;
+ uint64_t start, offset;
+
+ offset = DECANONICAL(buf->addr.offset);
/* We require bufs to be sorted. */
igt_assert(i == 0 ||
- buf->addr.offset >= bufs[i - 1]->addr.offset +
- intel_buf_bo_size(bufs[i - 1]));
+ offset >= DECANONICAL(bufs[i - 1]->addr.offset) +
+ intel_buf_bo_size(bufs[i - 1]));
+ start = ALIGN_DOWN(offset, 1UL << address_bits);
- start = ALIGN_DOWN(buf->addr.offset, 1UL << address_bits);
/* Avoid double counting for overlapping aligned bufs. */
start = max(start, end);
- end = ALIGN(buf->addr.offset + last_buf_surface_end(buf),
+ end = ALIGN(offset + last_buf_surface_end(buf),
1UL << address_bits);
igt_assert(end >= start);
@@ -180,11 +182,11 @@ pgt_get_child_table(struct pgtable *pgt, uint64_t parent_table,
uint32_t offset;
child_table = pgt_alloc_table(pgt, level - 1);
- igt_assert(!((child_table + pgt->buf->addr.offset) &
+ igt_assert(!((child_table + DECANONICAL(pgt->buf->addr.offset)) &
~ptr_mask(pgt, level)));
pte = child_table | flags;
- *child_entry_ptr = pgt->buf->addr.offset + pte;
+ *child_entry_ptr = DECANONICAL(pgt->buf->addr.offset) + pte;
igt_assert(pte <= INT32_MAX);
@@ -197,7 +199,7 @@ pgt_get_child_table(struct pgtable *pgt, uint64_t parent_table,
pgt->buf->addr.offset);
} else {
child_table = (*child_entry_ptr & ptr_mask(pgt, level)) -
- pgt->buf->addr.offset;
+ DECANONICAL(pgt->buf->addr.offset);
}
return child_table;
@@ -346,11 +348,11 @@ pgt_populate_entries_for_buf(struct pgtable *pgt,
uint64_t top_table,
int surface_idx)
{
- uint64_t surface_addr = buf->addr.offset +
+ uint64_t surface_addr = DECANONICAL(buf->addr.offset) +
buf->surface[surface_idx].offset;
uint64_t surface_end = surface_addr +
buf->surface[surface_idx].size;
- uint64_t aux_addr = buf->addr.offset + buf->ccs[surface_idx].offset;
+ uint64_t aux_addr = DECANONICAL(buf->addr.offset) + buf->ccs[surface_idx].offset;
uint64_t l1_flags = pgt_get_l1_flags(buf, surface_idx);
uint64_t lx_flags = pgt_get_lx_flags();
@@ -441,7 +443,6 @@ struct intel_buf *
intel_aux_pgtable_create(struct intel_bb *ibb,
struct intel_buf **bufs, int buf_count)
{
- struct drm_i915_gem_exec_object2 *obj;
static const struct pgtable_level_desc level_desc[] = {
{
.idx_shift = 16,
@@ -465,7 +466,6 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
struct pgtable *pgt;
struct buf_ops *bops;
struct intel_buf *buf;
- uint64_t prev_alignment;
igt_assert(buf_count);
bops = bufs[0]->bops;
@@ -476,11 +476,8 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
I915_COMPRESSION_NONE);
/* We need to use pgt->max_align for aux table */
- prev_alignment = intel_bb_set_default_object_alignment(ibb,
- pgt->max_align);
- obj = intel_bb_add_intel_buf(ibb, pgt->buf, false);
- intel_bb_set_default_object_alignment(ibb, prev_alignment);
- obj->alignment = pgt->max_align;
+ intel_bb_add_intel_buf_with_alignment(ibb, pgt->buf,
+ pgt->max_align, false);
pgt_map(ibb->i915, pgt);
pgt_populate_entries(pgt, bufs, buf_count);
@@ -496,11 +493,15 @@ static void
aux_pgtable_reserve_buf_slot(struct intel_buf **bufs, int buf_count,
struct intel_buf *new_buf)
{
+ uint64_t curr, newone;
int i;
- for (i = 0; i < buf_count; i++)
- if (bufs[i]->addr.offset > new_buf->addr.offset)
+ for (i = 0; i < buf_count; i++) {
+ curr = DECANONICAL(bufs[i]->addr.offset);
+ newone = DECANONICAL(new_buf->addr.offset);
+ if (curr > newone)
break;
+ }
memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count - i));
@@ -591,8 +592,10 @@ gen12_aux_pgtable_cleanup(struct intel_bb *ibb, struct aux_pgtable_info *info)
igt_assert_eq_u64(addr, info->buf_pin_offsets[i]);
}
- if (info->pgtable_buf)
+ if (info->pgtable_buf) {
+ intel_bb_remove_intel_buf(ibb, info->pgtable_buf);
intel_buf_destroy(info->pgtable_buf);
+ }
}
uint32_t
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 14/23] lib/igt_fb: Initialize intel_buf with same size as fb
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (12 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 13/23] lib/intel_aux_pgtable: Get addresses for aux table from an allocator Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 15/23] tests/api_intel_bb: Modify test to verify intel_bb with allocator Zbigniew Kempczyński
` (12 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
We need to have same size when intel_buf is initialized over fb
(with compression) because allocator could be called with smaller
size what could lead to relocation.
Use new intel_buf function which allows initalize with handle and size.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_fb.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 43f8c475..207a8393 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2172,11 +2172,11 @@ static struct intel_buf *create_buf(struct fb_blit_upload *blit,
bo_name = gem_flink(blit->fd, fb->gem_handle);
handle = gem_open(blit->fd, bo_name);
- buf = intel_buf_create_using_handle(blit->bops, handle,
- fb->width, fb->height,
- fb->plane_bpp[0], 0,
- igt_fb_mod_to_tiling(fb->modifier),
- compression);
+ buf = intel_buf_create_using_handle_and_size(blit->bops, handle,
+ fb->width, fb->height,
+ fb->plane_bpp[0], 0,
+ igt_fb_mod_to_tiling(fb->modifier),
+ compression, fb->size);
intel_buf_set_name(buf, name);
/* Make sure we close handle on destroy path */
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 15/23] tests/api_intel_bb: Modify test to verify intel_bb with allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (13 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 14/23] lib/igt_fb: Initialize intel_buf with same size as fb Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 16/23] tests/api_intel_bb: Add compressed->compressed copy Zbigniew Kempczyński
` (11 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
intel_bb was adopted to use allocator. Change the test to verify
addresses in different scenarios - with relocations and with softpin.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/api_intel_bb.c | 542 +++++++++++++++++++++++++++++---------
1 file changed, 411 insertions(+), 131 deletions(-)
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
index 965a7dde..9882fb99 100644
--- a/tests/i915/api_intel_bb.c
+++ b/tests/i915/api_intel_bb.c
@@ -45,6 +45,8 @@
#define COLOR_77 0x77
#define COLOR_CC 0xcc
+#define DECANONICAL(offset) (offset & ((1ull << 48) - 1))
+
IGT_TEST_DESCRIPTION("intel_bb API check.");
enum reloc_objects {
@@ -123,24 +125,33 @@ static void print_buf(struct intel_buf *buf, const char *name)
ptr = gem_mmap__device_coherent(i915, buf->handle, 0,
buf->surface[0].size, PROT_READ);
- igt_debug("[%s] Buf handle: %d, size: %d, v: 0x%02x, presumed_addr: %p\n",
+ igt_debug("[%s] Buf handle: %d, size: %" PRIu64
+ ", v: 0x%02x, presumed_addr: %p\n",
name, buf->handle, buf->surface[0].size, ptr[0],
from_user_pointer(buf->addr.offset));
munmap(ptr, buf->surface[0].size);
}
+static void reset_bb(struct buf_ops *bops)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ intel_bb_reset(ibb, false);
+ intel_bb_destroy(ibb);
+}
+
static void simple_bb(struct buf_ops *bops, bool use_context)
{
int i915 = buf_ops_get_fd(bops);
struct intel_bb *ibb;
- uint32_t ctx;
+ uint32_t ctx = 0;
- if (use_context) {
+ if (use_context)
gem_require_contexts(i915);
- ctx = gem_context_create(i915);
- }
- ibb = intel_bb_create(i915, PAGE_SIZE);
+ ibb = intel_bb_create_full(i915, ctx, PAGE_SIZE, INTEL_ALLOCATOR_SIMPLE);
if (debug_bb)
intel_bb_set_debug(ibb, true);
@@ -155,10 +166,8 @@ static void simple_bb(struct buf_ops *bops, bool use_context)
intel_bb_reset(ibb, false);
intel_bb_reset(ibb, true);
- intel_bb_out(ibb, MI_BATCH_BUFFER_END);
- intel_bb_ptr_align(ibb, 8);
-
if (use_context) {
+ ctx = gem_context_create(i915);
intel_bb_destroy(ibb);
ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
intel_bb_out(ibb, MI_BATCH_BUFFER_END);
@@ -166,11 +175,10 @@ static void simple_bb(struct buf_ops *bops, bool use_context)
intel_bb_exec(ibb, intel_bb_offset(ibb),
I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
true);
+ gem_context_destroy(i915, ctx);
}
intel_bb_destroy(ibb);
- if (use_context)
- gem_context_destroy(i915, ctx);
}
/*
@@ -194,28 +202,42 @@ static void lot_of_buffers(struct buf_ops *bops)
for (i = 0; i < NUM_BUFS; i++) {
buf[i] = intel_buf_create(bops, 4096, 1, 8, 0, I915_TILING_NONE,
I915_COMPRESSION_NONE);
- intel_bb_add_intel_buf(ibb, buf[i], false);
+ if (i % 2)
+ intel_bb_add_intel_buf(ibb, buf[i], false);
+ else
+ intel_bb_add_intel_buf_with_alignment(ibb, buf[i],
+ 0x4000, false);
}
intel_bb_exec(ibb, intel_bb_offset(ibb),
I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
- intel_bb_destroy(ibb);
-
for (i = 0; i < NUM_BUFS; i++)
intel_buf_destroy(buf[i]);
+
+ intel_bb_destroy(ibb);
}
/*
* Make sure intel-bb space allocator currently doesn't enter 47-48 bit
* gtt sizes.
*/
+#define GEN8_HIGH_ADDRESS_BIT 47
+static uint64_t gen8_canonical_addr(uint64_t address)
+{
+ int shift = 63 - GEN8_HIGH_ADDRESS_BIT;
+
+ return (int64_t)(address << shift) >> shift;
+}
+
static void check_canonical(struct buf_ops *bops)
{
- int i915 = buf_ops_get_fd(bops);
+ int i915 = buf_ops_get_fd(bops), i;
struct intel_bb *ibb;
struct intel_buf *buf;
uint32_t offset;
+ /* Twice same addresses to verify will be unreserved in remove path */
+ uint64_t addresses[] = { 0x800000000000, 0x800000000000, 0x400000000000 };
uint64_t address;
bool supports_48bit;
@@ -225,25 +247,32 @@ static void check_canonical(struct buf_ops *bops)
intel_bb_destroy(ibb);
igt_require_f(supports_48bit, "We need 48bit ppgtt for testing\n");
- address = 0xc00000000000;
if (debug_bb)
intel_bb_set_debug(ibb, true);
- offset = intel_bb_emit_bbe(ibb);
+ for (i = 0; i < ARRAY_SIZE(addresses); i++) {
+ address = addresses[i];
- buf = intel_buf_create(bops, 512, 512, 32, 0,
- I915_TILING_NONE, I915_COMPRESSION_NONE);
+ offset = intel_bb_emit_bbe(ibb);
- buf->addr.offset = address;
- intel_bb_add_intel_buf(ibb, buf, true);
- intel_bb_object_set_flag(ibb, buf->handle, EXEC_OBJECT_PINNED);
+ buf = intel_buf_create(bops, 512, 512, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
- igt_assert(buf->addr.offset == 0);
+ buf->addr.offset = address;
+ intel_bb_add_intel_buf(ibb, buf, true);
+ intel_bb_add_intel_buf(ibb, buf, true);
- intel_bb_exec(ibb, offset,
- I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ igt_assert(buf->addr.offset == gen8_canonical_addr(address));
+
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ /* We ensure to do unreserve and verify address can be reused */
+ intel_bb_remove_intel_buf(ibb, buf);
+ intel_buf_destroy(buf);
+ intel_bb_reset(ibb, true);
+ }
- intel_buf_destroy(buf);
intel_bb_destroy(ibb);
}
@@ -339,70 +368,287 @@ static void reset_flags(struct buf_ops *bops)
intel_bb_destroy(ibb);
}
+static void add_remove_objects(struct buf_ops *bops)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *mid, *dst;
+ uint32_t offset;
+ const uint32_t width = 512;
+ const uint32_t height = 512;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
-#define MI_FLUSH_DW (0x26<<23)
-#define BCS_SWCTRL 0x22200
-#define BCS_SRC_Y (1 << 0)
-#define BCS_DST_Y (1 << 1)
-static void __emit_blit(struct intel_bb *ibb,
- struct intel_buf *src, struct intel_buf *dst)
+ src = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ mid = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ dst = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, mid, true);
+ intel_bb_remove_intel_buf(ibb, mid);
+ intel_bb_remove_intel_buf(ibb, mid);
+ intel_bb_remove_intel_buf(ibb, mid);
+ intel_bb_add_intel_buf(ibb, dst, true);
+
+ offset = intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ intel_buf_destroy(src);
+ intel_buf_destroy(mid);
+ intel_buf_destroy(dst);
+ intel_bb_destroy(ibb);
+}
+
+static void destroy_bb(struct buf_ops *bops)
{
- uint32_t mask;
- bool has_64b_reloc;
- uint64_t address;
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *mid, *dst;
+ uint32_t offset;
+ const uint32_t width = 512;
+ const uint32_t height = 512;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ src = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ mid = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ dst = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, mid, true);
+ intel_bb_add_intel_buf(ibb, dst, true);
+
+ offset = intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ /* Check destroy will detach intel_bufs */
+ intel_bb_destroy(ibb);
+ igt_assert(src->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(src->ibb == NULL);
+ igt_assert(mid->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(mid->ibb == NULL);
+ igt_assert(dst->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(dst->ibb == NULL);
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_add_intel_buf(ibb, src, false);
+ offset = intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ intel_bb_destroy(ibb);
+ intel_buf_destroy(src);
+ intel_buf_destroy(mid);
+ intel_buf_destroy(dst);
+}
- has_64b_reloc = ibb->gen >= 8;
+static void object_reloc(struct buf_ops *bops, enum obj_cache_ops cache_op)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ uint32_t h1, h2;
+ uint64_t poff_bb, poff_h1, poff_h2;
+ uint64_t poff2_bb, poff2_h1, poff2_h2;
+ uint64_t flags = 0;
+ uint64_t shift = cache_op == PURGE_CACHE ? 0x2000 : 0x0;
+ bool purge_cache = cache_op == PURGE_CACHE ? true : false;
+
+ ibb = intel_bb_create_with_relocs(i915, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
- if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
- intel_bb_out(ibb, MI_LOAD_REGISTER_IMM);
- intel_bb_out(ibb, BCS_SWCTRL);
+ h1 = gem_create(i915, PAGE_SIZE);
+ h2 = gem_create(i915, PAGE_SIZE);
- mask = (BCS_SRC_Y | BCS_DST_Y) << 16;
- if (src->tiling == I915_TILING_Y)
- mask |= BCS_SRC_Y;
- if (dst->tiling == I915_TILING_Y)
- mask |= BCS_DST_Y;
- intel_bb_out(ibb, mask);
+ /* intel_bb_create adds bb handle so it has 0 for relocs */
+ poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ igt_assert(poff_bb == 0);
+
+ /* Before adding to intel_bb it should return INVALID_ADDRESS */
+ poff_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_debug("[1] poff_h1: %lx\n", (long) poff_h1);
+ igt_debug("[1] poff_h2: %lx\n", (long) poff_h2);
+ igt_assert(poff_h1 == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(poff_h2 == INTEL_BUF_INVALID_ADDRESS);
+
+ intel_bb_add_object(ibb, h1, PAGE_SIZE, poff_h1, 0, true);
+ intel_bb_add_object(ibb, h2, PAGE_SIZE, poff_h2, 0x2000, true);
+
+ /*
+ * Objects were added to bb, we expect initial addresses are zeroed
+ * for relocs.
+ */
+ poff_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_assert(poff_h1 == 0);
+ igt_assert(poff_h2 == 0);
+
+ intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, intel_bb_offset(ibb), flags, false);
+
+ poff2_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff2_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff2_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_debug("[2] poff2_h1: %lx\n", (long) poff2_h1);
+ igt_debug("[2] poff2_h2: %lx\n", (long) poff2_h2);
+ /* Some addresses won't be 0 */
+ igt_assert(poff2_bb | poff2_h1 | poff2_h2);
+
+ intel_bb_reset(ibb, purge_cache);
+
+ if (purge_cache) {
+ intel_bb_add_object(ibb, h1, PAGE_SIZE, poff2_h1, 0, true);
+ intel_bb_add_object(ibb, h2, PAGE_SIZE, poff2_h2 + shift, 0x2000, true);
}
- intel_bb_out(ibb,
- XY_SRC_COPY_BLT_CMD |
- XY_SRC_COPY_BLT_WRITE_ALPHA |
- XY_SRC_COPY_BLT_WRITE_RGB |
- (6 + 2 * has_64b_reloc));
- intel_bb_out(ibb, 3 << 24 | 0xcc << 16 | dst->surface[0].stride);
- intel_bb_out(ibb, 0);
- intel_bb_out(ibb, intel_buf_height(dst) << 16 | intel_buf_width(dst));
+ poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_debug("[3] poff_h1: %lx\n", (long) poff_h1);
+ igt_debug("[3] poff_h2: %lx\n", (long) poff_h2);
+ igt_debug("[3] poff2_h1: %lx\n", (long) poff2_h1);
+ igt_debug("[3] poff2_h2: %lx + shift (%lx)\n", (long) poff2_h2,
+ (long) shift);
+ igt_assert(poff_h1 == poff2_h1);
+ igt_assert(poff_h2 == poff2_h2 + shift);
+ intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, intel_bb_offset(ibb), flags, false);
- address = intel_bb_get_object_offset(ibb, dst->handle);
- intel_bb_emit_reloc_fenced(ibb, dst->handle,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER,
- 0, address);
- intel_bb_out(ibb, 0);
- intel_bb_out(ibb, src->surface[0].stride);
+ gem_close(i915, h1);
+ gem_close(i915, h2);
+ intel_bb_destroy(ibb);
+}
- address = intel_bb_get_object_offset(ibb, src->handle);
- intel_bb_emit_reloc_fenced(ibb, src->handle,
- I915_GEM_DOMAIN_RENDER, 0,
- 0, address);
+#define WITHIN_RANGE(offset, start, end) \
+ (DECANONICAL(offset) >= start && DECANONICAL(offset) <= end)
+static void object_noreloc(struct buf_ops *bops, enum obj_cache_ops cache_op,
+ uint8_t allocator_type)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ uint32_t h1, h2;
+ uint64_t start, end;
+ uint64_t poff_bb, poff_h1, poff_h2;
+ uint64_t poff2_bb, poff2_h1, poff2_h2;
+ uint64_t flags = 0;
+ bool purge_cache = cache_op == PURGE_CACHE ? true : false;
- if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
- igt_assert(ibb->gen >= 6);
- intel_bb_out(ibb, MI_FLUSH_DW | 2);
- intel_bb_out(ibb, 0);
- intel_bb_out(ibb, 0);
- intel_bb_out(ibb, 0);
+ igt_require(gem_uses_full_ppgtt(i915));
+
+ ibb = intel_bb_create_full(i915, 0, PAGE_SIZE, allocator_type);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ h1 = gem_create(i915, PAGE_SIZE);
+ h2 = gem_create(i915, PAGE_SIZE);
+
+ intel_allocator_get_address_range(ibb->allocator_handle,
+ &start, &end);
+ poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ igt_debug("[1] bb presumed offset: 0x%" PRIx64
+ ", start: %" PRIx64 ", end: %" PRIx64 "\n",
+ poff_bb, start, end);
+ igt_assert(WITHIN_RANGE(poff_bb, start, end));
+
+ /* Before adding to intel_bb it should return INVALID_ADDRESS */
+ poff_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_debug("[1] h1 presumed offset: 0x%"PRIx64"\n", poff_h1);
+ igt_debug("[1] h2 presumed offset: 0x%"PRIx64"\n", poff_h2);
+ igt_assert(poff_h1 == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(poff_h2 == INTEL_BUF_INVALID_ADDRESS);
+
+ intel_bb_add_object(ibb, h1, PAGE_SIZE, poff_h1, 0, true);
+ intel_bb_add_object(ibb, h2, PAGE_SIZE, poff_h2, 0, true);
+
+ poff_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_debug("[2] bb presumed offset: 0x%"PRIx64"\n", poff_bb);
+ igt_debug("[2] h1 presumed offset: 0x%"PRIx64"\n", poff_h1);
+ igt_debug("[2] h2 presumed offset: 0x%"PRIx64"\n", poff_h2);
+ igt_assert(WITHIN_RANGE(poff_bb, start, end));
+ igt_assert(WITHIN_RANGE(poff_h1, start, end));
+ igt_assert(WITHIN_RANGE(poff_h2, start, end));
+
+ intel_bb_emit_bbe(ibb);
+ igt_debug("exec flags: %" PRIX64 "\n", flags);
+ intel_bb_exec(ibb, intel_bb_offset(ibb), flags, false);
+
+ poff2_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff2_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff2_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_debug("[3] bb presumed offset: 0x%"PRIx64"\n", poff2_bb);
+ igt_debug("[3] h1 presumed offset: 0x%"PRIx64"\n", poff2_h1);
+ igt_debug("[3] h2 presumed offset: 0x%"PRIx64"\n", poff2_h2);
+ igt_assert(poff_h1 == poff2_h1);
+ igt_assert(poff_h2 == poff2_h2);
+
+ igt_debug("purge: %d\n", purge_cache);
+ intel_bb_reset(ibb, purge_cache);
- intel_bb_out(ibb, MI_LOAD_REGISTER_IMM);
- intel_bb_out(ibb, BCS_SWCTRL);
- intel_bb_out(ibb, (BCS_SRC_Y | BCS_DST_Y) << 16);
+ /*
+ * Check if intel-bb cache was purged:
+ * a) retrieve same address from allocator (works for simple, not random)
+ * b) passing previous address enters allocator <-> intel_bb cache
+ * consistency check path.
+ */
+ if (purge_cache) {
+ intel_bb_add_object(ibb, h1, PAGE_SIZE,
+ INTEL_BUF_INVALID_ADDRESS, 0, true);
+ intel_bb_add_object(ibb, h2, PAGE_SIZE, poff2_h2, 0, true);
+ } else {
+ /* See consistency check will not fail */
+ intel_bb_add_object(ibb, h1, PAGE_SIZE, poff2_h1, 0, true);
+ intel_bb_add_object(ibb, h2, PAGE_SIZE, poff2_h2, 0, true);
}
+
+ poff_h1 = intel_bb_get_object_offset(ibb, h1);
+ poff_h2 = intel_bb_get_object_offset(ibb, h2);
+ igt_debug("[4] bb presumed offset: 0x%"PRIx64"\n", poff_bb);
+ igt_debug("[4] h1 presumed offset: 0x%"PRIx64"\n", poff_h1);
+ igt_debug("[4] h2 presumed offset: 0x%"PRIx64"\n", poff_h2);
+
+ /* For simple allocator and purge=cache we must have same addresses */
+ if (allocator_type == INTEL_ALLOCATOR_SIMPLE || !purge_cache) {
+ igt_assert(poff_h1 == poff2_h1);
+ igt_assert(poff_h2 == poff2_h2);
+ }
+
+ gem_close(i915, h1);
+ gem_close(i915, h2);
+ intel_bb_destroy(ibb);
+}
+static void __emit_blit(struct intel_bb *ibb,
+ struct intel_buf *src, struct intel_buf *dst)
+{
+ intel_bb_emit_blt_copy(ibb,
+ src, 0, 0, src->surface[0].stride,
+ dst, 0, 0, dst->surface[0].stride,
+ intel_buf_width(dst),
+ intel_buf_height(dst),
+ dst->bpp);
}
static void blit(struct buf_ops *bops,
enum reloc_objects reloc_obj,
- enum obj_cache_ops cache_op)
+ enum obj_cache_ops cache_op,
+ uint8_t allocator_type)
{
int i915 = buf_ops_get_fd(bops);
struct intel_bb *ibb;
@@ -413,6 +659,9 @@ static void blit(struct buf_ops *bops,
bool purge_cache = cache_op == PURGE_CACHE ? true : false;
bool do_relocs = reloc_obj == RELOC ? true : false;
+ if (!do_relocs)
+ igt_require(gem_uses_full_ppgtt(i915));
+
src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
dst = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
@@ -424,55 +673,68 @@ static void blit(struct buf_ops *bops,
if (do_relocs) {
ibb = intel_bb_create_with_relocs(i915, PAGE_SIZE);
} else {
- ibb = intel_bb_create(i915, PAGE_SIZE);
+ ibb = intel_bb_create_full(i915, 0, PAGE_SIZE, allocator_type);
flags |= I915_EXEC_NO_RELOC;
}
- if (ibb->gen >= 6)
- flags |= I915_EXEC_BLT;
-
if (debug_bb)
intel_bb_set_debug(ibb, true);
-
- intel_bb_add_intel_buf(ibb, src, false);
- intel_bb_add_intel_buf(ibb, dst, true);
-
__emit_blit(ibb, src, dst);
/* We expect initial addresses are zeroed for relocs */
- poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
- poff_src = intel_bb_get_object_offset(ibb, src->handle);
- poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
- igt_debug("bb presumed offset: 0x%"PRIx64"\n", poff_bb);
- igt_debug("src presumed offset: 0x%"PRIx64"\n", poff_src);
- igt_debug("dst presumed offset: 0x%"PRIx64"\n", poff_dst);
if (reloc_obj == RELOC) {
+ poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
+ poff_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ igt_debug("bb presumed offset: 0x%"PRIx64"\n", poff_bb);
+ igt_debug("src presumed offset: 0x%"PRIx64"\n", poff_src);
+ igt_debug("dst presumed offset: 0x%"PRIx64"\n", poff_dst);
igt_assert(poff_bb == 0);
igt_assert(poff_src == 0);
igt_assert(poff_dst == 0);
}
intel_bb_emit_bbe(ibb);
- igt_debug("exec flags: %" PRIX64 "\n", flags);
- intel_bb_exec(ibb, intel_bb_offset(ibb), flags, true);
+ intel_bb_flush_blit(ibb);
+ intel_bb_sync(ibb);
+
check_buf(dst, COLOR_CC);
poff_bb = intel_bb_get_object_offset(ibb, ibb->handle);
poff_src = intel_bb_get_object_offset(ibb, src->handle);
poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ /*
+ * For relocations intel_bb is not updating intel_buf offsets yet,
+ * for allocators we use intel_buf offset even if intel_bb cache
+ * is empty.
+ */
+ if (reloc_obj == RELOC) {
+ intel_bb_object_offset_to_buf(ibb, src);
+ intel_bb_object_offset_to_buf(ibb, dst);
+ }
+
intel_bb_reset(ibb, purge_cache);
+ /* Add buffers again, should work both for purge and keep cache */
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, dst, true);
+
+ igt_assert_f(poff_src == src->addr.offset,
+ "prev src addr: %" PRIx64 " <> src addr %" PRIx64 "\n",
+ poff_src, src->addr.offset);
+ igt_assert_f(poff_dst == dst->addr.offset,
+ "prev dst addr: %" PRIx64 " <> dst addr %" PRIx64 "\n",
+ poff_dst, dst->addr.offset);
+
fill_buf(src, COLOR_77);
fill_buf(dst, COLOR_00);
- if (purge_cache && !do_relocs) {
- intel_bb_add_intel_buf(ibb, src, false);
- intel_bb_add_intel_buf(ibb, dst, true);
- }
-
__emit_blit(ibb, src, dst);
+ intel_bb_flush_blit(ibb);
+ intel_bb_sync(ibb);
+ check_buf(dst, COLOR_77);
poff2_bb = intel_bb_get_object_offset(ibb, ibb->handle);
poff2_src = intel_bb_get_object_offset(ibb, src->handle);
@@ -485,28 +747,12 @@ static void blit(struct buf_ops *bops,
igt_debug("bb2 presumed offset: 0x%"PRIx64"\n", poff2_bb);
igt_debug("src2 presumed offset: 0x%"PRIx64"\n", poff2_src);
igt_debug("dst2 presumed offset: 0x%"PRIx64"\n", poff2_dst);
- if (purge_cache) {
- if (do_relocs) {
- igt_assert(poff2_bb == 0);
- igt_assert(poff2_src == 0);
- igt_assert(poff2_dst == 0);
- } else {
- igt_assert(poff_bb != poff2_bb);
- igt_assert(poff_src == poff2_src);
- igt_assert(poff_dst == poff2_dst);
- }
- } else {
- igt_assert(poff_bb == poff2_bb);
- igt_assert(poff_src == poff2_src);
- igt_assert(poff_dst == poff2_dst);
- }
-
- intel_bb_emit_bbe(ibb);
- intel_bb_exec(ibb, intel_bb_offset(ibb), flags, true);
- check_buf(dst, COLOR_77);
- poff2_src = intel_bb_get_object_offset(ibb, src->handle);
- poff2_dst = intel_bb_get_object_offset(ibb, dst->handle);
+ /*
+ * In intel_bb reset path we recreate bb handle so we cannot assume
+ * we will have same address for relocations. We can enforce it
+ * when we use allocator and softpin. */
+ igt_assert(do_relocs || poff_bb == poff2_bb);
igt_assert(poff_src == poff2_src);
igt_assert(poff_dst == poff2_dst);
@@ -663,7 +909,7 @@ static int dump_base64(const char *name, struct intel_buf *buf)
if (ret != Z_OK) {
igt_warn("error compressing, ret: %d\n", ret);
} else {
- igt_info("compressed %u -> %lu\n",
+ igt_info("compressed %" PRIu64 " -> %lu\n",
buf->surface[0].size, outsize);
igt_info("--- %s ---\n", name);
@@ -796,11 +1042,11 @@ static void offset_control(struct buf_ops *bops)
dst2 = create_buf(bops, WIDTH, HEIGHT, COLOR_77);
intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
- src->addr.offset, false);
+ src->addr.offset, 0, false);
intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
- dst1->addr.offset, true);
+ dst1->addr.offset, 0, true);
intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
- dst2->addr.offset, true);
+ dst2->addr.offset, 0, true);
intel_bb_out(ibb, MI_BATCH_BUFFER_END);
intel_bb_ptr_align(ibb, 8);
@@ -824,13 +1070,13 @@ static void offset_control(struct buf_ops *bops)
dst3 = create_buf(bops, WIDTH, HEIGHT, COLOR_33);
intel_bb_add_object(ibb, dst3->handle, intel_buf_bo_size(dst3),
- dst3->addr.offset, true);
+ dst3->addr.offset, 0, true);
intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
- src->addr.offset, false);
+ src->addr.offset, 0, false);
intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
- dst1->addr.offset, true);
+ dst1->addr.offset, 0, true);
intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
- dst2->addr.offset, true);
+ dst2->addr.offset, 0, true);
intel_bb_out(ibb, MI_BATCH_BUFFER_END);
intel_bb_ptr_align(ibb, 8);
@@ -1109,6 +1355,10 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
gen = intel_gen(intel_get_drm_devid(i915));
}
+ igt_describe("Ensure reset is possible on fresh bb");
+ igt_subtest("reset-bb")
+ reset_bb(bops);
+
igt_subtest("simple-bb")
simple_bb(bops, false);
@@ -1124,17 +1374,47 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
igt_subtest("reset-flags")
reset_flags(bops);
- igt_subtest("blit-noreloc-keep-cache")
- blit(bops, NORELOC, KEEP_CACHE);
+ igt_subtest("add-remove-objects")
+ add_remove_objects(bops);
- igt_subtest("blit-reloc-purge-cache")
- blit(bops, RELOC, PURGE_CACHE);
+ igt_subtest("destroy-bb")
+ destroy_bb(bops);
- igt_subtest("blit-noreloc-purge-cache")
- blit(bops, NORELOC, PURGE_CACHE);
+ igt_subtest("object-reloc-purge-cache")
+ object_reloc(bops, PURGE_CACHE);
+
+ igt_subtest("object-reloc-keep-cache")
+ object_reloc(bops, KEEP_CACHE);
+
+ igt_subtest("object-noreloc-purge-cache-simple")
+ object_noreloc(bops, PURGE_CACHE, INTEL_ALLOCATOR_SIMPLE);
+
+ igt_subtest("object-noreloc-keep-cache-simple")
+ object_noreloc(bops, KEEP_CACHE, INTEL_ALLOCATOR_SIMPLE);
+
+ igt_subtest("object-noreloc-purge-cache-random")
+ object_noreloc(bops, PURGE_CACHE, INTEL_ALLOCATOR_RANDOM);
+
+ igt_subtest("object-noreloc-keep-cache-random")
+ object_noreloc(bops, KEEP_CACHE, INTEL_ALLOCATOR_RANDOM);
+
+ igt_subtest("blit-reloc-purge-cache")
+ blit(bops, RELOC, PURGE_CACHE, INTEL_ALLOCATOR_SIMPLE);
igt_subtest("blit-reloc-keep-cache")
- blit(bops, RELOC, KEEP_CACHE);
+ blit(bops, RELOC, KEEP_CACHE, INTEL_ALLOCATOR_SIMPLE);
+
+ igt_subtest("blit-noreloc-keep-cache-random")
+ blit(bops, NORELOC, KEEP_CACHE, INTEL_ALLOCATOR_RANDOM);
+
+ igt_subtest("blit-noreloc-purge-cache-random")
+ blit(bops, NORELOC, PURGE_CACHE, INTEL_ALLOCATOR_RANDOM);
+
+ igt_subtest("blit-noreloc-keep-cache")
+ blit(bops, NORELOC, KEEP_CACHE, INTEL_ALLOCATOR_SIMPLE);
+
+ igt_subtest("blit-noreloc-purge-cache")
+ blit(bops, NORELOC, PURGE_CACHE, INTEL_ALLOCATOR_SIMPLE);
igt_subtest("intel-bb-blit-none")
do_intel_bb_blit(bops, 10, I915_TILING_NONE);
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 16/23] tests/api_intel_bb: Add compressed->compressed copy
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (14 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 15/23] tests/api_intel_bb: Modify test to verify intel_bb with allocator Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 17/23] tests/api_intel_allocator: Simple allocator test suite Zbigniew Kempczyński
` (10 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
Check aux pagetables are working when more than one compressed
buffers are added.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/api_intel_bb.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
index 9882fb99..44ebd9cc 100644
--- a/tests/i915/api_intel_bb.c
+++ b/tests/i915/api_intel_bb.c
@@ -1245,7 +1245,7 @@ static void render_ccs(struct buf_ops *bops)
struct intel_bb *ibb;
const int width = 1024;
const int height = 1024;
- struct intel_buf src, dst, final;
+ struct intel_buf src, dst, dst2, final;
int i915 = buf_ops_get_fd(bops);
uint32_t fails = 0;
uint32_t compressed = 0;
@@ -1260,6 +1260,8 @@ static void render_ccs(struct buf_ops *bops)
I915_COMPRESSION_NONE);
scratch_buf_init(bops, &dst, width, height, I915_TILING_Y,
I915_COMPRESSION_RENDER);
+ scratch_buf_init(bops, &dst2, width, height, I915_TILING_Y,
+ I915_COMPRESSION_RENDER);
scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
I915_COMPRESSION_NONE);
@@ -1279,6 +1281,12 @@ static void render_ccs(struct buf_ops *bops)
render_copy(ibb,
&dst,
0, 0, width, height,
+ &dst2,
+ 0, 0);
+
+ render_copy(ibb,
+ &dst2,
+ 0, 0, width, height,
&final,
0, 0);
@@ -1294,12 +1302,15 @@ static void render_ccs(struct buf_ops *bops)
if (write_png) {
intel_buf_write_to_png(&src, "render-ccs-src.png");
intel_buf_write_to_png(&dst, "render-ccs-dst.png");
+ intel_buf_write_to_png(&dst2, "render-ccs-dst2.png");
intel_buf_write_aux_to_png(&dst, "render-ccs-dst-aux.png");
+ intel_buf_write_aux_to_png(&dst2, "render-ccs-dst2-aux.png");
intel_buf_write_to_png(&final, "render-ccs-final.png");
}
intel_buf_close(bops, &src);
intel_buf_close(bops, &dst);
+ intel_buf_close(bops, &dst2);
intel_buf_close(bops, &final);
igt_assert_f(fails == 0, "render-ccs fails: %d\n", fails);
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 17/23] tests/api_intel_allocator: Simple allocator test suite
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (15 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 16/23] tests/api_intel_bb: Add compressed->compressed copy Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 18/23] tests/gem|kms: Remove intel_bb from fixture Zbigniew Kempczyński
` (9 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
We want to verify allocator works as expected. Try to exploit it.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/api_intel_allocator.c | 589 +++++++++++++++++++++++++++++++
tests/meson.build | 1 +
2 files changed, 590 insertions(+)
create mode 100644 tests/i915/api_intel_allocator.c
diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c
new file mode 100644
index 00000000..84366e70
--- /dev/null
+++ b/tests/i915/api_intel_allocator.c
@@ -0,0 +1,589 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <stdatomic.h>
+#include "i915/gem.h"
+#include "igt.h"
+#include "igt_aux.h"
+#include "intel_allocator.h"
+
+#define OBJ_SIZE 1024
+
+struct test_obj {
+ uint32_t handle;
+ uint64_t offset;
+ uint64_t size;
+};
+
+static _Atomic(uint32_t) next_handle;
+
+static inline uint32_t gem_handle_gen(void)
+{
+ return atomic_fetch_add(&next_handle, 1);
+}
+
+static void alloc_simple(int fd)
+{
+ uint64_t ialh;
+ uint64_t offset0, offset1;
+ bool is_allocated, freed;
+
+ ialh = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+
+ offset0 = intel_allocator_alloc(ialh, 1, 0x1000, 0x1000);
+ offset1 = intel_allocator_alloc(ialh, 1, 0x1000, 0x1000);
+ igt_assert(offset0 == offset1);
+
+ is_allocated = intel_allocator_is_allocated(ialh, 1, 0x1000, offset0);
+ igt_assert(is_allocated);
+
+ freed = intel_allocator_free(ialh, 1);
+ igt_assert(freed);
+
+ is_allocated = intel_allocator_is_allocated(ialh, 1, 0x1000, offset0);
+ igt_assert(!is_allocated);
+
+ freed = intel_allocator_free(ialh, 1);
+ igt_assert(!freed);
+
+ intel_allocator_close(ialh);
+}
+
+static void reserve_simple(int fd)
+{
+ uint64_t ialh;
+ uint64_t start;
+ bool reserved, unreserved;
+
+ ialh = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+ intel_allocator_get_address_range(ialh, &start, NULL);
+
+ reserved = intel_allocator_reserve(ialh, 0, 0x1000, start);
+ igt_assert(reserved);
+
+ reserved = intel_allocator_is_reserved(ialh, 0x1000, start);
+ igt_assert(reserved);
+
+ reserved = intel_allocator_reserve(ialh, 0, 0x1000, start);
+ igt_assert(!reserved);
+
+ unreserved = intel_allocator_unreserve(ialh, 0, 0x1000, start);
+ igt_assert(unreserved);
+
+ reserved = intel_allocator_is_reserved(ialh, 0x1000, start);
+ igt_assert(!reserved);
+
+ intel_allocator_close(ialh);
+}
+
+static void purge_bb(int fd)
+{
+ struct buf_ops *bops;
+ struct intel_buf *buf;
+ struct intel_bb *ibb;
+ uint64_t offset0, offset1;
+
+ bops = buf_ops_create(fd);
+ buf = intel_buf_create(bops, 512, 512, 32, 0, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ ibb = intel_bb_create(fd, 4096);
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_add_intel_buf(ibb, buf, false);
+ offset0 = buf->addr.offset;
+
+ intel_bb_reset(ibb, true);
+ buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
+
+ intel_bb_add_intel_buf(ibb, buf, false);
+ offset1 = buf->addr.offset;
+
+ igt_assert(offset0 == offset1);
+
+ intel_buf_destroy(buf);
+ intel_bb_destroy(ibb);
+ buf_ops_destroy(bops);
+}
+
+static void reserve(int fd, uint8_t type)
+{
+ struct intel_allocator *ial;
+ struct test_obj obj;
+
+ ial = from_user_pointer(intel_allocator_open(fd, 0, type));
+
+ igt_assert(ial->reserve(ial, 0, 0x40000, 0x800000));
+ /* try reserve once again */
+ igt_assert_eq(ial->reserve(ial, 0, 0x40040, 0x700000), false);
+
+ obj.handle = gem_handle_gen();
+ obj.size = OBJ_SIZE;
+ obj.offset = ial->alloc(ial, obj.handle, obj.size, 0);
+
+ igt_assert_eq(ial->reserve(ial, 0, obj.offset,
+ obj.offset + obj.size), false);
+ ial->free(ial, obj.handle);
+ igt_assert_eq(ial->reserve(ial, 0, obj.offset,
+ obj.offset + obj.size), true);
+
+ ial->unreserve(ial, 0, obj.offset, obj.offset + obj.size);
+ ial->unreserve(ial, 0, 0x40000, 0x800000);
+ igt_assert(ial->reserve(ial, 0, 0x40040, 0x700000));
+ ial->unreserve(ial, 0, 0x40040, 0x700000);
+
+ igt_assert(ial->is_empty(ial));
+
+ intel_allocator_close(to_user_pointer(ial));
+}
+
+static bool overlaps(struct test_obj *buf1, struct test_obj *buf2)
+{
+ uint64_t begin1 = buf1->offset;
+ uint64_t end1 = buf1->offset + buf1->size;
+ uint64_t begin2 = buf2->offset;
+ uint64_t end2 = buf2->offset + buf2->size;
+
+ return (end1 > begin2 && end2 > end1) || (end2 > begin1 && end1 > end2);
+}
+
+static void basic_alloc(int fd, int cnt, uint8_t type)
+{
+ struct test_obj *obj;
+ struct intel_allocator *ial;
+ int i, j;
+
+ ial = from_user_pointer(intel_allocator_open(fd, 0, type));
+ obj = malloc(sizeof(struct test_obj) * cnt);
+
+ for (i = 0; i < cnt; i++) {
+ igt_progress("allocating objects: ", i, cnt);
+ obj[i].handle = gem_handle_gen();
+ obj[i].size = OBJ_SIZE;
+ obj[i].offset = ial->alloc(ial, obj[i].handle,
+ obj[i].size, 4096);
+ igt_assert_eq(obj[i].offset % 4096, 0);
+ }
+
+ for (i = 0; i < cnt; i++) {
+ igt_progress("check overlapping: ", i, cnt);
+
+ if (type == INTEL_ALLOCATOR_RANDOM)
+ continue;
+
+ for (j = 0; j < cnt; j++) {
+ if (j == i)
+ continue;
+ igt_assert(!overlaps(&obj[i], &obj[j]));
+ }
+ }
+
+ for (i = 0; i < cnt; i++) {
+ igt_progress("freeing objects: ", i, cnt);
+ ial->free(ial, obj[i].handle);
+ }
+
+ igt_assert(ial->is_empty(ial));
+
+ free(obj);
+ intel_allocator_close(to_user_pointer(ial));
+}
+
+static void reuse(int fd, uint8_t type)
+{
+ struct test_obj obj[128], tmp;
+ struct intel_allocator *ial;
+ uint64_t prev_offset;
+ int i;
+
+ ial = from_user_pointer(intel_allocator_open(fd, 0, type));
+
+ for (i = 0; i < 128; i++) {
+ obj[i].handle = gem_handle_gen();
+ obj[i].size = OBJ_SIZE;
+ obj[i].offset = ial->alloc(ial, obj[i].handle,
+ obj[i].size, 0x40);
+ }
+
+ /* check simple reuse */
+ for (i = 0; i < 128; i++) {
+ prev_offset = obj[i].offset;
+ obj[i].offset = ial->alloc(ial, obj[i].handle, obj[i].size, 0);
+ igt_assert(prev_offset == obj[i].offset);
+ }
+ i--;
+
+ /* free bo prevously alloced */
+ ial->free(ial, obj[i].handle);
+ /* alloc different buffer to fill freed hole */
+ tmp.handle = gem_handle_gen();
+ tmp.offset = ial->alloc(ial, tmp.handle, OBJ_SIZE, 0);
+ igt_assert(prev_offset == tmp.offset);
+
+ obj[i].offset = ial->alloc(ial, obj[i].handle, obj[i].size, 0);
+ igt_assert(prev_offset != obj[i].offset);
+ ial->free(ial, tmp.handle);
+
+ for (i = 0; i < 128; i++)
+ ial->free(ial, obj[i].handle);
+
+ igt_assert(ial->is_empty(ial));
+
+ intel_allocator_close(to_user_pointer(ial));
+}
+
+struct ial_thread_args {
+ struct intel_allocator *ial;
+ pthread_t thread;
+ uint32_t *handles;
+ uint64_t *offsets;
+ uint32_t count;
+ int threads;
+ int idx;
+};
+
+static void *alloc_bo_in_thread(void *arg)
+{
+ struct ial_thread_args *a = arg;
+ int i;
+
+ for (i = a->idx; i < a->count; i += a->threads) {
+ a->handles[i] = gem_handle_gen();
+ pthread_mutex_lock(&a->ial->mutex);
+ a->offsets[i] = a->ial->alloc(a->ial, a->handles[i], OBJ_SIZE,
+ 1UL << ((random() % 20) + 1));
+ pthread_mutex_unlock(&a->ial->mutex);
+ }
+
+ return NULL;
+}
+
+static void *free_bo_in_thread(void *arg)
+{
+ struct ial_thread_args *a = arg;
+ int i;
+
+ for (i = (a->idx + 1) % a->threads; i < a->count; i += a->threads) {
+ pthread_mutex_lock(&a->ial->mutex);
+ a->ial->free(a->ial, a->handles[i]);
+ pthread_mutex_unlock(&a->ial->mutex);
+ }
+
+ return NULL;
+}
+
+#define THREADS 6
+
+static void parallel_one(int fd, uint8_t type)
+{
+ struct intel_allocator *ial;
+ struct ial_thread_args a[THREADS];
+ uint32_t *handles;
+ uint64_t *offsets;
+ int count, i;
+
+ srandom(0xdeadbeef);
+ ial = from_user_pointer(intel_allocator_open(fd, 0, type));
+ count = 1UL << 12;
+
+ handles = malloc(sizeof(uint32_t) * count);
+ offsets = calloc(1, sizeof(uint64_t) * count);
+
+ for (i = 0; i < THREADS; i++) {
+ a[i].ial = ial;
+ a[i].handles = handles;
+ a[i].offsets = offsets;
+ a[i].count = count;
+ a[i].threads = THREADS;
+ a[i].idx = i;
+ pthread_create(&a[i].thread, NULL, alloc_bo_in_thread, &a[i]);
+ }
+
+ for (i = 0; i < THREADS; i++)
+ pthread_join(a[i].thread, NULL);
+
+ /* Check if all objects are alocated */
+ for (i = 0; i < count; i++) {
+ /* Random allocator don't have state. Always returns different offset */
+ if (type == INTEL_ALLOCATOR_RANDOM)
+ break;
+
+ igt_assert_eq(offsets[i],
+ a->ial->alloc(ial, handles[i], OBJ_SIZE, 0));
+ }
+
+ for (i = 0; i < THREADS; i++)
+ pthread_create(&a[i].thread, NULL, free_bo_in_thread, &a[i]);
+
+ for (i = 0; i < THREADS; i++)
+ pthread_join(a[i].thread, NULL);
+
+ /* Check if all offsets where objects were are free */
+ for (i = 0; i < count; i++) {
+ if (type == INTEL_ALLOCATOR_RANDOM)
+ break;
+
+ igt_assert(ial->reserve(ial, 0, offsets[i], offsets[i] + 1));
+ }
+
+ free(handles);
+ free(offsets);
+
+ intel_allocator_close(to_user_pointer(ial));
+}
+
+#define SIMPLE_GROUP_ALLOCS 1
+static void __simple_allocs(int fd)
+{
+ uint32_t handles[SIMPLE_GROUP_ALLOCS];
+ uint64_t ahnd;
+ uint32_t ctx;
+ int i;
+
+ ctx = rand() % 2;
+ ahnd = intel_allocator_open(fd, ctx, INTEL_ALLOCATOR_SIMPLE);
+
+ for (i = 0; i < SIMPLE_GROUP_ALLOCS; i++) {
+ uint32_t size;
+
+ size = (rand() % 4 + 1) * 0x1000;
+ handles[i] = gem_create(fd, size);
+ intel_allocator_alloc(ahnd, handles[i], size, 0x1000);
+ }
+
+ for (i = 0; i < SIMPLE_GROUP_ALLOCS; i++) {
+ igt_assert_f(intel_allocator_free(ahnd, handles[i]) == 1,
+ "Error freeing handle: %u\n", handles[i]);
+ gem_close(fd, handles[i]);
+ }
+
+ intel_allocator_close(ahnd);
+}
+
+static void fork_simple_once(int fd)
+{
+ intel_allocator_multiprocess_start();
+
+ igt_fork(child, 1)
+ __simple_allocs(fd);
+
+ igt_waitchildren();
+
+ intel_allocator_multiprocess_stop();
+}
+
+#define SIMPLE_TIMEOUT 5
+static void *__fork_simple_thread(void *data)
+{
+ int fd = (int) (long) data;
+
+ igt_until_timeout(SIMPLE_TIMEOUT) {
+ __simple_allocs(fd);
+ }
+
+ return NULL;
+}
+
+static void fork_simple_stress(int fd, bool two_level_inception)
+{
+ pthread_t thread0, thread1;
+ uint64_t ahnd0, ahnd1;
+ bool are_empty;
+
+ intel_allocator_multiprocess_start();
+
+ ahnd0 = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+ ahnd1 = intel_allocator_open(fd, 1, INTEL_ALLOCATOR_SIMPLE);
+
+ pthread_create(&thread0, NULL, __fork_simple_thread, (void *) (long) fd);
+ pthread_create(&thread1, NULL, __fork_simple_thread, (void *) (long) fd);
+
+ igt_fork(child, 8) {
+ if (two_level_inception) {
+ pthread_create(&thread0, NULL, __fork_simple_thread,
+ (void *) (long) fd);
+ pthread_create(&thread1, NULL, __fork_simple_thread,
+ (void *) (long) fd);
+ }
+
+ igt_until_timeout(SIMPLE_TIMEOUT) {
+ __simple_allocs(fd);
+ }
+
+ if (two_level_inception) {
+ pthread_join(thread0, NULL);
+ pthread_join(thread1, NULL);
+ }
+ }
+ igt_waitchildren();
+
+ pthread_join(thread0, NULL);
+ pthread_join(thread1, NULL);
+
+ are_empty = intel_allocator_close(ahnd0);
+ are_empty &= intel_allocator_close(ahnd1);
+
+ intel_allocator_multiprocess_stop();
+
+ igt_assert_f(are_empty, "Allocators were not emptied\n");
+}
+
+static void __reopen_allocs(int fd1, int fd2)
+{
+ uint64_t ahnd0, ahnd1, ahnd2;
+
+ ahnd0 = intel_allocator_open(fd1, 0, INTEL_ALLOCATOR_SIMPLE);
+ ahnd1 = intel_allocator_open(fd2, 0, INTEL_ALLOCATOR_SIMPLE);
+ ahnd2 = intel_allocator_open(fd2, 0, INTEL_ALLOCATOR_SIMPLE);
+ igt_assert(ahnd0 != ahnd1);
+ igt_assert(ahnd1 == ahnd2);
+
+ intel_allocator_close(ahnd0);
+ intel_allocator_close(ahnd1);
+ intel_allocator_close(ahnd2);
+}
+
+static void reopen(int fd)
+{
+ int fd2;
+
+ igt_require_gem(fd);
+
+ fd2 = gem_reopen_driver(fd);
+
+ __reopen_allocs(fd, fd2);
+
+ close(fd2);
+}
+
+#define REOPEN_TIMEOUT 3
+static void reopen_fork(int fd)
+{
+ int fd2;
+
+ igt_require_gem(fd);
+
+ intel_allocator_multiprocess_start();
+
+ fd2 = gem_reopen_driver(fd);
+
+ igt_fork(child, 1) {
+ igt_until_timeout(REOPEN_TIMEOUT)
+ __reopen_allocs(fd, fd2);
+ }
+ igt_until_timeout(REOPEN_TIMEOUT)
+ __reopen_allocs(fd, fd2);
+
+ igt_waitchildren();
+
+ close(fd2);
+
+ intel_allocator_multiprocess_stop();
+}
+
+struct allocators {
+ const char *name;
+ uint8_t type;
+} als[] = {
+ {"simple", INTEL_ALLOCATOR_SIMPLE},
+ {"random", INTEL_ALLOCATOR_RANDOM},
+ {NULL, 0},
+};
+
+igt_main
+{
+ int fd;
+ struct allocators *a;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_INTEL);
+ atomic_init(&next_handle, 1);
+ srandom(0xdeadbeef);
+ }
+
+ igt_subtest_f("alloc-simple")
+ alloc_simple(fd);
+
+ igt_subtest_f("reserve-simple")
+ reserve_simple(fd);
+
+ igt_subtest_f("purge-bb")
+ purge_bb(fd);
+
+ igt_subtest_f("print")
+ basic_alloc(fd, 1UL << 2, INTEL_ALLOCATOR_RANDOM);
+
+ igt_subtest_f("reuse")
+ reuse(fd, INTEL_ALLOCATOR_SIMPLE);
+
+ igt_subtest_f("reserve")
+ reserve(fd, INTEL_ALLOCATOR_SIMPLE);
+
+ for (a = als; a->name; a++) {
+ igt_subtest_with_dynamic_f("%s-allocator", a->name) {
+ igt_dynamic("basic")
+ basic_alloc(fd, 1UL << 8, a->type);
+
+ igt_dynamic("parallel-one")
+ parallel_one(fd, a->type);
+
+ if (a->type != INTEL_ALLOCATOR_RANDOM) {
+ igt_dynamic("reuse")
+ reuse(fd, a->type);
+
+ igt_dynamic("reserve")
+ reserve(fd, a->type);
+ }
+ }
+ }
+
+ igt_subtest_f("fork-simple-once")
+ fork_simple_once(fd);
+
+ igt_subtest_f("fork-simple-stress")
+ fork_simple_stress(fd, false);
+
+ igt_subtest_f("fork-simple-stress-signal") {
+ igt_fork_signal_helper();
+ fork_simple_stress(fd, false);
+ igt_stop_signal_helper();
+ }
+
+ igt_subtest_f("two-level-inception")
+ fork_simple_stress(fd, true);
+
+ igt_subtest_f("two-level-inception-interruptible") {
+ igt_fork_signal_helper();
+ fork_simple_stress(fd, true);
+ igt_stop_signal_helper();
+ }
+
+ igt_subtest_f("reopen")
+ reopen(fd);
+
+ igt_subtest_f("reopen-fork")
+ reopen_fork(fd);
+
+ igt_fixture
+ close(fd);
+}
diff --git a/tests/meson.build b/tests/meson.build
index 71516981..4ad05ca0 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -109,6 +109,7 @@ test_progs = [
]
i915_progs = [
+ 'api_intel_allocator',
'api_intel_bb',
'gen3_mixed_blits',
'gen3_render_linear_blits',
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 18/23] tests/gem|kms: Remove intel_bb from fixture
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (16 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 17/23] tests/api_intel_allocator: Simple allocator test suite Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 19/23] tests/gem_mmap_offset: Use intel_buf wrapper code instead direct Zbigniew Kempczyński
` (8 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
As intel_bb "opens" connection to allocator when test completes it can
leave allocator in unknown state (mostly in failed tests). As igt_core
was armed in resetting allocator infrastructure connection to it inside
intel_bb is not valid anymore. Trying to use it leads to catastrofic
errors.
Migrate intel_bb out of fixture and create it inside tests individually.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_caching.c | 14 ++++++++--
tests/i915/gem_partial_pwrite_pread.c | 40 +++++++++++++++++----------
tests/i915/gem_render_copy.c | 31 ++++++++++-----------
tests/kms_big_fb.c | 12 +++++---
4 files changed, 61 insertions(+), 36 deletions(-)
diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index bdaff68a..4e844952 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -158,7 +158,6 @@ igt_main
flags = 0;
}
data.bops = buf_ops_create(data.fd);
- ibb = intel_bb_create(data.fd, PAGE_SIZE);
scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
32, 0, I915_TILING_NONE, 0);
@@ -174,6 +173,8 @@ igt_main
igt_info("checking partial reads\n");
+ ibb = intel_bb_create(data.fd, PAGE_SIZE);
+
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i;
int start, len;
@@ -195,11 +196,15 @@ igt_main
igt_progress("partial reads test: ", i, ROUNDS);
}
+
+ intel_bb_destroy(ibb);
}
igt_subtest("writes") {
igt_require(flags & TEST_WRITE);
+ ibb = intel_bb_create(data.fd, PAGE_SIZE);
+
igt_info("checking partial writes\n");
for (i = 0; i < ROUNDS; i++) {
@@ -240,11 +245,15 @@ igt_main
igt_progress("partial writes test: ", i, ROUNDS);
}
+
+ intel_bb_destroy(ibb);
}
igt_subtest("read-writes") {
igt_require((flags & TEST_BOTH) == TEST_BOTH);
+ ibb = intel_bb_create(data.fd, PAGE_SIZE);
+
igt_info("checking partial writes after partial reads\n");
for (i = 0; i < ROUNDS; i++) {
@@ -307,10 +316,11 @@ igt_main
igt_progress("partial read/writes test: ", i, ROUNDS);
}
+
+ intel_bb_destroy(ibb);
}
igt_fixture {
- intel_bb_destroy(ibb);
intel_buf_destroy(scratch_buf);
intel_buf_destroy(staging_buf);
buf_ops_destroy(data.bops);
diff --git a/tests/i915/gem_partial_pwrite_pread.c b/tests/i915/gem_partial_pwrite_pread.c
index 72c33539..c2ca561e 100644
--- a/tests/i915/gem_partial_pwrite_pread.c
+++ b/tests/i915/gem_partial_pwrite_pread.c
@@ -53,7 +53,6 @@ IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial"
#define PAGE_SIZE 4096
#define BO_SIZE (4*4096)
-struct intel_bb *ibb;
struct intel_buf *scratch_buf;
struct intel_buf *staging_buf;
@@ -77,7 +76,8 @@ static void *__try_gtt_map_first(data_t *data, struct intel_buf *buf,
return ptr;
}
-static void copy_bo(struct intel_buf *src, struct intel_buf *dst)
+static void copy_bo(struct intel_bb *ibb,
+ struct intel_buf *src, struct intel_buf *dst)
{
bool has_64b_reloc;
@@ -109,8 +109,8 @@ static void copy_bo(struct intel_buf *src, struct intel_buf *dst)
}
static void
-blt_bo_fill(data_t *data, struct intel_buf *tmp_bo,
- struct intel_buf *bo, uint8_t val)
+blt_bo_fill(data_t *data, struct intel_bb *ibb,
+ struct intel_buf *tmp_bo, struct intel_buf *bo, uint8_t val)
{
uint8_t *gtt_ptr;
int i;
@@ -124,7 +124,7 @@ blt_bo_fill(data_t *data, struct intel_buf *tmp_bo,
igt_drop_caches_set(data->drm_fd, DROP_BOUND);
- copy_bo(tmp_bo, bo);
+ copy_bo(ibb, tmp_bo, bo);
}
#define MAX_BLT_SIZE 128
@@ -139,14 +139,17 @@ static void get_range(int *start, int *len)
static void test_partial_reads(data_t *data)
{
+ struct intel_bb *ibb;
int i, j;
+ ibb = intel_bb_create(data->drm_fd, PAGE_SIZE);
+
igt_info("checking partial reads\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val = i;
int start, len;
- blt_bo_fill(data, staging_buf, scratch_buf, val);
+ blt_bo_fill(data, ibb, staging_buf, scratch_buf, val);
get_range(&start, &len);
gem_read(data->drm_fd, scratch_buf->handle, start, tmp, len);
@@ -159,26 +162,31 @@ static void test_partial_reads(data_t *data)
igt_progress("partial reads test: ", i, ROUNDS);
}
+
+ intel_bb_destroy(ibb);
}
static void test_partial_writes(data_t *data)
{
+ struct intel_bb *ibb;
int i, j;
uint8_t *gtt_ptr;
+ ibb = intel_bb_create(data->drm_fd, PAGE_SIZE);
+
igt_info("checking partial writes\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val = i;
int start, len;
- blt_bo_fill(data, staging_buf, scratch_buf, val);
+ blt_bo_fill(data, ibb, staging_buf, scratch_buf, val);
memset(tmp, i + 63, BO_SIZE);
get_range(&start, &len);
gem_write(data->drm_fd, scratch_buf->handle, start, tmp, len);
- copy_bo(scratch_buf, staging_buf);
+ copy_bo(ibb, scratch_buf, staging_buf);
gtt_ptr = __try_gtt_map_first(data, staging_buf, 0);
for (j = 0; j < start; j++) {
@@ -200,19 +208,24 @@ static void test_partial_writes(data_t *data)
igt_progress("partial writes test: ", i, ROUNDS);
}
+
+ intel_bb_destroy(ibb);
}
static void test_partial_read_writes(data_t *data)
{
+ struct intel_bb *ibb;
int i, j;
uint8_t *gtt_ptr;
+ ibb = intel_bb_create(data->drm_fd, PAGE_SIZE);
+
igt_info("checking partial writes after partial reads\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val = i;
int start, len;
- blt_bo_fill(data, staging_buf, scratch_buf, val);
+ blt_bo_fill(data, ibb, staging_buf, scratch_buf, val);
/* partial read */
get_range(&start, &len);
@@ -226,7 +239,7 @@ static void test_partial_read_writes(data_t *data)
/* Change contents through gtt to make the pread cachelines
* stale. */
val += 17;
- blt_bo_fill(data, staging_buf, scratch_buf, val);
+ blt_bo_fill(data, ibb, staging_buf, scratch_buf, val);
/* partial write */
memset(tmp, i + 63, BO_SIZE);
@@ -234,7 +247,7 @@ static void test_partial_read_writes(data_t *data)
get_range(&start, &len);
gem_write(data->drm_fd, scratch_buf->handle, start, tmp, len);
- copy_bo(scratch_buf, staging_buf);
+ copy_bo(ibb, scratch_buf, staging_buf);
gtt_ptr = __try_gtt_map_first(data, staging_buf, 0);
for (j = 0; j < start; j++) {
@@ -256,6 +269,8 @@ static void test_partial_read_writes(data_t *data)
igt_progress("partial read/writes test: ", i, ROUNDS);
}
+
+ intel_bb_destroy(ibb);
}
static void do_tests(data_t *data, int cache_level, const char *suffix)
@@ -288,8 +303,6 @@ igt_main
data.devid = intel_get_drm_devid(data.drm_fd);
data.bops = buf_ops_create(data.drm_fd);
- ibb = intel_bb_create(data.drm_fd, PAGE_SIZE);
-
/* overallocate the buffers we're actually using because */
scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1, 32, 0, I915_TILING_NONE, 0);
staging_buf = intel_buf_create(data.bops, BO_SIZE/4, 1, 32, 0, I915_TILING_NONE, 0);
@@ -303,7 +316,6 @@ igt_main
do_tests(&data, 2, "-display");
igt_fixture {
- intel_bb_destroy(ibb);
intel_buf_destroy(scratch_buf);
intel_buf_destroy(staging_buf);
buf_ops_destroy(data.bops);
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index afc490f1..e48b5b99 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -58,7 +58,6 @@ typedef struct {
int drm_fd;
uint32_t devid;
struct buf_ops *bops;
- struct intel_bb *ibb;
igt_render_copyfunc_t render_copy;
igt_vebox_copyfunc_t vebox_copy;
} data_t;
@@ -341,6 +340,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
enum i915_compression dst_compression,
int flags)
{
+ struct intel_bb *ibb;
struct intel_buf ref, src_tiled, src_ccs, dst_ccs, dst;
struct {
struct intel_buf buf;
@@ -397,6 +397,8 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
src_compressed || dst_compressed)
igt_require(intel_gen(data->devid) >= 9);
+ ibb = intel_bb_create(data->drm_fd, 4096);
+
for (int i = 0; i < num_src; i++)
scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling,
I915_COMPRESSION_NONE);
@@ -456,12 +458,12 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
*/
if (src_mixed_tiled) {
if (dst_compressed)
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&dst, 0, 0, WIDTH, HEIGHT,
&dst_ccs, 0, 0);
for (int i = 0; i < num_src; i++) {
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&src[i].buf,
WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
dst_compressed ? &dst_ccs : &dst,
@@ -469,13 +471,13 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
}
if (dst_compressed)
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&dst_ccs, 0, 0, WIDTH, HEIGHT,
&dst, 0, 0);
} else {
if (src_compression == I915_COMPRESSION_RENDER) {
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&src_tiled, 0, 0, WIDTH, HEIGHT,
&src_ccs,
0, 0);
@@ -486,7 +488,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
"render-src_ccs.bin");
}
} else if (src_compression == I915_COMPRESSION_MEDIA) {
- data->vebox_copy(data->ibb,
+ data->vebox_copy(ibb,
&src_tiled, WIDTH, HEIGHT,
&src_ccs);
if (dump_compressed_src_buf) {
@@ -498,34 +500,34 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
}
if (dst_compression == I915_COMPRESSION_RENDER) {
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
src_compressed ? &src_ccs : &src_tiled,
0, 0, WIDTH, HEIGHT,
&dst_ccs,
0, 0);
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&dst_ccs,
0, 0, WIDTH, HEIGHT,
&dst,
0, 0);
} else if (dst_compression == I915_COMPRESSION_MEDIA) {
- data->vebox_copy(data->ibb,
+ data->vebox_copy(ibb,
src_compressed ? &src_ccs : &src_tiled,
WIDTH, HEIGHT,
&dst_ccs);
- data->vebox_copy(data->ibb,
+ data->vebox_copy(ibb,
&dst_ccs,
WIDTH, HEIGHT,
&dst);
} else if (force_vebox_dst_copy) {
- data->vebox_copy(data->ibb,
+ data->vebox_copy(ibb,
src_compressed ? &src_ccs : &src_tiled,
WIDTH, HEIGHT,
&dst);
} else {
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
src_compressed ? &src_ccs : &src_tiled,
0, 0, WIDTH, HEIGHT,
&dst,
@@ -572,8 +574,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
for (int i = 0; i < num_src; i++)
scratch_buf_fini(&src[i].buf);
- /* handles gone, need to clean the objects cache within intel_bb */
- intel_bb_reset(data->ibb, true);
+ intel_bb_destroy(ibb);
}
static int opt_handler(int opt, int opt_index, void *data)
@@ -796,7 +797,6 @@ igt_main_args("dac", NULL, help_str, opt_handler, NULL)
data.vebox_copy = igt_get_vebox_copyfunc(data.devid);
data.bops = buf_ops_create(data.drm_fd);
- data.ibb = intel_bb_create(data.drm_fd, 4096);
igt_fork_hang_detector(data.drm_fd);
}
@@ -849,7 +849,6 @@ igt_main_args("dac", NULL, help_str, opt_handler, NULL)
igt_fixture {
igt_stop_hang_detector();
- intel_bb_destroy(data.ibb);
buf_ops_destroy(data.bops);
}
}
diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c
index 02e9915b..445d7bb0 100644
--- a/tests/kms_big_fb.c
+++ b/tests/kms_big_fb.c
@@ -662,7 +662,6 @@ igt_main
data.render_copy = igt_get_render_copyfunc(data.devid);
data.bops = buf_ops_create(data.drm_fd);
- data.ibb = intel_bb_create(data.drm_fd, 4096);
}
/*
@@ -675,7 +674,9 @@ igt_main
igt_subtest_f("%s-addfb-size-overflow",
modifiers[i].name) {
data.modifier = modifiers[i].modifier;
+ data.ibb = intel_bb_create(data.drm_fd, 4096);
test_size_overflow(&data);
+ intel_bb_destroy(data.ibb);
}
}
@@ -683,15 +684,18 @@ igt_main
igt_subtest_f("%s-addfb-size-offset-overflow",
modifiers[i].name) {
data.modifier = modifiers[i].modifier;
+ data.ibb = intel_bb_create(data.drm_fd, 4096);
test_size_offset_overflow(&data);
+ intel_bb_destroy(data.ibb);
}
}
for (int i = 0; i < ARRAY_SIZE(modifiers); i++) {
igt_subtest_f("%s-addfb", modifiers[i].name) {
data.modifier = modifiers[i].modifier;
-
+ data.ibb = intel_bb_create(data.drm_fd, 4096);
test_addfb(&data);
+ intel_bb_destroy(data.ibb);
}
}
@@ -709,7 +713,9 @@ igt_main
igt_require(data.format == DRM_FORMAT_C8 ||
igt_fb_supported_format(data.format));
igt_require(igt_display_has_format_mod(&data.display, data.format, data.modifier));
+ data.ibb = intel_bb_create(data.drm_fd, 4096);
test_scanout(&data);
+ intel_bb_destroy(data.ibb);
}
}
@@ -720,8 +726,6 @@ igt_main
igt_fixture {
igt_display_fini(&data.display);
-
- intel_bb_destroy(data.ibb);
buf_ops_destroy(data.bops);
}
}
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 19/23] tests/gem_mmap_offset: Use intel_buf wrapper code instead direct
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (17 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 18/23] tests/gem|kms: Remove intel_bb from fixture Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 20/23] tests/gem_ppgtt: Adopt test to use intel_bb with allocator Zbigniew Kempczyński
` (7 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
Generally when playing with intel_buf we should use wrapper code
instead of adding it to intel_bb directly. Code checks required
alignment on specific gens so protects us from passing unaligned
properly addresses.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_mmap_offset.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
index 8b29d0a0..8f200627 100644
--- a/tests/i915/gem_mmap_offset.c
+++ b/tests/i915/gem_mmap_offset.c
@@ -614,8 +614,8 @@ static void blt_coherency(int i915)
dst = create_bo(bops, 1, width, height);
size = src->surface[0].size;
- intel_bb_add_object(ibb, src->handle, size, src->addr.offset, false);
- intel_bb_add_object(ibb, dst->handle, size, dst->addr.offset, true);
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, dst, true);
intel_bb_blt_copy(ibb,
src, 0, 0, src->surface[0].stride,
--
2.26.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 20/23] tests/gem_ppgtt: Adopt test to use intel_bb with allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (18 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 19/23] tests/gem_mmap_offset: Use intel_buf wrapper code instead direct Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 21/23] tests/gem_render_copy_redux: Adopt to use with intel_bb and allocator Zbigniew Kempczyński
` (6 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
Tests work in multiprocess environment so we must turn on/off
thread in parent process which is responsible for allocations.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_ppgtt.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index 73bd19c5..b9b3d1fc 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -136,6 +136,7 @@ static void fork_rcs_copy(int timeout, uint32_t final,
dst[child], 0, 0);
intel_buf_destroy(src);
+ dst[child]->addr.offset = INTEL_BUF_INVALID_ADDRESS;
intel_bb_destroy(ibb);
}
@@ -175,6 +176,7 @@ static void fork_bcs_copy(int timeout, uint32_t final,
intel_buf_destroy(src[1]);
intel_buf_destroy(src[0]);
+ intel_bb_reset(ibb, true);
}
src[0] = create_bo(dst[child]->bops, ~0);
@@ -190,6 +192,7 @@ static void fork_bcs_copy(int timeout, uint32_t final,
intel_buf_destroy(src[1]);
intel_buf_destroy(src[0]);
+ dst[child]->addr.offset = INTEL_BUF_INVALID_ADDRESS;
intel_bb_destroy(ibb);
}
@@ -288,6 +291,8 @@ igt_main
igt_subtest("blt-vs-render-ctx0") {
struct intel_buf *bcs[1], *rcs[N_CHILD];
+ intel_allocator_multiprocess_start();
+
fork_bcs_copy(30, 0x4000, bcs, 1);
fork_rcs_copy(30, 0x8000 / N_CHILD, rcs, N_CHILD, 0);
@@ -298,6 +303,8 @@ igt_main
cleanup_bufs(bcs, 1);
cleanup_bufs(rcs, N_CHILD);
+
+ intel_allocator_multiprocess_stop();
}
igt_subtest("blt-vs-render-ctxN") {
@@ -305,6 +312,8 @@ igt_main
igt_require(has_contexts());
+ intel_allocator_multiprocess_start();
+
fork_rcs_copy(30, 0x8000 / N_CHILD, rcs, N_CHILD, CREATE_CONTEXT);
fork_bcs_copy(30, 0x4000, bcs, 1);
@@ -315,6 +324,8 @@ igt_main
cleanup_bufs(bcs, 1);
cleanup_bufs(rcs, N_CHILD);
+
+ intel_allocator_multiprocess_stop();
}
igt_subtest("flink-and-close-vma-leak")
--
2.26.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 21/23] tests/gem_render_copy_redux: Adopt to use with intel_bb and allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (19 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 20/23] tests/gem_ppgtt: Adopt test to use intel_bb with allocator Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 22/23] tests/perf.c: Remove buffer from batch Zbigniew Kempczyński
` (5 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
As intel_bb has some strong requirements when allocator is in use
(addresses cannot move when simple allocator is used) ensure gem
buffer which is created from flink will reacquire new address.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_render_copy_redux.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/tests/i915/gem_render_copy_redux.c b/tests/i915/gem_render_copy_redux.c
index 8e633567..0d2d593e 100644
--- a/tests/i915/gem_render_copy_redux.c
+++ b/tests/i915/gem_render_copy_redux.c
@@ -63,7 +63,6 @@ typedef struct {
int fd;
uint32_t devid;
struct buf_ops *bops;
- struct intel_bb *ibb;
igt_render_copyfunc_t render_copy;
uint32_t linear[WIDTH * HEIGHT];
} data_t;
@@ -77,13 +76,10 @@ static void data_init(data_t *data)
data->render_copy = igt_get_render_copyfunc(data->devid);
igt_require_f(data->render_copy,
"no render-copy function\n");
-
- data->ibb = intel_bb_create(data->fd, 4096);
}
static void data_fini(data_t *data)
{
- intel_bb_destroy(data->ibb);
buf_ops_destroy(data->bops);
close(data->fd);
}
@@ -126,15 +122,17 @@ scratch_buf_check(data_t *data, struct intel_buf *buf, int x, int y,
static void copy(data_t *data)
{
+ struct intel_bb *ibb;
struct intel_buf src, dst;
+ ibb = intel_bb_create(data->fd, 4096);
scratch_buf_init(data, &src, WIDTH, HEIGHT, STRIDE, SRC_COLOR);
scratch_buf_init(data, &dst, WIDTH, HEIGHT, STRIDE, DST_COLOR);
scratch_buf_check(data, &src, WIDTH / 2, HEIGHT / 2, SRC_COLOR);
scratch_buf_check(data, &dst, WIDTH / 2, HEIGHT / 2, DST_COLOR);
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&src, 0, 0, WIDTH, HEIGHT,
&dst, WIDTH / 2, HEIGHT / 2);
@@ -143,11 +141,13 @@ static void copy(data_t *data)
scratch_buf_fini(data, &src);
scratch_buf_fini(data, &dst);
+ intel_bb_destroy(ibb);
}
static void copy_flink(data_t *data)
{
data_t local;
+ struct intel_bb *ibb, *local_ibb;
struct intel_buf src, dst;
struct intel_buf local_src, local_dst;
struct intel_buf flink;
@@ -155,25 +155,29 @@ static void copy_flink(data_t *data)
data_init(&local);
+ ibb = intel_bb_create(data->fd, 4096);
+ local_ibb = intel_bb_create(local.fd, 4096);
scratch_buf_init(data, &src, WIDTH, HEIGHT, STRIDE, 0);
scratch_buf_init(data, &dst, WIDTH, HEIGHT, STRIDE, DST_COLOR);
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&src, 0, 0, WIDTH, HEIGHT,
&dst, WIDTH, HEIGHT);
scratch_buf_init(&local, &local_src, WIDTH, HEIGHT, STRIDE, 0);
scratch_buf_init(&local, &local_dst, WIDTH, HEIGHT, STRIDE, SRC_COLOR);
- local.render_copy(local.ibb,
+ local.render_copy(local_ibb,
&local_src, 0, 0, WIDTH, HEIGHT,
&local_dst, WIDTH, HEIGHT);
name = gem_flink(local.fd, local_dst.handle);
flink = local_dst;
flink.handle = gem_open(data->fd, name);
+ flink.ibb = ibb;
+ flink.addr.offset = INTEL_BUF_INVALID_ADDRESS;
- data->render_copy(data->ibb,
+ data->render_copy(ibb,
&flink, 0, 0, WIDTH, HEIGHT,
&dst, WIDTH / 2, HEIGHT / 2);
@@ -183,7 +187,6 @@ static void copy_flink(data_t *data)
scratch_buf_check(data, &dst, 10, 10, DST_COLOR);
scratch_buf_check(data, &dst, WIDTH - 10, HEIGHT - 10, SRC_COLOR);
- intel_bb_reset(data->ibb, true);
scratch_buf_fini(data, &src);
scratch_buf_fini(data, &flink);
scratch_buf_fini(data, &dst);
@@ -191,6 +194,8 @@ static void copy_flink(data_t *data)
scratch_buf_fini(&local, &local_src);
scratch_buf_fini(&local, &local_dst);
+ intel_bb_destroy(local_ibb);
+ intel_bb_destroy(ibb);
data_fini(&local);
}
--
2.26.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 22/23] tests/perf.c: Remove buffer from batch
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (20 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 21/23] tests/gem_render_copy_redux: Adopt to use with intel_bb and allocator Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 23/23] tests/gem_linear_blits: Use intel allocator Zbigniew Kempczyński
` (4 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
Currently we need to ensure intel_buf is a part of single ibb due
to fact it is acquiring address from allocator so we cannot keep
it in two separate ibbs (theoretically it is possible when different
ibbs would be in same context but it is not currently implemented).
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/perf.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/tests/i915/perf.c b/tests/i915/perf.c
index a5c4adc3..e596afd3 100644
--- a/tests/i915/perf.c
+++ b/tests/i915/perf.c
@@ -3430,6 +3430,9 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
/* Another redundant flush to clarify batch bo is free to reuse */
intel_bb_flush_render(ibb0);
+ /* Remove intel_buf from ibb0 added implicitly in rendercopy */
+ intel_bb_remove_intel_buf(ibb0, dst_buf);
+
/* submit two copies on the other context to avoid a false
* positive in case the driver somehow ended up filtering for
* context1
@@ -3823,6 +3826,9 @@ static void gen12_single_ctx_helper(void)
BO_REPORT_ID0);
intel_bb_flush_render(ibb0);
+ /* Remove intel_buf from ibb0 added implicitly in rendercopy */
+ intel_bb_remove_intel_buf(ibb0, dst_buf);
+
/* This is the work/context that is measured for counter increments */
render_copy(ibb0,
&src[0], 0, 0, width, height,
@@ -3869,6 +3875,9 @@ static void gen12_single_ctx_helper(void)
BO_REPORT_ID3);
intel_bb_flush_render(ibb1);
+ /* Remove intel_buf from ibb1 added implicitly in rendercopy */
+ intel_bb_remove_intel_buf(ibb1, dst_buf);
+
/* Submit an mi-rpc to context0 after all measurable work */
#define BO_TIMESTAMP_OFFSET1 1032
#define BO_REPORT_OFFSET1 256
--
2.26.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] [PATCH i-g-t v3 23/23] tests/gem_linear_blits: Use intel allocator
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (21 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 22/23] tests/perf.c: Remove buffer from batch Zbigniew Kempczyński
@ 2020-10-23 12:42 ` Zbigniew Kempczyński
2020-10-23 13:10 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce IGT allocator (rev3) Patchwork
` (3 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-23 12:42 UTC (permalink / raw)
To: igt-dev; +Cc: Chris Wilson
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Use intel allocator directly, without intel-bb infrastructure.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_linear_blits.c | 103 ++++++++++++++++++++++++----------
1 file changed, 73 insertions(+), 30 deletions(-)
diff --git a/tests/i915/gem_linear_blits.c b/tests/i915/gem_linear_blits.c
index cae42d52..372d6ad8 100644
--- a/tests/i915/gem_linear_blits.c
+++ b/tests/i915/gem_linear_blits.c
@@ -56,12 +56,14 @@ IGT_TEST_DESCRIPTION("Test doing many blits with a working set larger than the"
static uint32_t linear[WIDTH*HEIGHT];
static void
-copy(int fd, uint32_t dst, uint32_t src)
+copy(int fd, uint64_t ahnd, uint32_t dst, uint32_t src,
+ uint64_t dst_offset, uint64_t src_offset)
{
uint32_t batch[12];
struct drm_i915_gem_relocation_entry reloc[2];
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_execbuffer2 exec;
+ bool do_relocs = false;
int i = 0;
batch[i++] = XY_SRC_COPY_BLT_CMD |
@@ -77,41 +79,59 @@ copy(int fd, uint32_t dst, uint32_t src)
WIDTH*4;
batch[i++] = 0; /* dst x1,y1 */
batch[i++] = (HEIGHT << 16) | WIDTH; /* dst x2,y2 */
- batch[i++] = 0; /* dst reloc */
+ batch[i++] = dst_offset;
if (intel_gen(intel_get_drm_devid(fd)) >= 8)
- batch[i++] = 0;
+ batch[i++] = dst_offset >> 32;
batch[i++] = 0; /* src x1,y1 */
batch[i++] = WIDTH*4;
- batch[i++] = 0; /* src reloc */
+ batch[i++] = src_offset;
if (intel_gen(intel_get_drm_devid(fd)) >= 8)
- batch[i++] = 0;
+ batch[i++] = src_offset >> 32;
batch[i++] = MI_BATCH_BUFFER_END;
batch[i++] = MI_NOOP;
- memset(reloc, 0, sizeof(reloc));
- reloc[0].target_handle = dst;
- reloc[0].delta = 0;
- reloc[0].offset = 4 * sizeof(batch[0]);
- reloc[0].presumed_offset = 0;
- reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
- reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
-
- reloc[1].target_handle = src;
- reloc[1].delta = 0;
- reloc[1].offset = 7 * sizeof(batch[0]);
- if (intel_gen(intel_get_drm_devid(fd)) >= 8)
- reloc[1].offset += sizeof(batch[0]);
- reloc[1].presumed_offset = 0;
- reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
- reloc[1].write_domain = 0;
-
memset(obj, 0, sizeof(obj));
obj[0].handle = dst;
obj[1].handle = src;
obj[2].handle = gem_create(fd, 4096);
gem_write(fd, obj[2].handle, 0, batch, i * sizeof(batch[0]));
- obj[2].relocation_count = 2;
- obj[2].relocs_ptr = to_user_pointer(reloc);
+
+ if (src_offset == 0 && dst_offset == 0) {
+ do_relocs = true;
+ memset(reloc, 0, sizeof(reloc));
+ reloc[0].target_handle = dst;
+ reloc[0].delta = 0;
+ reloc[0].offset = 4 * sizeof(batch[0]);
+ reloc[0].presumed_offset = 0;
+ reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+
+ reloc[1].target_handle = src;
+ reloc[1].delta = 0;
+ reloc[1].offset = 7 * sizeof(batch[0]);
+ if (intel_gen(intel_get_drm_devid(fd)) >= 8)
+ reloc[1].offset += sizeof(batch[0]);
+ reloc[1].presumed_offset = 0;
+ reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[1].write_domain = 0;
+
+ obj[2].relocation_count = 2;
+ obj[2].relocs_ptr = to_user_pointer(reloc);
+ } else {
+ obj[0].offset = CANONICAL(dst_offset);
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ obj[1].offset = CANONICAL(src_offset);
+ obj[1].flags = EXEC_OBJECT_PINNED |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ obj[2].offset = intel_allocator_alloc(ahnd, obj[2].handle,
+ sizeof(linear), 0);
+ obj[2].offset = CANONICAL(obj[2].offset);
+ obj[2].flags = EXEC_OBJECT_PINNED |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ }
memset(&exec, 0, sizeof(exec));
exec.buffers_ptr = to_user_pointer(obj);
@@ -120,6 +140,9 @@ copy(int fd, uint32_t dst, uint32_t src)
exec.flags = gem_has_blt(fd) ? I915_EXEC_BLT : 0;
gem_execbuf(fd, &exec);
+
+ if (!do_relocs)
+ intel_allocator_free(ahnd, obj[2].handle);
gem_close(fd, obj[2].handle);
}
@@ -157,17 +180,26 @@ check_bo(int fd, uint32_t handle, uint32_t val)
igt_assert_eq(num_errors, 0);
}
-static void run_test(int fd, int count)
+static void run_test(int fd, int count, bool do_relocs)
{
uint32_t *handle, *start_val;
+ uint64_t *offset, ahnd;
uint32_t start = 0;
int i;
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
handle = malloc(sizeof(uint32_t) * count * 2);
start_val = handle + count;
+ offset = calloc(1, sizeof(uint64_t) * count);
for (i = 0; i < count; i++) {
+
handle[i] = create_bo(fd, start);
+
+ if (!do_relocs)
+ offset[i] = intel_allocator_alloc(ahnd, handle[i],
+ sizeof(linear), 4096);
+
start_val[i] = start;
start += 1024 * 1024 / 4;
}
@@ -178,17 +210,20 @@ static void run_test(int fd, int count)
if (src == dst)
continue;
+ copy(fd, ahnd, handle[dst], handle[src], offset[dst], offset[src]);
- copy(fd, handle[dst], handle[src]);
start_val[dst] = start_val[src];
}
for (i = 0; i < count; i++) {
check_bo(fd, handle[i], start_val[i]);
+ if (!do_relocs)
+ intel_allocator_free(ahnd, handle[i]);
gem_close(fd, handle[i]);
}
free(handle);
+ intel_allocator_close(ahnd);
}
#define MAX_32b ((1ull << 32) - 4096)
@@ -197,38 +232,46 @@ igt_main
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
uint64_t count = 0;
+ bool do_relocs;
int fd = -1;
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
gem_require_blitter(fd);
+ do_relocs = !gem_uses_ppgtt(fd);
count = gem_aperture_size(fd);
if (count >> 32)
count = MAX_32b;
+ else
+ do_relocs = true;
+
count = 3 + count / (1024*1024);
igt_require(count > 1);
intel_require_memory(count, sizeof(linear), CHECK_RAM);
-
igt_debug("Using %'"PRIu64" 1MiB buffers\n", count);
count = (count + ncpus - 1) / ncpus;
}
igt_subtest("basic")
- run_test(fd, 2);
+ run_test(fd, 2, do_relocs);
igt_subtest("normal") {
+ intel_allocator_multiprocess_start();
igt_fork(child, ncpus)
- run_test(fd, count);
+ run_test(fd, count, do_relocs);
igt_waitchildren();
+ intel_allocator_multiprocess_stop();
}
igt_subtest("interruptible") {
+ intel_allocator_multiprocess_start();
igt_fork_signal_helper();
igt_fork(child, ncpus)
- run_test(fd, count);
+ run_test(fd, count, do_relocs);
igt_waitchildren();
igt_stop_signal_helper();
+ intel_allocator_multiprocess_stop();
}
}
--
2.26.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for Introduce IGT allocator (rev3)
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (22 preceding siblings ...)
2020-10-23 12:42 ` [igt-dev] [PATCH i-g-t v3 23/23] tests/gem_linear_blits: Use intel allocator Zbigniew Kempczyński
@ 2020-10-23 13:10 ` Patchwork
2020-10-23 15:29 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2020-10-23 13:10 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 2915 bytes --]
== Series Details ==
Series: Introduce IGT allocator (rev3)
URL : https://patchwork.freedesktop.org/series/82954/
State : success
== Summary ==
CI Bug Log - changes from IGT_5823 -> IGTPW_5092
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
Known issues
------------
Here are the changes found in IGTPW_5092 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5823 -> IGTPW_5092
CI-20190529: 20190529
CI_DRM_9190: a3d535579dd93942862b867b4452ba11e4f6bbb1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5092: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
IGT_5823: 7dd2fe99bd9dde00456cc5abf7e5ef0c8d7d6118 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@api_intel_allocator@alloc-simple
+igt@api_intel_allocator@fork-simple-once
+igt@api_intel_allocator@fork-simple-stress
+igt@api_intel_allocator@fork-simple-stress-signal
+igt@api_intel_allocator@print
+igt@api_intel_allocator@purge-bb
+igt@api_intel_allocator@random-allocator
+igt@api_intel_allocator@reopen
+igt@api_intel_allocator@reopen-fork
+igt@api_intel_allocator@reserve
+igt@api_intel_allocator@reserve-simple
+igt@api_intel_allocator@reuse
+igt@api_intel_allocator@simple-allocator
+igt@api_intel_allocator@two-level-inception
+igt@api_intel_allocator@two-level-inception-interruptible
+igt@api_intel_bb@add-remove-objects
+igt@api_intel_bb@blit-noreloc-keep-cache-random
+igt@api_intel_bb@blit-noreloc-purge-cache-random
+igt@api_intel_bb@destroy-bb
+igt@api_intel_bb@object-noreloc-keep-cache-random
+igt@api_intel_bb@object-noreloc-keep-cache-simple
+igt@api_intel_bb@object-noreloc-purge-cache-random
+igt@api_intel_bb@object-noreloc-purge-cache-simple
+igt@api_intel_bb@object-reloc-keep-cache
+igt@api_intel_bb@object-reloc-purge-cache
+igt@api_intel_bb@reset-bb
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
[-- Attachment #1.2: Type: text/html, Size: 3669 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread* [igt-dev] ✗ Fi.CI.IGT: failure for Introduce IGT allocator (rev3)
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (23 preceding siblings ...)
2020-10-23 13:10 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce IGT allocator (rev3) Patchwork
@ 2020-10-23 15:29 ` Patchwork
2020-10-26 5:30 ` Zbigniew Kempczyński
2020-10-26 5:43 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce IGT allocator (rev4) Patchwork
2020-10-26 6:44 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
26 siblings, 1 reply; 30+ messages in thread
From: Patchwork @ 2020-10-23 15:29 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
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== Series Details ==
Series: Introduce IGT allocator (rev3)
URL : https://patchwork.freedesktop.org/series/82954/
State : failure
== Summary ==
CI Bug Log - changes from IGT_5823_full -> IGTPW_5092_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5092_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5092_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5092_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-glk: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk8/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-glk2/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_reloc@basic-write-cpu-noreloc:
- shard-snb: [PASS][3] -> [FAIL][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-snb7/igt@gem_exec_reloc@basic-write-cpu-noreloc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-snb5/igt@gem_exec_reloc@basic-write-cpu-noreloc.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-hsw: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw1/igt@gem_userptr_blits@coherency-unsync.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-hsw6/igt@gem_userptr_blits@coherency-unsync.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@hotrebind}:
- shard-hsw: NOTRUN -> [WARN][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-hsw5/igt@core_hotunplug@hotrebind.html
New tests
---------
New tests have been introduced between IGT_5823_full and IGTPW_5092_full:
### New IGT tests (32) ###
* igt@api_intel_allocator@alloc-simple:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@fork-simple-once:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.04] s
* igt@api_intel_allocator@fork-simple-stress:
- Statuses : 7 pass(s)
- Exec time: [5.40, 5.60] s
* igt@api_intel_allocator@fork-simple-stress-signal:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.50] s
* igt@api_intel_allocator@print:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@purge-bb:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@api_intel_allocator@random-allocator:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@random-allocator@basic:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@api_intel_allocator@random-allocator@parallel-one:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_allocator@reopen:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_allocator@reopen-fork:
- Statuses : 7 pass(s)
- Exec time: [3.23, 3.26] s
* igt@api_intel_allocator@reserve:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@reserve-simple:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@reuse:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@simple-allocator:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@simple-allocator@basic:
- Statuses : 7 pass(s)
- Exec time: [0.00] s
* igt@api_intel_allocator@simple-allocator@parallel-one:
- Statuses : 7 pass(s)
- Exec time: [0.10, 0.21] s
* igt@api_intel_allocator@simple-allocator@reserve:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@simple-allocator@reuse:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@two-level-inception:
- Statuses : 7 pass(s)
- Exec time: [5.40, 5.61] s
* igt@api_intel_allocator@two-level-inception-interruptible:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.60] s
* igt@api_intel_bb@add-remove-objects:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-noreloc-keep-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@blit-noreloc-purge-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@destroy-bb:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.02] s
* igt@api_intel_bb@object-noreloc-keep-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-noreloc-keep-cache-simple:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-noreloc-purge-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-noreloc-purge-cache-simple:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-reloc-keep-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@object-reloc-purge-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@reset-bb:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
Known issues
------------
Here are the changes found in IGTPW_5092_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-noreloc-keep-cache:
- shard-hsw: [PASS][8] -> [SKIP][9] ([fdo#109271]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw2/igt@api_intel_bb@blit-noreloc-keep-cache.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-hsw8/igt@api_intel_bb@blit-noreloc-keep-cache.html
- shard-snb: [PASS][10] -> [SKIP][11] ([fdo#109271]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-snb2/igt@api_intel_bb@blit-noreloc-keep-cache.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-snb2/igt@api_intel_bb@blit-noreloc-keep-cache.html
* igt@core_hotunplug@hotrebind-lateclose:
- shard-iclb: [PASS][12] -> [DMESG-WARN][13] ([i915#1982])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb1/igt@core_hotunplug@hotrebind-lateclose.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-iclb5/igt@core_hotunplug@hotrebind-lateclose.html
* igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge:
- shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#1635] / [i915#1982]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl1/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-apl3/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-hsw: [PASS][16] -> [FAIL][17] ([i915#2370])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_frontbuffer_tracking@fbc-farfromfence:
- shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
* igt@kms_frontbuffer_tracking@fbcpsr-badstride:
- shard-tglb: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-badstride.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-badstride.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109441]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@perf@oa-formats:
- shard-iclb: [PASS][24] -> [SKIP][25] ([i915#1354]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb5/igt@perf@oa-formats.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-iclb6/igt@perf@oa-formats.html
- shard-glk: [PASS][26] -> [SKIP][27] ([fdo#109271] / [i915#1354]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk9/igt@perf@oa-formats.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-glk1/igt@perf@oa-formats.html
- shard-apl: [PASS][28] -> [SKIP][29] ([fdo#109271] / [i915#1354] / [i915#1635]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl4/igt@perf@oa-formats.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-apl7/igt@perf@oa-formats.html
- shard-kbl: [PASS][30] -> [SKIP][31] ([fdo#109271] / [i915#1354]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl4/igt@perf@oa-formats.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-kbl7/igt@perf@oa-formats.html
- shard-tglb: [PASS][32] -> [SKIP][33] ([i915#1354])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb1/igt@perf@oa-formats.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-tglb6/igt@perf@oa-formats.html
#### Possible fixes ####
* igt@gem_exec_create@madvise:
- shard-glk: [DMESG-WARN][34] ([i915#118] / [i915#95]) -> [PASS][35] +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk5/igt@gem_exec_create@madvise.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-glk1/igt@gem_exec_create@madvise.html
* igt@gem_exec_fence@long-history:
- shard-kbl: [INCOMPLETE][36] ([CI#80]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl7/igt@gem_exec_fence@long-history.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-kbl6/igt@gem_exec_fence@long-history.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [FAIL][38] ([i915#1635] / [i915#2389]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl3/igt@gem_exec_reloc@basic-many-active@rcs0.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-apl7/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][40] ([i915#454]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][42] ([i915#2521]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl4/igt@kms_async_flips@async-flip-with-page-flip-events.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-kbl4/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge:
- shard-glk: [DMESG-WARN][44] ([i915#1982]) -> [PASS][45] +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-glk3/igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge.html
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-apl: [DMESG-WARN][46] ([i915#1635] / [i915#1982]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl2/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-apl2/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [INCOMPLETE][48] ([i915#2055]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw6/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: [FAIL][50] ([i915#49]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
- shard-tglb: [DMESG-WARN][52] ([i915#1982]) -> [PASS][53] +4 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [SKIP][54] ([fdo#109441]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb4/igt@kms_psr@psr2_sprite_plane_onoff.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
#### Warnings ####
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [TIMEOUT][56] ([i915#1319] / [i915#1635]) -> [FAIL][57] ([fdo#110321] / [fdo#110336] / [i915#1635]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl7/igt@kms_content_protection@atomic-dpms.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-apl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-apl: [FAIL][58] ([fdo#110321] / [i915#1635]) -> [TIMEOUT][59] ([i915#1319] / [i915#1635])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl1/igt@kms_content_protection@lic.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-apl2/igt@kms_content_protection@lic.html
* igt@perf@mi-rpc:
- shard-tglb: [SKIP][60] ([fdo#109289]) -> [SKIP][61] ([i915#1354])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb2/igt@perf@mi-rpc.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/shard-tglb6/igt@perf@mi-rpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5823 -> IGTPW_5092
CI-20190529: 20190529
CI_DRM_9190: a3d535579dd93942862b867b4452ba11e4f6bbb1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5092: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
IGT_5823: 7dd2fe99bd9dde00456cc5abf7e5ef0c8d7d6118 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
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^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Introduce IGT allocator (rev3)
2020-10-23 15:29 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-26 5:30 ` Zbigniew Kempczyński
0 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-26 5:30 UTC (permalink / raw)
To: igt-dev
On Fri, Oct 23, 2020 at 03:29:49PM +0000, Patchwork wrote:
> Patch Details
>
> Series: Introduce IGT allocator (rev3)
> URL: https://patchwork.freedesktop.org/series/82954/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
>
> CI Bug Log - changes from IGT_5823_full -> IGTPW_5092_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_5092_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_5092_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> IGTPW_5092_full:
>
> IGT changes
>
> Possible regressions
>
> * igt@gem_ctx_isolation@preservation-s3@vcs0:
>
> * shard-glk: PASS -> INCOMPLETE
> * igt@gem_exec_reloc@basic-write-cpu-noreloc:
I didn't touch this test. I rerun the series to check is this
was incidental, but:
Starting subtest: basic-write-cpu-noreloc
(gem_exec_reloc:1496) CRITICAL: Test assertion failure function basic_reloc, file ../tests/i915/gem_exec_reloc.c:639:
(gem_exec_reloc:1496) CRITICAL: Failed assertion: reloc.presumed_offset == offset
(gem_exec_reloc:1496) CRITICAL: error: 0x7fff0000 != 0
Subtest basic-write-cpu-noreloc failed.
looks it should be likely reproducible on that gen all the time.
--
Zbigniew
>
> * shard-snb: PASS -> FAIL +1 similar issue
> * igt@gem_userptr_blits@coherency-unsync:
>
> * shard-hsw: PASS -> INCOMPLETE
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@core_hotunplug@hotrebind}:
> * shard-hsw: NOTRUN -> WARN
>
> New tests
>
> New tests have been introduced between IGT_5823_full and IGTPW_5092_full:
>
> New IGT tests (32)
>
> * igt@api_intel_allocator@alloc-simple:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@fork-simple-once:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.01, 0.04] s
> * igt@api_intel_allocator@fork-simple-stress:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.40, 5.60] s
> * igt@api_intel_allocator@fork-simple-stress-signal:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.41, 5.50] s
> * igt@api_intel_allocator@print:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@purge-bb:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0, 0.00] s
> * igt@api_intel_allocator@random-allocator:
>
> * Statuses :
> * Exec time: [None] s
> * igt@api_intel_allocator@random-allocator@basic:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0, 0.00] s
> * igt@api_intel_allocator@random-allocator@parallel-one:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_allocator@reopen:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_allocator@reopen-fork:
>
> * Statuses : 7 pass(s)
> * Exec time: [3.23, 3.26] s
> * igt@api_intel_allocator@reserve:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@reserve-simple:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@reuse:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@simple-allocator:
>
> * Statuses :
> * Exec time: [None] s
> * igt@api_intel_allocator@simple-allocator@basic:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00] s
> * igt@api_intel_allocator@simple-allocator@parallel-one:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.10, 0.21] s
> * igt@api_intel_allocator@simple-allocator@reserve:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@simple-allocator@reuse:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@two-level-inception:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.40, 5.61] s
> * igt@api_intel_allocator@two-level-inception-interruptible:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.41, 5.60] s
> * igt@api_intel_bb@add-remove-objects:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_bb@blit-noreloc-keep-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@blit-noreloc-purge-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@destroy-bb:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.01, 0.02] s
> * igt@api_intel_bb@object-noreloc-keep-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-noreloc-keep-cache-simple:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-noreloc-purge-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-noreloc-purge-cache-simple:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-reloc-keep-cache:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_bb@object-reloc-purge-cache:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_bb@reset-bb:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0, 0.00] s
>
> Known issues
>
> Here are the changes found in IGTPW_5092_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@api_intel_bb@blit-noreloc-keep-cache:
>
> * shard-hsw: PASS -> SKIP (fdo#109271) +3 similar issues
>
> * shard-snb: PASS -> SKIP (fdo#109271) +1 similar issue
>
> * igt@core_hotunplug@hotrebind-lateclose:
>
> * shard-iclb: PASS -> DMESG-WARN (i915#1982)
> * igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge:
>
> * shard-apl: PASS -> DMESG-WARN (i915#1635 / i915#1982) +1 similar
> issue
> * igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
>
> * shard-hsw: PASS -> FAIL (i915#2370)
> * igt@kms_frontbuffer_tracking@fbc-farfromfence:
>
> * shard-kbl: PASS -> DMESG-WARN (i915#1982) +2 similar issues
> * igt@kms_frontbuffer_tracking@fbcpsr-badstride:
>
> * shard-tglb: PASS -> DMESG-WARN (i915#1982) +2 similar issues
> * igt@kms_psr@psr2_cursor_render:
>
> * shard-iclb: PASS -> SKIP (fdo#109441) +1 similar issue
> * igt@perf@oa-formats:
>
> * shard-iclb: PASS -> SKIP (i915#1354) +1 similar issue
>
> * shard-glk: PASS -> SKIP (fdo#109271 / i915#1354) +1 similar issue
>
> * shard-apl: PASS -> SKIP (fdo#109271 / i915#1354 / i915#1635) +1
> similar issue
>
> * shard-kbl: PASS -> SKIP (fdo#109271 / i915#1354) +1 similar issue
>
> * shard-tglb: PASS -> SKIP (i915#1354)
>
> Possible fixes
>
> * igt@gem_exec_create@madvise:
>
> * shard-glk: DMESG-WARN (i915#118 / i915#95) -> PASS +1 similar
> issue
> * igt@gem_exec_fence@long-history:
>
> * shard-kbl: INCOMPLETE (CI#80) -> PASS
> * igt@gem_exec_reloc@basic-many-active@rcs0:
>
> * shard-apl: FAIL (i915#1635 / i915#2389) -> PASS
> * igt@i915_pm_dc@dc6-psr:
>
> * shard-iclb: FAIL (i915#454) -> PASS
> * {igt@kms_async_flips@async-flip-with-page-flip-events}:
>
> * shard-kbl: FAIL (i915#2521) -> PASS
> * igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge:
>
> * shard-glk: DMESG-WARN (i915#1982) -> PASS +1 similar issue
> * igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
>
> * shard-apl: DMESG-WARN (i915#1635 / i915#1982) -> PASS
> * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
>
> * shard-hsw: INCOMPLETE (i915#2055) -> PASS
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
>
> * shard-glk: FAIL (i915#49) -> PASS
> * igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
>
> * shard-tglb: DMESG-WARN (i915#1982) -> PASS +4 similar issues
> * igt@kms_psr@psr2_sprite_plane_onoff:
>
> * shard-iclb: SKIP (fdo#109441) -> PASS
>
> Warnings
>
> * igt@kms_content_protection@atomic-dpms:
>
> * shard-apl: TIMEOUT (i915#1319 / i915#1635) -> FAIL (fdo#110321 /
> fdo#110336 / i915#1635) +1 similar issue
> * igt@kms_content_protection@lic:
>
> * shard-apl: FAIL (fdo#110321 / i915#1635) -> TIMEOUT (i915#1319 /
> i915#1635)
> * igt@perf@mi-rpc:
>
> * shard-tglb: SKIP (fdo#109289) -> SKIP (i915#1354)
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> Participating hosts (8 -> 8)
>
> No changes in participating hosts
>
> Build changes
>
> * CI: CI-20190529 -> None
> * IGT: IGT_5823 -> IGTPW_5092
>
> CI-20190529: 20190529
> CI_DRM_9190: a3d535579dd93942862b867b4452ba11e4f6bbb1 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_5092: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5092/index.html
> IGT_5823: 7dd2fe99bd9dde00456cc5abf7e5ef0c8d7d6118 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Introduce IGT allocator (rev4)
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (24 preceding siblings ...)
2020-10-23 15:29 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-26 5:43 ` Patchwork
2020-10-26 6:44 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
26 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2020-10-26 5:43 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 4927 bytes --]
== Series Details ==
Series: Introduce IGT allocator (rev4)
URL : https://patchwork.freedesktop.org/series/82954/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9193 -> IGTPW_5096
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/index.html
Known issues
------------
Here are the changes found in IGTPW_5096 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-icl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([i915#2203])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [INCOMPLETE][9] ([i915#1635]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/fi-apl-guc/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/fi-apl-guc/igt@gem_ctx_create@basic-files.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][13] ([i915#2203]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/fi-skl-guc/igt@vgem_basic@unload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/fi-skl-guc/igt@vgem_basic@unload.html
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
Participating hosts (46 -> 39)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5825 -> IGTPW_5096
CI-20190529: 20190529
CI_DRM_9193: 92d57a5d951e06303a37f344f179d010753db622 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5096: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/index.html
IGT_5825: e3503f6542fef432413e78e38436e13cca76bf8c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@api_intel_allocator@alloc-simple
+igt@api_intel_allocator@fork-simple-once
+igt@api_intel_allocator@fork-simple-stress
+igt@api_intel_allocator@fork-simple-stress-signal
+igt@api_intel_allocator@print
+igt@api_intel_allocator@purge-bb
+igt@api_intel_allocator@random-allocator
+igt@api_intel_allocator@reopen
+igt@api_intel_allocator@reopen-fork
+igt@api_intel_allocator@reserve
+igt@api_intel_allocator@reserve-simple
+igt@api_intel_allocator@reuse
+igt@api_intel_allocator@simple-allocator
+igt@api_intel_allocator@two-level-inception
+igt@api_intel_allocator@two-level-inception-interruptible
+igt@api_intel_bb@add-remove-objects
+igt@api_intel_bb@blit-noreloc-keep-cache-random
+igt@api_intel_bb@blit-noreloc-purge-cache-random
+igt@api_intel_bb@destroy-bb
+igt@api_intel_bb@object-noreloc-keep-cache-random
+igt@api_intel_bb@object-noreloc-keep-cache-simple
+igt@api_intel_bb@object-noreloc-purge-cache-random
+igt@api_intel_bb@object-noreloc-purge-cache-simple
+igt@api_intel_bb@object-reloc-keep-cache
+igt@api_intel_bb@object-reloc-purge-cache
+igt@api_intel_bb@reset-bb
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/index.html
[-- Attachment #1.2: Type: text/html, Size: 6116 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread* [igt-dev] ✗ Fi.CI.IGT: failure for Introduce IGT allocator (rev4)
2020-10-23 12:41 [igt-dev] [PATCH i-g-t v3 00/23] Introduce IGT allocator Zbigniew Kempczyński
` (25 preceding siblings ...)
2020-10-26 5:43 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce IGT allocator (rev4) Patchwork
@ 2020-10-26 6:44 ` Patchwork
2020-10-26 8:09 ` Zbigniew Kempczyński
26 siblings, 1 reply; 30+ messages in thread
From: Patchwork @ 2020-10-26 6:44 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 30246 bytes --]
== Series Details ==
Series: Introduce IGT allocator (rev4)
URL : https://patchwork.freedesktop.org/series/82954/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9193_full -> IGTPW_5096_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5096_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5096_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5096_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_parallel@fds@vecs0:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb3/igt@gem_exec_parallel@fds@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb5/igt@gem_exec_parallel@fds@vecs0.html
* igt@gem_pipe_control_store_loop@fresh-buffer:
- shard-snb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-snb7/igt@gem_pipe_control_store_loop@fresh-buffer.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-snb4/igt@gem_pipe_control_store_loop@fresh-buffer.html
* igt@kms_cursor_legacy@all-pipes-forked-bo:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb7/igt@kms_cursor_legacy@all-pipes-forked-bo.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb3/igt@kms_cursor_legacy@all-pipes-forked-bo.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
New tests
---------
New tests have been introduced between CI_DRM_9193_full and IGTPW_5096_full:
### New IGT tests (32) ###
* igt@api_intel_allocator@alloc-simple:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@fork-simple-once:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.04] s
* igt@api_intel_allocator@fork-simple-stress:
- Statuses : 7 pass(s)
- Exec time: [5.40, 5.50] s
* igt@api_intel_allocator@fork-simple-stress-signal:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.54] s
* igt@api_intel_allocator@print:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@purge-bb:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@api_intel_allocator@random-allocator:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@random-allocator@basic:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@api_intel_allocator@random-allocator@parallel-one:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_allocator@reopen:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_allocator@reopen-fork:
- Statuses : 7 pass(s)
- Exec time: [3.23, 3.27] s
* igt@api_intel_allocator@reserve:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@reserve-simple:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@reuse:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@api_intel_allocator@simple-allocator:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@simple-allocator@basic:
- Statuses : 7 pass(s)
- Exec time: [0.00] s
* igt@api_intel_allocator@simple-allocator@parallel-one:
- Statuses : 7 pass(s)
- Exec time: [0.10, 0.22] s
* igt@api_intel_allocator@simple-allocator@reserve:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@simple-allocator@reuse:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@api_intel_allocator@two-level-inception:
- Statuses : 7 pass(s)
- Exec time: [5.40, 5.61] s
* igt@api_intel_allocator@two-level-inception-interruptible:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.62] s
* igt@api_intel_bb@add-remove-objects:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@blit-noreloc-keep-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@blit-noreloc-purge-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@destroy-bb:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.02] s
* igt@api_intel_bb@object-noreloc-keep-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-noreloc-keep-cache-simple:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-noreloc-purge-cache-random:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-noreloc-purge-cache-simple:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.01] s
* igt@api_intel_bb@object-reloc-keep-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@object-reloc-purge-cache:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@api_intel_bb@reset-bb:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
Known issues
------------
Here are the changes found in IGTPW_5096_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-noreloc-keep-cache:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-hsw1/igt@api_intel_bb@blit-noreloc-keep-cache.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-hsw4/igt@api_intel_bb@blit-noreloc-keep-cache.html
- shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-snb7/igt@api_intel_bb@blit-noreloc-keep-cache.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-snb4/igt@api_intel_bb@blit-noreloc-keep-cache.html
* igt@core_hotunplug@unbind-rebind:
- shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb4/igt@core_hotunplug@unbind-rebind.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb1/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_whisper@basic-fds-all:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118] / [i915#95]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk1/igt@gem_exec_whisper@basic-fds-all.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk4/igt@gem_exec_whisper@basic-fds-all.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([i915#155] / [i915#636])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl7/igt@i915_suspend@forcewake.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl2/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@linear-8bpp-rotate-180:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl2/igt@kms_big_fb@linear-8bpp-rotate-180.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl4/igt@kms_big_fb@linear-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#1635] / [i915#1982])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl2/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl7/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
- shard-kbl: [PASS][23] -> [FAIL][24] ([i915#54])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#1635] / [i915#54])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#54])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb3/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][31] -> [FAIL][32] ([i915#79])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-kbl: [PASS][33] -> [FAIL][34] ([i915#49])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
- shard-apl: [PASS][35] -> [FAIL][36] ([i915#1635] / [i915#49])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-snb: [PASS][37] -> [FAIL][38] ([i915#2546])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
* igt@kms_prime@basic-crc@first-to-second:
- shard-iclb: [PASS][39] -> [SKIP][40] ([i915#1836])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@kms_prime@basic-crc@first-to-second.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb7/igt@kms_prime@basic-crc@first-to-second.html
- shard-kbl: [PASS][41] -> [SKIP][42] ([fdo#109271]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl2/igt@kms_prime@basic-crc@first-to-second.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl1/igt@kms_prime@basic-crc@first-to-second.html
- shard-tglb: [PASS][43] -> [SKIP][44] ([i915#1836])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb2/igt@kms_prime@basic-crc@first-to-second.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb2/igt@kms_prime@basic-crc@first-to-second.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html
* igt@perf@invalid-open-flags:
- shard-tglb: [PASS][47] -> [SKIP][48] ([i915#405])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb7/igt@perf@invalid-open-flags.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb1/igt@perf@invalid-open-flags.html
- shard-apl: [PASS][49] -> [SKIP][50] ([fdo#109271] / [i915#1635]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl1/igt@perf@invalid-open-flags.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl3/igt@perf@invalid-open-flags.html
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#405])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@perf@invalid-open-flags.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb5/igt@perf@invalid-open-flags.html
- shard-glk: [PASS][53] -> [SKIP][54] ([fdo#109271]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk3/igt@perf@invalid-open-flags.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk7/igt@perf@invalid-open-flags.html
#### Possible fixes ####
* igt@gem_ctx_shared@q-smoketest-all:
- shard-glk: [FAIL][55] ([i915#1888]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk5/igt@gem_ctx_shared@q-smoketest-all.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk5/igt@gem_ctx_shared@q-smoketest-all.html
* {igt@gem_exec_capture@pi@vecs0}:
- shard-iclb: [INCOMPLETE][57] -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@gem_exec_capture@pi@vecs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb7/igt@gem_exec_capture@pi@vecs0.html
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [FAIL][59] ([i915#2389]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk4/igt@gem_exec_reloc@basic-many-active@vecs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk5/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-snb: [INCOMPLETE][61] ([i915#82]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-snb7/igt@gem_exec_whisper@basic-contexts-forked.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-snb7/igt@gem_exec_whisper@basic-contexts-forked.html
- shard-hsw: [FAIL][63] ([i915#1888]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-hsw6/igt@gem_exec_whisper@basic-contexts-forked.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-hsw6/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [DMESG-WARN][65] ([i915#118] / [i915#95]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk1/igt@gem_exec_whisper@basic-queues-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][67] ([i915#2190]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb1/igt@gem_huc_copy@huc-copy.html
* igt@gem_linear_blits@normal:
- shard-snb: [FAIL][69] -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-snb5/igt@gem_linear_blits@normal.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-snb7/igt@gem_linear_blits@normal.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb7/igt@i915_module_load@reload-with-fault-injection.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb5/igt@i915_module_load@reload-with-fault-injection.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-apl: [FAIL][73] ([i915#1635] / [i915#2521]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl6/igt@kms_async_flips@async-flip-with-page-flip-events.html
* {igt@kms_async_flips@test-time-stamp}:
- shard-tglb: [FAIL][75] ([i915#2597]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb8/igt@kms_async_flips@test-time-stamp.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-glk: [FAIL][77] ([i915#1119]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk5/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk3/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_flip@2x-nonexisting-fb-interruptible@ab-vga1-hdmi-a1:
- shard-hsw: [DMESG-WARN][79] ([i915#1982]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-hsw6/igt@kms_flip@2x-nonexisting-fb-interruptible@ab-vga1-hdmi-a1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-hsw1/igt@kms_flip@2x-nonexisting-fb-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-apl: [FAIL][81] ([i915#1635] / [i915#79]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl2/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl8/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][83] ([i915#2598]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [INCOMPLETE][85] ([i915#2055]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-hsw6/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-hsw7/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][87] ([i915#1982]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl4/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl1/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-kbl: [FAIL][89] ([i915#49]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
- shard-glk: [FAIL][91] ([i915#49]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-apl: [FAIL][93] ([i915#1635] / [i915#49]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
- shard-iclb: [DMESG-WARN][95] ([i915#1982]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
* igt@kms_prime@basic-crc@second-to-first:
- shard-apl: [SKIP][97] ([fdo#109271] / [i915#1635]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl7/igt@kms_prime@basic-crc@second-to-first.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl1/igt@kms_prime@basic-crc@second-to-first.html
- shard-kbl: [SKIP][99] ([fdo#109271]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl2/igt@kms_prime@basic-crc@second-to-first.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl1/igt@kms_prime@basic-crc@second-to-first.html
- shard-iclb: [SKIP][101] ([i915#1836]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@kms_prime@basic-crc@second-to-first.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb7/igt@kms_prime@basic-crc@second-to-first.html
- shard-tglb: [SKIP][103] ([i915#1836]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb2/igt@kms_prime@basic-crc@second-to-first.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb2/igt@kms_prime@basic-crc@second-to-first.html
- shard-glk: [SKIP][105] ([fdo#109271]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk2/igt@kms_prime@basic-crc@second-to-first.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk1/igt@kms_prime@basic-crc@second-to-first.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][107] ([fdo#109642] / [fdo#111068]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][109] ([fdo#109441]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb5/igt@kms_psr@psr2_sprite_render.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
* igt@kms_vblank@pipe-c-wait-idle:
- shard-apl: [DMESG-WARN][111] ([i915#1635] / [i915#1982]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl6/igt@kms_vblank@pipe-c-wait-idle.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl7/igt@kms_vblank@pipe-c-wait-idle.html
* igt@perf@gen12-oa-tlb-invalidate:
- shard-tglb: [SKIP][113] ([i915#1354]) -> [PASS][114] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-tglb2/igt@perf@gen12-oa-tlb-invalidate.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-tglb1/igt@perf@gen12-oa-tlb-invalidate.html
* igt@perf@non-system-wide-paranoid:
- shard-apl: [SKIP][115] ([fdo#109271] / [i915#1354] / [i915#1635]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl3/igt@perf@non-system-wide-paranoid.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl7/igt@perf@non-system-wide-paranoid.html
- shard-glk: [SKIP][117] ([fdo#109271] / [i915#1354]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk5/igt@perf@non-system-wide-paranoid.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk5/igt@perf@non-system-wide-paranoid.html
- shard-hsw: [SKIP][119] ([fdo#109271]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-hsw6/igt@perf@non-system-wide-paranoid.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-hsw2/igt@perf@non-system-wide-paranoid.html
- shard-iclb: [SKIP][121] ([i915#1354]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@perf@non-system-wide-paranoid.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb8/igt@perf@non-system-wide-paranoid.html
- shard-kbl: [SKIP][123] ([fdo#109271] / [i915#1354]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl1/igt@perf@non-system-wide-paranoid.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl2/igt@perf@non-system-wide-paranoid.html
#### Warnings ####
* igt@kms_content_protection@lic:
- shard-apl: [FAIL][125] ([fdo#110321] / [i915#1635]) -> [TIMEOUT][126] ([i915#1319] / [i915#1635])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl7/igt@kms_content_protection@lic.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl1/igt@kms_content_protection@lic.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][127] ([i915#1226]) -> [SKIP][128] ([fdo#109349])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: [FAIL][129] ([fdo#108145] / [i915#1635] / [i915#265]) -> [DMESG-FAIL][130] ([fdo#108145] / [i915#1635] / [i915#1982])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: [DMESG-FAIL][131] ([fdo#108145] / [i915#1635] / [i915#1982]) -> [FAIL][132] ([fdo#108145] / [i915#1635] / [i915#265])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@perf@gen12-oa-tlb-invalidate:
- shard-kbl: [SKIP][133] ([fdo#109271] / [i915#1354]) -> [SKIP][134] ([fdo#109271])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-kbl2/igt@perf@gen12-oa-tlb-invalidate.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-kbl1/igt@perf@gen12-oa-tlb-invalidate.html
- shard-glk: [SKIP][135] ([fdo#109271] / [i915#1354]) -> [SKIP][136] ([fdo#109271])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-glk2/igt@perf@gen12-oa-tlb-invalidate.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-glk2/igt@perf@gen12-oa-tlb-invalidate.html
- shard-apl: [SKIP][137] ([fdo#109271] / [i915#1354] / [i915#1635]) -> [SKIP][138] ([fdo#109271] / [i915#1635])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-apl7/igt@perf@gen12-oa-tlb-invalidate.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-apl3/igt@perf@gen12-oa-tlb-invalidate.html
- shard-iclb: [SKIP][139] ([i915#1354]) -> [SKIP][140] ([fdo#109289])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9193/shard-iclb2/igt@perf@gen12-oa-tlb-invalidate.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/shard-iclb6/igt@perf@gen12-oa-tlb-invalidate.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/index.html
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Introduce IGT allocator (rev4)
2020-10-26 6:44 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-26 8:09 ` Zbigniew Kempczyński
0 siblings, 0 replies; 30+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-26 8:09 UTC (permalink / raw)
To: igt-dev
On Mon, Oct 26, 2020 at 06:44:51AM +0000, Patchwork wrote:
> Patch Details
>
> Series: Introduce IGT allocator (rev4)
> URL: https://patchwork.freedesktop.org/series/82954/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/index.html
>
> CI Bug Log - changes from CI_DRM_9193_full -> IGTPW_5096_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_5096_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_5096_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5096/index.html
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> IGTPW_5096_full:
>
> IGT changes
>
> Possible regressions
>
> * igt@gem_exec_parallel@fds@vecs0:
>
> * shard-iclb: PASS -> INCOMPLETE
I didn't touch the test.
> * igt@gem_pipe_control_store_loop@fresh-buffer:
>
> * shard-snb: PASS -> FAIL
I didn't touch the test.
> * igt@kms_cursor_legacy@all-pipes-forked-bo:
It seems there's some limits constraints exceeded:
Starting subtest: all-pipes-forked-bo
runner: This test was killed due to exceeding disk usage limit. (Used 10492255 bytes, limit 10485760)
>
> * shard-tglb: PASS -> INCOMPLETE
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
>
> * shard-tglb: PASS -> FAIL
(kms_flip:1498) CRITICAL: Test assertion failure function run_test_step, file ../tests/kms_flip.c:721:
(kms_flip:1498) CRITICAL: Failed assertion: timercmp(&reply.ts, &o->flip_state.last_ts, ==)
(kms_flip:1498) CRITICAL: Last errno: 4, Interrupted system call
Dynamic subtest A-eDP1 failed.
Also series is not involved in above error.
--
Zbigniew
>
> New tests
>
> New tests have been introduced between CI_DRM_9193_full and
> IGTPW_5096_full:
>
> New IGT tests (32)
>
> * igt@api_intel_allocator@alloc-simple:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@fork-simple-once:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.01, 0.04] s
> * igt@api_intel_allocator@fork-simple-stress:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.40, 5.50] s
> * igt@api_intel_allocator@fork-simple-stress-signal:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.41, 5.54] s
> * igt@api_intel_allocator@print:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@purge-bb:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0, 0.00] s
> * igt@api_intel_allocator@random-allocator:
>
> * Statuses :
> * Exec time: [None] s
> * igt@api_intel_allocator@random-allocator@basic:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0, 0.00] s
> * igt@api_intel_allocator@random-allocator@parallel-one:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_allocator@reopen:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_allocator@reopen-fork:
>
> * Statuses : 7 pass(s)
> * Exec time: [3.23, 3.27] s
> * igt@api_intel_allocator@reserve:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@reserve-simple:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@reuse:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0, 0.00] s
> * igt@api_intel_allocator@simple-allocator:
>
> * Statuses :
> * Exec time: [None] s
> * igt@api_intel_allocator@simple-allocator@basic:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00] s
> * igt@api_intel_allocator@simple-allocator@parallel-one:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.10, 0.22] s
> * igt@api_intel_allocator@simple-allocator@reserve:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@simple-allocator@reuse:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0] s
> * igt@api_intel_allocator@two-level-inception:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.40, 5.61] s
> * igt@api_intel_allocator@two-level-inception-interruptible:
>
> * Statuses : 7 pass(s)
> * Exec time: [5.41, 5.62] s
> * igt@api_intel_bb@add-remove-objects:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_bb@blit-noreloc-keep-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@blit-noreloc-purge-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@destroy-bb:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.01, 0.02] s
> * igt@api_intel_bb@object-noreloc-keep-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-noreloc-keep-cache-simple:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-noreloc-purge-cache-random:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-noreloc-purge-cache-simple:
>
> * Statuses : 5 pass(s) 2 skip(s)
> * Exec time: [0.0, 0.01] s
> * igt@api_intel_bb@object-reloc-keep-cache:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_bb@object-reloc-purge-cache:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.00, 0.01] s
> * igt@api_intel_bb@reset-bb:
>
> * Statuses : 7 pass(s)
> * Exec time: [0.0, 0.00] s
>
> Known issues
>
> Here are the changes found in IGTPW_5096_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@api_intel_bb@blit-noreloc-keep-cache:
>
> * shard-hsw: PASS -> SKIP (fdo#109271) +2 similar issues
>
> * shard-snb: PASS -> SKIP (fdo#109271) +1 similar issue
>
> * igt@core_hotunplug@unbind-rebind:
>
> * shard-iclb: PASS -> DMESG-WARN ([i915#1982])
> * igt@gem_exec_whisper@basic-fds-all:
>
> * shard-glk: PASS -> DMESG-WARN (i915#118 / [i915#95]) +2 similar
> issues
> * igt@i915_suspend@forcewake:
>
> * shard-kbl: PASS -> INCOMPLETE ([i915#155] / [i915#636])
> * igt@kms_big_fb@linear-8bpp-rotate-180:
>
> * shard-kbl: PASS -> DMESG-WARN ([i915#1982]) +2 similar issues
> * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
>
> * shard-apl: PASS -> DMESG-WARN ([i915#1635] / [i915#1982])
> * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
>
> * shard-kbl: PASS -> FAIL ([i915#54])
>
> * shard-apl: PASS -> FAIL ([i915#1635] / [i915#54])
>
> * shard-glk: PASS -> FAIL ([i915#54])
>
> * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
>
> * shard-tglb: PASS -> DMESG-WARN ([i915#1982]) +3 similar issues
> * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
>
> * shard-glk: PASS -> FAIL ([i915#79])
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
>
> * shard-kbl: PASS -> FAIL ([i915#49])
>
> * shard-apl: PASS -> FAIL ([i915#1635] / [i915#49])
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
>
> * shard-snb: PASS -> FAIL ([i915#2546])
> * igt@kms_prime@basic-crc@first-to-second:
>
> * shard-iclb: PASS -> SKIP ([i915#1836])
>
> * shard-kbl: PASS -> SKIP (fdo#109271) +1 similar issue
>
> * shard-tglb: PASS -> SKIP ([i915#1836])
>
> * igt@kms_psr@psr2_cursor_plane_move:
>
> * shard-iclb: PASS -> SKIP (fdo#109441) +3 similar issues
> * igt@perf@invalid-open-flags:
>
> * shard-tglb: PASS -> SKIP ([i915#405])
>
> * shard-apl: PASS -> SKIP (fdo#109271 / [i915#1635]) +1 similar
> issue
>
> * shard-iclb: PASS -> SKIP ([i915#405])
>
> * shard-glk: PASS -> SKIP (fdo#109271) +1 similar issue
>
> Possible fixes
>
> * igt@gem_ctx_shared@q-smoketest-all:
>
> * shard-glk: FAIL ([i915#1888]) -> PASS
> * {igt@gem_exec_capture@pi@vecs0}:
>
> * shard-iclb: INCOMPLETE -> PASS
> * igt@gem_exec_reloc@basic-many-active@vecs0:
>
> * shard-glk: FAIL ([i915#2389]) -> PASS +2 similar issues
> * igt@gem_exec_whisper@basic-contexts-forked:
>
> * shard-snb: INCOMPLETE ([i915#82]) -> PASS
>
> * shard-hsw: FAIL ([i915#1888]) -> PASS +1 similar issue
>
> * igt@gem_exec_whisper@basic-queues-all:
>
> * shard-glk: DMESG-WARN (i915#118 / [i915#95]) -> PASS +1 similar
> issue
> * igt@gem_huc_copy@huc-copy:
>
> * shard-tglb: SKIP ([i915#2190]) -> PASS
> * igt@gem_linear_blits@normal:
>
> * shard-snb: FAIL -> PASS
> * igt@i915_module_load@reload-with-fault-injection:
>
> * shard-tglb: DMESG-WARN ([i915#1982]) -> PASS +3 similar issues
> * {igt@kms_async_flips@async-flip-with-page-flip-events}:
>
> * shard-apl: FAIL ([i915#1635] / [i915#2521]) -> PASS
> * {igt@kms_async_flips@test-time-stamp}:
>
> * shard-tglb: FAIL ([i915#2597]) -> PASS
> * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
>
> * shard-glk: FAIL (i915#1119) -> PASS
> * igt@kms_flip@2x-nonexisting-fb-interruptible@ab-vga1-hdmi-a1:
>
> * shard-hsw: DMESG-WARN ([i915#1982]) -> PASS +1 similar issue
> * igt@kms_flip@flip-vs-expired-vblank@a-dp1:
>
> * shard-apl: FAIL ([i915#1635] / [i915#79]) -> PASS
> * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
>
> * shard-tglb: FAIL ([i915#2598]) -> PASS
> * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
>
> * shard-hsw: INCOMPLETE ([i915#2055]) -> PASS
> * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1:
>
> * shard-kbl: DMESG-WARN ([i915#1982]) -> PASS
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
>
> * shard-kbl: FAIL ([i915#49]) -> PASS +1 similar issue
>
> * shard-glk: FAIL ([i915#49]) -> PASS
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
>
> * shard-apl: FAIL ([i915#1635] / [i915#49]) -> PASS +1 similar
> issue
> * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
>
> * shard-iclb: DMESG-WARN ([i915#1982]) -> PASS
> * igt@kms_prime@basic-crc@second-to-first:
>
> * shard-apl: SKIP (fdo#109271 / [i915#1635]) -> PASS
>
> * shard-kbl: SKIP (fdo#109271) -> PASS
>
> * shard-iclb: SKIP ([i915#1836]) -> PASS
>
> * shard-tglb: SKIP ([i915#1836]) -> PASS
>
> * shard-glk: SKIP (fdo#109271) -> PASS
>
> * igt@kms_psr2_su@frontbuffer:
>
> * shard-iclb: SKIP (fdo#109642 / fdo#111068) -> PASS
> * igt@kms_psr@psr2_sprite_render:
>
> * shard-iclb: SKIP (fdo#109441) -> PASS
> * igt@kms_vblank@pipe-c-wait-idle:
>
> * shard-apl: DMESG-WARN ([i915#1635] / [i915#1982]) -> PASS
> * igt@perf@gen12-oa-tlb-invalidate:
>
> * shard-tglb: SKIP (i915#1354) -> PASS +1 similar issue
> * igt@perf@non-system-wide-paranoid:
>
> * shard-apl: SKIP (fdo#109271 / i915#1354 / [i915#1635]) -> PASS
>
> * shard-glk: SKIP (fdo#109271 / i915#1354) -> PASS
>
> * shard-hsw: SKIP (fdo#109271) -> PASS
>
> * shard-iclb: SKIP (i915#1354) -> PASS
>
> * shard-kbl: SKIP (fdo#109271 / i915#1354) -> PASS
>
> Warnings
>
> * igt@kms_content_protection@lic:
>
> * shard-apl: FAIL (fdo#110321 / [i915#1635]) -> TIMEOUT (i915#1319
> / [i915#1635])
> * igt@kms_dp_dsc@basic-dsc-enable-edp:
>
> * shard-iclb: DMESG-WARN (i915#1226) -> SKIP (fdo#109349)
> * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
>
> * shard-apl: FAIL (fdo#108145 / [i915#1635] / [i915#265]) ->
> DMESG-FAIL (fdo#108145 / [i915#1635] / [i915#1982])
> * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
>
> * shard-apl: DMESG-FAIL (fdo#108145 / [i915#1635] / [i915#1982]) ->
> FAIL (fdo#108145 / [i915#1635] / [i915#265])
> * igt@perf@gen12-oa-tlb-invalidate:
>
> * shard-kbl: SKIP (fdo#109271 / i915#1354) -> SKIP (fdo#109271)
>
> * shard-glk: SKIP (fdo#109271 / i915#1354) -> SKIP (fdo#109271)
>
> * shard-apl: SKIP (fdo#109271 / i915#1354 / [i915#1635]) -> SKIP
> (fdo#109271 / [i915#1635])
>
> * shard-iclb: SKIP (i915#1354) -> SKIP (fdo#109289)
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
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