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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Huacai Chen" <chenhc@lemote.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	kvm@vger.kernel.org,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 5/9] target/mips: Remove now unused ASE_MSA definition
Date: Wed,  2 Dec 2020 19:44:11 +0100	[thread overview]
Message-ID: <20201202184415.1434484-6-f4bug@amsat.org> (raw)
In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org>

We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/mips-defs.h          | 1 -
 target/mips/translate_init.c.inc | 8 ++++----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ed6a7a9e545..805034b8956 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -45,7 +45,6 @@
 #define ASE_MT            0x0000000040000000ULL
 #define ASE_SMARTMIPS     0x0000000080000000ULL
 #define ASE_MICROMIPS     0x0000000100000000ULL
-#define ASE_MSA           0x0000000200000000ULL
 /*
  *   bits 40-51: vendor-specific base instruction sets
  */
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 3b069190ed8..2170f8ace6f 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -408,7 +408,7 @@ const mips_def_t mips_defs[] =
         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
         .SEGBITS = 32,
         .PABITS = 40,
-        .insn_flags = CPU_MIPS32R5 | ASE_MSA,
+        .insn_flags = CPU_MIPS32R5,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
@@ -719,7 +719,7 @@ const mips_def_t mips_defs[] =
         .MSAIR = 0x03 << MSAIR_ProcID,
         .SEGBITS = 48,
         .PABITS = 48,
-        .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+        .insn_flags = CPU_MIPS64R6,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
@@ -759,7 +759,7 @@ const mips_def_t mips_defs[] =
         .MSAIR = 0x03 << MSAIR_ProcID,
         .SEGBITS = 48,
         .PABITS = 48,
-        .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+        .insn_flags = CPU_MIPS64R6,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
@@ -885,7 +885,7 @@ const mips_def_t mips_defs[] =
         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
         .SEGBITS = 48,
         .PABITS = 48,
-        .insn_flags = CPU_LOONGSON3A | ASE_MSA,
+        .insn_flags = CPU_LOONGSON3A,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
-- 
2.26.2


WARNING: multiple messages have this Message-ID (diff)
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	kvm@vger.kernel.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Huacai Chen" <chenhc@lemote.com>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 5/9] target/mips: Remove now unused ASE_MSA definition
Date: Wed,  2 Dec 2020 19:44:11 +0100	[thread overview]
Message-ID: <20201202184415.1434484-6-f4bug@amsat.org> (raw)
In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org>

We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/mips-defs.h          | 1 -
 target/mips/translate_init.c.inc | 8 ++++----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ed6a7a9e545..805034b8956 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -45,7 +45,6 @@
 #define ASE_MT            0x0000000040000000ULL
 #define ASE_SMARTMIPS     0x0000000080000000ULL
 #define ASE_MICROMIPS     0x0000000100000000ULL
-#define ASE_MSA           0x0000000200000000ULL
 /*
  *   bits 40-51: vendor-specific base instruction sets
  */
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 3b069190ed8..2170f8ace6f 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -408,7 +408,7 @@ const mips_def_t mips_defs[] =
         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
         .SEGBITS = 32,
         .PABITS = 40,
-        .insn_flags = CPU_MIPS32R5 | ASE_MSA,
+        .insn_flags = CPU_MIPS32R5,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
@@ -719,7 +719,7 @@ const mips_def_t mips_defs[] =
         .MSAIR = 0x03 << MSAIR_ProcID,
         .SEGBITS = 48,
         .PABITS = 48,
-        .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+        .insn_flags = CPU_MIPS64R6,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
@@ -759,7 +759,7 @@ const mips_def_t mips_defs[] =
         .MSAIR = 0x03 << MSAIR_ProcID,
         .SEGBITS = 48,
         .PABITS = 48,
-        .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+        .insn_flags = CPU_MIPS64R6,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
@@ -885,7 +885,7 @@ const mips_def_t mips_defs[] =
         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
         .SEGBITS = 48,
         .PABITS = 48,
-        .insn_flags = CPU_LOONGSON3A | ASE_MSA,
+        .insn_flags = CPU_LOONGSON3A,
         .mmu_type = MMU_TYPE_R4000,
     },
     {
-- 
2.26.2



  parent reply	other threads:[~2020-12-02 18:45 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-02 18:44 [PATCH 0/9] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2020-12-02 18:44 ` Philippe Mathieu-Daudé
2020-12-02 18:44 ` [PATCH 1/9] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:08   ` Richard Henderson
2020-12-03 17:08     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 2/9] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:10   ` Richard Henderson
2020-12-03 17:10     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 3/9] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:10   ` Richard Henderson
2020-12-03 17:10     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 4/9] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:14   ` Richard Henderson
2020-12-03 17:14     ` Richard Henderson
2020-12-02 18:44 ` Philippe Mathieu-Daudé [this message]
2020-12-02 18:44   ` [PATCH 5/9] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2020-12-03 17:15   ` Richard Henderson
2020-12-03 17:15     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 16:28   ` Richard Henderson
2020-12-04 16:28     ` Richard Henderson
2020-12-04 22:40     ` Philippe Mathieu-Daudé
2020-12-04 22:40       ` Philippe Mathieu-Daudé
2020-12-05 12:44       ` Richard Henderson
2020-12-05 12:44         ` Richard Henderson
2020-12-02 18:44 ` [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 16:30   ` Richard Henderson
2020-12-04 16:30     ` Richard Henderson
2020-12-04 17:23     ` Philippe Mathieu-Daudé
2020-12-04 17:23       ` Philippe Mathieu-Daudé
2020-12-04 18:15       ` Richard Henderson
2020-12-04 18:15         ` Richard Henderson
2020-12-02 18:44 ` [PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 16:31   ` Richard Henderson
2020-12-04 16:31     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 17:04   ` Richard Henderson
2020-12-04 17:04     ` Richard Henderson
2020-12-04 22:53     ` Philippe Mathieu-Daudé
2020-12-04 22:53       ` Philippe Mathieu-Daudé
2020-12-05 12:46       ` Richard Henderson
2020-12-05 12:46         ` Richard Henderson
2020-12-03  3:36 ` [PATCH 0/9] target/mips: Simplify MSA TCG logic Jiaxun Yang
2020-12-03  3:36   ` Jiaxun Yang
2020-12-03  3:38 ` Jiaxun Yang
2020-12-03  3:38   ` Jiaxun Yang

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