From: Suzuki K Poulose <suzuki.poulose@arm.com> To: maz@kernel.org, mathieu.poirier@linaro.org Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anshuman.khandual@arm.com, mike.leach@linaro.org, catalin.marinas@arm.com, will@kernel.org, peterz@infradead.org, leo.yan@linaro.org, robh@kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v6 02/20] perf: aux: Add CoreSight PMU buffer formats Date: Mon, 5 Apr 2021 17:42:49 +0100 [thread overview] Message-ID: <20210405164307.1720226-3-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210405164307.1720226-1-suzuki.poulose@arm.com> CoreSight PMU supports aux-buffer for the ETM tracing. The trace generated by the ETM (associated with individual CPUs, like Intel PT) is captured by a separate IP (CoreSight TMC-ETR/ETF until now). The TMC-ETR applies formatting of the raw ETM trace data, as it can collect traces from multiple ETMs, with the TraceID to indicate the source of a given trace packet. Arm Trace Buffer Extension is new "sink" IP, attached to individual CPUs and thus do not provide additional formatting, like TMC-ETR. Additionally, a system could have both TRBE *and* TMC-ETR for the trace collection. e.g, TMC-ETR could be used as a single trace buffer to collect data from multiple ETMs to correlate the traces from different CPUs. It is possible to have a perf session where some events end up collecting the trace in TMC-ETR while the others in TRBE. Thus we need a way to identify the type of the trace for each AUX record. Define the trace formats exported by the CoreSight PMU. We don't define the flags following the "ETM" as this information is available to the user when issuing the session. What is missing is the additional formatting applied by the "sink" which is decided at the runtime and the user may not have a control on. So we define : - CORESIGHT format (indicates the Frame format) - RAW format (indicates the format of the source) The default value is CORESIGHT format for all the records (i,e == 0). Add the RAW format for others that use raw format. Cc: Peter Zijlstra <peterz@infradead.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- include/uapi/linux/perf_event.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index f006eeab6f0e..63971eaef127 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1162,6 +1162,10 @@ enum perf_callchain_context { #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ +/* CoreSight PMU AUX buffer formats */ +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ + #define PERF_FLAG_FD_NO_GROUP (1UL << 0) #define PERF_FLAG_FD_OUTPUT (1UL << 1) #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: maz@kernel.org, mathieu.poirier@linaro.org Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anshuman.khandual@arm.com, mike.leach@linaro.org, catalin.marinas@arm.com, will@kernel.org, peterz@infradead.org, leo.yan@linaro.org, robh@kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v6 02/20] perf: aux: Add CoreSight PMU buffer formats Date: Mon, 5 Apr 2021 17:42:49 +0100 [thread overview] Message-ID: <20210405164307.1720226-3-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210405164307.1720226-1-suzuki.poulose@arm.com> CoreSight PMU supports aux-buffer for the ETM tracing. The trace generated by the ETM (associated with individual CPUs, like Intel PT) is captured by a separate IP (CoreSight TMC-ETR/ETF until now). The TMC-ETR applies formatting of the raw ETM trace data, as it can collect traces from multiple ETMs, with the TraceID to indicate the source of a given trace packet. Arm Trace Buffer Extension is new "sink" IP, attached to individual CPUs and thus do not provide additional formatting, like TMC-ETR. Additionally, a system could have both TRBE *and* TMC-ETR for the trace collection. e.g, TMC-ETR could be used as a single trace buffer to collect data from multiple ETMs to correlate the traces from different CPUs. It is possible to have a perf session where some events end up collecting the trace in TMC-ETR while the others in TRBE. Thus we need a way to identify the type of the trace for each AUX record. Define the trace formats exported by the CoreSight PMU. We don't define the flags following the "ETM" as this information is available to the user when issuing the session. What is missing is the additional formatting applied by the "sink" which is decided at the runtime and the user may not have a control on. So we define : - CORESIGHT format (indicates the Frame format) - RAW format (indicates the format of the source) The default value is CORESIGHT format for all the records (i,e == 0). Add the RAW format for others that use raw format. Cc: Peter Zijlstra <peterz@infradead.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- include/uapi/linux/perf_event.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index f006eeab6f0e..63971eaef127 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1162,6 +1162,10 @@ enum perf_callchain_context { #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ +/* CoreSight PMU AUX buffer formats */ +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ + #define PERF_FLAG_FD_NO_GROUP (1UL << 0) #define PERF_FLAG_FD_OUTPUT (1UL << 1) #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-04-05 16:43 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-05 16:42 [PATCH v6 00/20] coresight: Add support for ETE and TRBE Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 01/20] perf: aux: Add flags for the buffer format Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose [this message] 2021-04-05 16:42 ` [PATCH v6 02/20] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 03/20] arm64: Add support for trace synchronization barrier Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 04/20] arm64: Add TRBE definitions Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 05/20] kvm: arm64: Handle access to TRFCR_EL1 Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 06/20] kvm: arm64: Move SPE availability check to VCPU load Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-08 15:14 ` Alexandru Elisei 2021-04-08 15:14 ` Alexandru Elisei 2021-04-05 16:42 ` [PATCH v6 07/20] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 08/20] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 09/20] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 10/20] coresight: Do not scan for graph if none is present Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 11/20] coresight: etm4x: Add support for PE OS lock Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:42 ` [PATCH v6 12/20] coresight: ete: Add support for ETE sysreg access Suzuki K Poulose 2021-04-05 16:42 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 13/20] coresight: ete: Add support for ETE tracing Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 14/20] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 15/20] coresight: etm-perf: Handle stale output handles Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 16/20] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 17/20] coresight: sink: Add TRBE driver Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 18/20] Documentation: coresight: trbe: Sysfs ABI description Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 19/20] Documentation: trace: Add documentation for TRBE Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose 2021-04-05 16:43 ` [PATCH v6 20/20] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose 2021-04-05 16:43 ` Suzuki K Poulose
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