All of lore.kernel.org
 help / color / mirror / Atom feed
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: maz@kernel.org, mathieu.poirier@linaro.org
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
	mike.leach@linaro.org, catalin.marinas@arm.com, will@kernel.org,
	peterz@infradead.org, leo.yan@linaro.org, robh@kernel.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Will Deacon <will.deacon@arm.com>
Subject: [PATCH v6 03/20] arm64: Add support for trace synchronization barrier
Date: Mon,  5 Apr 2021 17:42:50 +0100	[thread overview]
Message-ID: <20210405164307.1720226-4-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210405164307.1720226-1-suzuki.poulose@arm.com>

tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/include/asm/barrier.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index c3009b0e5239..5a8367a2b868 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -23,6 +23,7 @@
 #define dsb(opt)	asm volatile("dsb " #opt : : : "memory")
 
 #define psb_csync()	asm volatile("hint #17" : : : "memory")
+#define tsb_csync()	asm volatile("hint #18" : : : "memory")
 #define csdb()		asm volatile("hint #20" : : : "memory")
 
 #define spec_bar()	asm volatile(ALTERNATIVE("dsb nsh\nisb\n",		\
-- 
2.24.1


WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: maz@kernel.org, mathieu.poirier@linaro.org
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
	mike.leach@linaro.org, catalin.marinas@arm.com, will@kernel.org,
	peterz@infradead.org, leo.yan@linaro.org, robh@kernel.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Will Deacon <will.deacon@arm.com>
Subject: [PATCH v6 03/20] arm64: Add support for trace synchronization barrier
Date: Mon,  5 Apr 2021 17:42:50 +0100	[thread overview]
Message-ID: <20210405164307.1720226-4-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210405164307.1720226-1-suzuki.poulose@arm.com>

tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/include/asm/barrier.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index c3009b0e5239..5a8367a2b868 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -23,6 +23,7 @@
 #define dsb(opt)	asm volatile("dsb " #opt : : : "memory")
 
 #define psb_csync()	asm volatile("hint #17" : : : "memory")
+#define tsb_csync()	asm volatile("hint #18" : : : "memory")
 #define csdb()		asm volatile("hint #20" : : : "memory")
 
 #define spec_bar()	asm volatile(ALTERNATIVE("dsb nsh\nisb\n",		\
-- 
2.24.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-04-05 16:43 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-05 16:42 [PATCH v6 00/20] coresight: Add support for ETE and TRBE Suzuki K Poulose
2021-04-05 16:42 ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 01/20] perf: aux: Add flags for the buffer format Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 02/20] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` Suzuki K Poulose [this message]
2021-04-05 16:42   ` [PATCH v6 03/20] arm64: Add support for trace synchronization barrier Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 04/20] arm64: Add TRBE definitions Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 05/20] kvm: arm64: Handle access to TRFCR_EL1 Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 06/20] kvm: arm64: Move SPE availability check to VCPU load Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-08 15:14   ` Alexandru Elisei
2021-04-08 15:14     ` Alexandru Elisei
2021-04-05 16:42 ` [PATCH v6 07/20] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 08/20] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 09/20] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 10/20] coresight: Do not scan for graph if none is present Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 11/20] coresight: etm4x: Add support for PE OS lock Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 12/20] coresight: ete: Add support for ETE sysreg access Suzuki K Poulose
2021-04-05 16:42   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 13/20] coresight: ete: Add support for ETE tracing Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 14/20] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 15/20] coresight: etm-perf: Handle stale output handles Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 16/20] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 17/20] coresight: sink: Add TRBE driver Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 18/20] Documentation: coresight: trbe: Sysfs ABI description Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 19/20] Documentation: trace: Add documentation for TRBE Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 20/20] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose
2021-04-05 16:43   ` Suzuki K Poulose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210405164307.1720226-4-suzuki.poulose@arm.com \
    --to=suzuki.poulose@arm.com \
    --cc=anshuman.khandual@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=coresight@lists.linaro.org \
    --cc=leo.yan@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mathieu.poirier@linaro.org \
    --cc=maz@kernel.org \
    --cc=mike.leach@linaro.org \
    --cc=peterz@infradead.org \
    --cc=robh@kernel.org \
    --cc=will.deacon@arm.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.