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From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>, Ley Foon Tan <lftan.linux@gmail.com>,
	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
	Tien Fong Chee <tien.fong.chee@intel.com>,
	Dalon Westergreen <dalon.westergreen@intel.com>,
	Simon Glass <sjg@chromium.org>,
	Yau Wai Gan <yau.wai.gan@intel.com>,
	Siew Chin Lim <elly.siew.chin.lim@intel.com>
Subject: [v3 09/17] arm: socfpga: Add clock manager for Intel N5X device
Date: Sun, 13 Jun 2021 16:48:44 +0800	[thread overview]
Message-ID: <20210613084852.30868-10-elly.siew.chin.lim@intel.com> (raw)
In-Reply-To: <20210613084852.30868-1-elly.siew.chin.lim@intel.com>

Add clock manager for N5X.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 ...k_manager_agilex.c => clock_manager_n5x.c} | 32 +++++++++----------
 .../mach-socfpga/include/mach/clock_manager.h |  2 ++
 .../include/mach/clock_manager_n5x.h          | 12 +++++++
 3 files changed, 29 insertions(+), 17 deletions(-)
 copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c} (64%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h

diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_n5x.c
similarity index 64%
copy from arch/arm/mach-socfpga/clock_manager_agilex.c
copy to arch/arm/mach-socfpga/clock_manager_n5x.c
index e035c09aae..4f098533e7 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -1,19 +1,18 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  *
  */
 
-#include <clk.h>
 #include <common.h>
-#include <dm.h>
-#include <log.h>
-#include <malloc.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/system_manager.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
-#include <dt-bindings/clock/agilex-clock.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-bindings/clock/n5x-clock.h>
+#include <malloc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
 	int ret;
 
 	ret = uclass_get_device_by_driver(UCLASS_CLK,
-					  DM_DRIVER_GET(socfpga_agilex_clk),
+					  DM_DRIVER_GET(socfpga_n5x_clk),
 					  &dev);
 	if (ret)
 		return 0;
@@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id)
 
 	clk_free(&clk);
 
-	if ((rate == (unsigned long)-ENOSYS) ||
-	    (rate == (unsigned long)-ENXIO) ||
+	if ((rate == (unsigned long)-ENXIO) ||
 	    (rate == (unsigned long)-EIO)) {
 		debug("%s id %u: clk_get_rate err: %ld\n",
 		      __func__, id, rate);
@@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id)
 
 unsigned long cm_get_mpu_clk_hz(void)
 {
-	return cm_get_rate_dm(AGILEX_MPU_CLK);
+	return cm_get_rate_dm(N5X_MPU_CLK);
 }
 
 unsigned int cm_get_l4_sys_free_clk_hz(void)
 {
-	return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+	return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
 }
 
 void cm_print_clock_quick_summary(void)
 {
 	printf("MPU       %10d kHz\n",
-	       cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+	       cm_get_rate_dm_khz(N5X_MPU_CLK));
 	printf("L4 Main	    %8d kHz\n",
-	       cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+	       cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
 	printf("L4 sys free %8d kHz\n",
-	       cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+	       cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
 	printf("L4 MP       %8d kHz\n",
-	       cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+	       cm_get_rate_dm_khz(N5X_L4_MP_CLK));
 	printf("L4 SP       %8d kHz\n",
-	       cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+	       cm_get_rate_dm_khz(N5X_L4_SP_CLK));
 	printf("SDMMC       %8d kHz\n",
-	       cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+	       cm_get_rate_dm_khz(N5X_SDMMC_CLK));
 }
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30e..a8cb07a1c4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
 #include <asm/arch/clock_manager_s10.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include <asm/arch/clock_manager_agilex.h>
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include <asm/arch/clock_manager_n5x.h>
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644
index 0000000000..54615ae8f7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */
-- 
2.19.0


  parent reply	other threads:[~2021-06-13  8:51 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-13  8:48 [v3 00/17] Add Intel N5X SoC support Siew Chin Lim
2021-06-13  8:48 ` [v3 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function Siew Chin Lim
2021-06-13  8:48 ` [v3 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h Siew Chin Lim
2021-06-13  8:48 ` [v3 03/17] arm: socfpga: Add base address for Intel N5X device Siew Chin Lim
2021-06-13  8:48 ` [v3 04/17] arm: socfpga: Add handoff data support " Siew Chin Lim
2021-07-08 16:15   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 05/17] drivers: clk: Add clock driver " Siew Chin Lim
2021-07-08 16:17   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 06/17] arm: socfpga: Get clock manager base address " Siew Chin Lim
2021-06-13  8:48 ` [v3 07/17] drivers: clk: Add memory clock driver " Siew Chin Lim
2021-07-08 16:19   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h Siew Chin Lim
2021-06-13  8:48 ` Siew Chin Lim [this message]
2021-06-13  8:48 ` [v3 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c Siew Chin Lim
2021-06-13  8:48 ` [v3 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB Siew Chin Lim
2021-06-13  8:48 ` [v3 12/17] ddr: altera: Add SDRAM driver for Intel N5X device Siew Chin Lim
2021-07-08 17:06   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 13/17] arm: socfpga: Add SPL " Siew Chin Lim
2021-06-13  8:48 ` [v3 14/17] board: intel: Add socdk board support " Siew Chin Lim
2021-06-13  8:48 ` [v3 15/17] arm: dts: Add base dtsi and devkit dts " Siew Chin Lim
2021-07-08 16:32   ` Ley Foon Tan
2021-07-09  1:10     ` Lim, Elly Siew Chin
2021-06-13  8:48 ` [v3 16/17] include: configs: Add Intel N5X device CONFIGs Siew Chin Lim
2021-06-13  8:48 ` [v3 17/17] arm: socfpga: Enable Intel N5X device build Siew Chin Lim

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