All of lore.kernel.org
 help / color / mirror / Atom feed
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>, Ley Foon Tan <lftan.linux@gmail.com>,
	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
	Tien Fong Chee <tien.fong.chee@intel.com>,
	Dalon Westergreen <dalon.westergreen@intel.com>,
	Simon Glass <sjg@chromium.org>,
	Yau Wai Gan <yau.wai.gan@intel.com>,
	Siew Chin Lim <elly.siew.chin.lim@intel.com>
Subject: [v3 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Date: Sun, 13 Jun 2021 16:48:37 +0800	[thread overview]
Message-ID: <20210613084852.30868-3-elly.siew.chin.lim@intel.com> (raw)
In-Reply-To: <20210613084852.30868-1-elly.siew.chin.lim@intel.com>

Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 .../include/mach/{base_addr_s10.h => base_addr_soc64.h}   | 8 ++++----
 include/configs/socfpga_soc64_common.h                    | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)
 rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (89%)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
similarity index 89%
rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index d3eca65e97..f89066d771 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
  */
 
-#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
-#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
 
 #define SOCFPGA_CCU_ADDRESS			0xf7000000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
@@ -44,4 +44,4 @@
 #define GICD_BASE				0xfffc1000
 #define GICC_BASE				0xfffc2000
 
-#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
+#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 5afdb10454..f0b7884ebc 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
 
-#include <asm/arch/base_addr_s10.h>
+#include <asm/arch/base_addr_soc64.h>
 #include <asm/arch/handoff_soc64.h>
 #include <linux/stringify.h>
 
-- 
2.19.0


  parent reply	other threads:[~2021-06-13  8:49 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-13  8:48 [v3 00/17] Add Intel N5X SoC support Siew Chin Lim
2021-06-13  8:48 ` [v3 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function Siew Chin Lim
2021-06-13  8:48 ` Siew Chin Lim [this message]
2021-06-13  8:48 ` [v3 03/17] arm: socfpga: Add base address for Intel N5X device Siew Chin Lim
2021-06-13  8:48 ` [v3 04/17] arm: socfpga: Add handoff data support " Siew Chin Lim
2021-07-08 16:15   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 05/17] drivers: clk: Add clock driver " Siew Chin Lim
2021-07-08 16:17   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 06/17] arm: socfpga: Get clock manager base address " Siew Chin Lim
2021-06-13  8:48 ` [v3 07/17] drivers: clk: Add memory clock driver " Siew Chin Lim
2021-07-08 16:19   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h Siew Chin Lim
2021-06-13  8:48 ` [v3 09/17] arm: socfpga: Add clock manager for Intel N5X device Siew Chin Lim
2021-06-13  8:48 ` [v3 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c Siew Chin Lim
2021-06-13  8:48 ` [v3 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB Siew Chin Lim
2021-06-13  8:48 ` [v3 12/17] ddr: altera: Add SDRAM driver for Intel N5X device Siew Chin Lim
2021-07-08 17:06   ` Ley Foon Tan
2021-06-13  8:48 ` [v3 13/17] arm: socfpga: Add SPL " Siew Chin Lim
2021-06-13  8:48 ` [v3 14/17] board: intel: Add socdk board support " Siew Chin Lim
2021-06-13  8:48 ` [v3 15/17] arm: dts: Add base dtsi and devkit dts " Siew Chin Lim
2021-07-08 16:32   ` Ley Foon Tan
2021-07-09  1:10     ` Lim, Elly Siew Chin
2021-06-13  8:48 ` [v3 16/17] include: configs: Add Intel N5X device CONFIGs Siew Chin Lim
2021-06-13  8:48 ` [v3 17/17] arm: socfpga: Enable Intel N5X device build Siew Chin Lim

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210613084852.30868-3-elly.siew.chin.lim@intel.com \
    --to=elly.siew.chin.lim@intel.com \
    --cc=dalon.westergreen@intel.com \
    --cc=lftan.linux@gmail.com \
    --cc=marex@denx.de \
    --cc=simon.k.r.goldschmidt@gmail.com \
    --cc=sjg@chromium.org \
    --cc=tien.fong.chee@intel.com \
    --cc=u-boot@lists.denx.de \
    --cc=yau.wai.gan@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.