From: Jonathan Cameron <jic23@kernel.org> To: Billy Tsai <billy_tsai@aspeedtech.com> Cc: <lars@metafoo.de>, <pmeerw@pmeerw.net>, <robh+dt@kernel.org>, <joel@jms.id.au>, <andrew@aj.id.au>, <p.zabel@pengutronix.de>, <lgirdwood@gmail.com>, <broonie@kernel.org>, <linux-iio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>, <BMC-SW@aspeedtech.com> Subject: Re: [v5 03/15] iio: adc: aspeed: completes the bitfield declare. Date: Sun, 5 Sep 2021 15:30:54 +0100 [thread overview] Message-ID: <20210905153054.56159999@jic23-huawei> (raw) In-Reply-To: <20210831071458.2334-4-billy_tsai@aspeedtech.com> On Tue, 31 Aug 2021 15:14:46 +0800 Billy Tsai <billy_tsai@aspeedtech.com> wrote: > This patch completes the declare of ADC register bitfields and uses the > same prefix ASPEED_ADC_* for these bitfields. In addition, tidy up space > alignment of the codes. > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> LGTM Applied to the togreg branch of iio.git. Note this won't be going out as non rebasing for a while yet (given mid merge window) so if anyone else has time to look at this that would be much appreciated! Jonathan > --- > drivers/iio/adc/aspeed_adc.c | 64 ++++++++++++++++++++++++++---------- > 1 file changed, 47 insertions(+), 17 deletions(-) > > diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c > index 34ec0c28b2df..f055fe7b2c40 100644 > --- a/drivers/iio/adc/aspeed_adc.c > +++ b/drivers/iio/adc/aspeed_adc.c > @@ -3,6 +3,7 @@ > * Aspeed AST2400/2500 ADC > * > * Copyright (C) 2017 Google, Inc. > + * Copyright (C) 2021 Aspeed Technology Inc. > */ > > #include <linux/clk.h> > @@ -16,6 +17,7 @@ > #include <linux/reset.h> > #include <linux/spinlock.h> > #include <linux/types.h> > +#include <linux/bitfield.h> > > #include <linux/iio/iio.h> > #include <linux/iio/driver.h> > @@ -28,15 +30,39 @@ > #define ASPEED_REG_INTERRUPT_CONTROL 0x04 > #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 > #define ASPEED_REG_CLOCK_CONTROL 0x0C > -#define ASPEED_REG_MAX 0xC0 > - > -#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1) > -#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1) > -#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1) > - > -#define ASPEED_ENGINE_ENABLE BIT(0) > - > -#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_REG_COMPENSATION_TRIM 0xC4 > +/* > + * The register offset between 0xC8~0xCC can be read and won't affect the > + * hardware logic in each version of ADC. > + */ > +#define ASPEED_REG_MAX 0xD0 > + > +#define ASPEED_ADC_ENGINE_ENABLE BIT(0) > +#define ASPEED_ADC_OP_MODE GENMASK(3, 1) > +#define ASPEED_ADC_OP_MODE_PWR_DOWN 0 > +#define ASPEED_ADC_OP_MODE_STANDBY 1 > +#define ASPEED_ADC_OP_MODE_NORMAL 7 > +#define ASPEED_ADC_CTRL_COMPENSATION BIT(4) > +#define ASPEED_ADC_AUTO_COMPENSATION BIT(5) > +/* > + * Bit 6 determines not only the reference voltage range but also the dividing > + * circuit for battery sensing. > + */ > +#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) > +#define ASPEED_ADC_REF_VOLTAGE_2500mV 0 > +#define ASPEED_ADC_REF_VOLTAGE_1200mV 1 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 > +#define ASPEED_ADC_BAT_SENSING_DIV BIT(6) > +#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 > +#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 > +#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_ADC_CH7_MODE BIT(12) > +#define ASPEED_ADC_CH7_NORMAL 0 > +#define ASPEED_ADC_CH7_BAT 1 > +#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) > +#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) > +#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) > > #define ASPEED_ADC_INIT_POLLING_TIME 500 > #define ASPEED_ADC_INIT_TIMEOUT 500000 > @@ -227,7 +253,9 @@ static int aspeed_adc_probe(struct platform_device *pdev) > > if (model_data->wait_init_sequence) { > /* Enable engine in normal mode. */ > - writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE, > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, > + ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE, > data->base + ASPEED_REG_ENGINE_CONTROL); > > /* Wait for initial sequence complete. */ > @@ -246,10 +274,12 @@ static int aspeed_adc_probe(struct platform_device *pdev) > if (ret) > goto clk_enable_error; > > - adc_engine_control_reg_val = GENMASK(31, 16) | > - ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; > + adc_engine_control_reg_val = > + ASPEED_ADC_CTRL_CHANNEL | > + FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE; > writel(adc_engine_control_reg_val, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + data->base + ASPEED_REG_ENGINE_CONTROL); > > model_data = of_device_get_match_data(&pdev->dev); > indio_dev->name = model_data->model_name; > @@ -265,8 +295,8 @@ static int aspeed_adc_probe(struct platform_device *pdev) > return 0; > > iio_register_error: > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > clk_enable_error: > poll_timeout_error: > @@ -284,8 +314,8 @@ static int aspeed_adc_remove(struct platform_device *pdev) > struct aspeed_adc_data *data = iio_priv(indio_dev); > > iio_device_unregister(indio_dev); > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > reset_control_assert(data->rst); > clk_hw_unregister_divider(data->clk_scaler);
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <jic23@kernel.org> To: Billy Tsai <billy_tsai@aspeedtech.com> Cc: <lars@metafoo.de>, <pmeerw@pmeerw.net>, <robh+dt@kernel.org>, <joel@jms.id.au>, <andrew@aj.id.au>, <p.zabel@pengutronix.de>, <lgirdwood@gmail.com>, <broonie@kernel.org>, <linux-iio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>, <BMC-SW@aspeedtech.com> Subject: Re: [v5 03/15] iio: adc: aspeed: completes the bitfield declare. Date: Sun, 5 Sep 2021 15:30:54 +0100 [thread overview] Message-ID: <20210905153054.56159999@jic23-huawei> (raw) In-Reply-To: <20210831071458.2334-4-billy_tsai@aspeedtech.com> On Tue, 31 Aug 2021 15:14:46 +0800 Billy Tsai <billy_tsai@aspeedtech.com> wrote: > This patch completes the declare of ADC register bitfields and uses the > same prefix ASPEED_ADC_* for these bitfields. In addition, tidy up space > alignment of the codes. > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> LGTM Applied to the togreg branch of iio.git. Note this won't be going out as non rebasing for a while yet (given mid merge window) so if anyone else has time to look at this that would be much appreciated! Jonathan > --- > drivers/iio/adc/aspeed_adc.c | 64 ++++++++++++++++++++++++++---------- > 1 file changed, 47 insertions(+), 17 deletions(-) > > diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c > index 34ec0c28b2df..f055fe7b2c40 100644 > --- a/drivers/iio/adc/aspeed_adc.c > +++ b/drivers/iio/adc/aspeed_adc.c > @@ -3,6 +3,7 @@ > * Aspeed AST2400/2500 ADC > * > * Copyright (C) 2017 Google, Inc. > + * Copyright (C) 2021 Aspeed Technology Inc. > */ > > #include <linux/clk.h> > @@ -16,6 +17,7 @@ > #include <linux/reset.h> > #include <linux/spinlock.h> > #include <linux/types.h> > +#include <linux/bitfield.h> > > #include <linux/iio/iio.h> > #include <linux/iio/driver.h> > @@ -28,15 +30,39 @@ > #define ASPEED_REG_INTERRUPT_CONTROL 0x04 > #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 > #define ASPEED_REG_CLOCK_CONTROL 0x0C > -#define ASPEED_REG_MAX 0xC0 > - > -#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1) > -#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1) > -#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1) > - > -#define ASPEED_ENGINE_ENABLE BIT(0) > - > -#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_REG_COMPENSATION_TRIM 0xC4 > +/* > + * The register offset between 0xC8~0xCC can be read and won't affect the > + * hardware logic in each version of ADC. > + */ > +#define ASPEED_REG_MAX 0xD0 > + > +#define ASPEED_ADC_ENGINE_ENABLE BIT(0) > +#define ASPEED_ADC_OP_MODE GENMASK(3, 1) > +#define ASPEED_ADC_OP_MODE_PWR_DOWN 0 > +#define ASPEED_ADC_OP_MODE_STANDBY 1 > +#define ASPEED_ADC_OP_MODE_NORMAL 7 > +#define ASPEED_ADC_CTRL_COMPENSATION BIT(4) > +#define ASPEED_ADC_AUTO_COMPENSATION BIT(5) > +/* > + * Bit 6 determines not only the reference voltage range but also the dividing > + * circuit for battery sensing. > + */ > +#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) > +#define ASPEED_ADC_REF_VOLTAGE_2500mV 0 > +#define ASPEED_ADC_REF_VOLTAGE_1200mV 1 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 > +#define ASPEED_ADC_BAT_SENSING_DIV BIT(6) > +#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 > +#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 > +#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_ADC_CH7_MODE BIT(12) > +#define ASPEED_ADC_CH7_NORMAL 0 > +#define ASPEED_ADC_CH7_BAT 1 > +#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) > +#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) > +#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) > > #define ASPEED_ADC_INIT_POLLING_TIME 500 > #define ASPEED_ADC_INIT_TIMEOUT 500000 > @@ -227,7 +253,9 @@ static int aspeed_adc_probe(struct platform_device *pdev) > > if (model_data->wait_init_sequence) { > /* Enable engine in normal mode. */ > - writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE, > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, > + ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE, > data->base + ASPEED_REG_ENGINE_CONTROL); > > /* Wait for initial sequence complete. */ > @@ -246,10 +274,12 @@ static int aspeed_adc_probe(struct platform_device *pdev) > if (ret) > goto clk_enable_error; > > - adc_engine_control_reg_val = GENMASK(31, 16) | > - ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; > + adc_engine_control_reg_val = > + ASPEED_ADC_CTRL_CHANNEL | > + FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE; > writel(adc_engine_control_reg_val, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + data->base + ASPEED_REG_ENGINE_CONTROL); > > model_data = of_device_get_match_data(&pdev->dev); > indio_dev->name = model_data->model_name; > @@ -265,8 +295,8 @@ static int aspeed_adc_probe(struct platform_device *pdev) > return 0; > > iio_register_error: > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > clk_enable_error: > poll_timeout_error: > @@ -284,8 +314,8 @@ static int aspeed_adc_remove(struct platform_device *pdev) > struct aspeed_adc_data *data = iio_priv(indio_dev); > > iio_device_unregister(indio_dev); > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > reset_control_assert(data->rst); > clk_hw_unregister_divider(data->clk_scaler); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-09-05 14:27 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-31 7:14 [v5 00/15] Add support for ast2600 ADC Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 01/15] iio: adc: aspeed: set driver data when adc probe Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:25 ` Jonathan Cameron 2021-09-05 14:25 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 02/15] dt-bindings: iio: adc: Add ast2600-adc bindings Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-01 1:38 ` Rob Herring 2021-09-01 1:38 ` Rob Herring 2021-09-05 14:27 ` Jonathan Cameron 2021-09-05 14:27 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 03/15] iio: adc: aspeed: completes the bitfield declare Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:30 ` Jonathan Cameron [this message] 2021-09-05 14:30 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 04/15] iio: adc: aspeed: Keep model data to driver data Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:33 ` Jonathan Cameron 2021-09-05 14:33 ` Jonathan Cameron 2021-09-05 14:50 ` Jonathan Cameron 2021-09-05 14:50 ` Jonathan Cameron 2021-09-16 3:52 ` Joel Stanley 2021-09-16 3:52 ` Joel Stanley 2021-09-18 17:55 ` Jonathan Cameron 2021-09-18 17:55 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 05/15] iio: adc: aspeed: Refactory model data structure Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:37 ` Jonathan Cameron 2021-09-05 14:37 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 06/15] iio: adc: aspeed: Add vref config function Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 07/15] iio: adc: aspeed: Set num_channels with model data Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 08/15] iio: adc: aspeed: Use model_data to set clk scaler Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 09/15] iio: adc: aspeed: Use devm_add_action_or_reset Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:51 ` Philipp Zabel 2021-08-31 7:51 ` Philipp Zabel 2021-08-31 7:14 ` [v5 10/15] iio: adc: aspeed: Support ast2600 adc Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 11/15] iio: adc: aspeed: Fix the calculate error of clock Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-09-05 14:47 ` Jonathan Cameron 2021-09-05 14:47 ` Jonathan Cameron 2021-08-31 7:14 ` [v5 12/15] iio: adc: aspeed: Add func to set sampling rate Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 13/15] iio: adc: aspeed: Add compensation phase Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 14/15] iio: adc: aspeed: Support battery sensing Billy Tsai 2021-08-31 7:14 ` Billy Tsai 2021-08-31 7:14 ` [v5 15/15] iio: adc: aspeed: Get and set trimming data Billy Tsai 2021-08-31 7:14 ` Billy Tsai
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