From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Date: Wed, 11 May 2022 23:41:29 +0200 [thread overview] Message-ID: <20220511214132.2281431-1-heiko@sntech.de> (raw) This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. As Palmer suggested, merging might have to wait until the cache instructions have landed in compilers, but I wanted to put the block-size changes out there for people to look at already and also update the series to match the current svpbmt state. changes in v2: - cbom-block-size is hardware-specific and comes from firmware - update Kconfig name to use the ISA extension name - select the ALTERNATIVES symbol when enabled - shorten the line lengths of the errata-assembly Heiko Stuebner (3): dt-bindings: riscv: document cbom-block-size riscv: Implement Zicbom-based cache management operations riscv: implement cache-management errata for T-Head SoCs .../devicetree/bindings/riscv/cpus.yaml | 7 ++ arch/riscv/Kconfig | 15 +++ arch/riscv/Kconfig.erratas | 10 ++ arch/riscv/errata/thead/errata.c | 5 + arch/riscv/include/asm/cacheflush.h | 6 ++ arch/riscv/include/asm/errata_list.h | 80 +++++++++++++++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 17 ++++ arch/riscv/kernel/setup.c | 2 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/dma-noncoherent.c | 92 +++++++++++++++++++ 12 files changed, 235 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/mm/dma-noncoherent.c -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Date: Wed, 11 May 2022 23:41:29 +0200 [thread overview] Message-ID: <20220511214132.2281431-1-heiko@sntech.de> (raw) This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. As Palmer suggested, merging might have to wait until the cache instructions have landed in compilers, but I wanted to put the block-size changes out there for people to look at already and also update the series to match the current svpbmt state. changes in v2: - cbom-block-size is hardware-specific and comes from firmware - update Kconfig name to use the ISA extension name - select the ALTERNATIVES symbol when enabled - shorten the line lengths of the errata-assembly Heiko Stuebner (3): dt-bindings: riscv: document cbom-block-size riscv: Implement Zicbom-based cache management operations riscv: implement cache-management errata for T-Head SoCs .../devicetree/bindings/riscv/cpus.yaml | 7 ++ arch/riscv/Kconfig | 15 +++ arch/riscv/Kconfig.erratas | 10 ++ arch/riscv/errata/thead/errata.c | 5 + arch/riscv/include/asm/cacheflush.h | 6 ++ arch/riscv/include/asm/errata_list.h | 80 +++++++++++++++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 17 ++++ arch/riscv/kernel/setup.c | 2 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/dma-noncoherent.c | 92 +++++++++++++++++++ 12 files changed, 235 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/mm/dma-noncoherent.c -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2022-05-11 21:41 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-11 21:41 Heiko Stuebner [this message] 2022-05-11 21:41 ` [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner 2022-05-11 21:41 ` [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size Heiko Stuebner 2022-05-11 21:41 ` Heiko Stuebner 2022-05-12 4:18 ` Anup Patel 2022-05-12 4:18 ` Anup Patel 2022-05-13 10:28 ` Christoph Müllner 2022-05-13 10:28 ` Christoph Müllner 2022-05-18 0:25 ` Rob Herring 2022-05-18 0:25 ` Rob Herring 2022-05-18 8:22 ` Philipp Tomsich 2022-05-18 8:22 ` Philipp Tomsich 2022-05-18 9:02 ` Heiko Stübner 2022-05-18 9:02 ` Heiko Stübner 2022-05-18 9:10 ` Anup Patel 2022-05-18 9:10 ` Anup Patel 2022-05-18 9:20 ` Philipp Tomsich 2022-05-18 9:20 ` Philipp Tomsich 2022-05-25 15:14 ` Heiko Stübner 2022-05-25 15:14 ` Heiko Stübner 2022-05-11 21:41 ` [PATCH v2 2/3] riscv: Implement Zicbom-based cache management operations Heiko Stuebner 2022-05-11 21:41 ` Heiko Stuebner 2022-05-12 4:19 ` Anup Patel 2022-05-12 4:19 ` Anup Patel 2022-05-13 13:38 ` Guo Ren 2022-05-13 13:38 ` Guo Ren 2022-05-16 6:00 ` Christoph Hellwig 2022-05-16 6:00 ` Christoph Hellwig 2022-05-11 21:41 ` [PATCH v2 3/3] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner 2022-05-11 21:41 ` Heiko Stuebner 2022-05-12 4:40 ` Anup Patel 2022-05-12 4:40 ` Anup Patel 2022-05-13 13:37 ` Guo Ren 2022-05-13 13:37 ` Guo Ren -- strict thread matches above, loose matches on Subject: below -- 2022-05-11 21:40 [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner 2022-05-11 21:40 ` Heiko Stuebner
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220511214132.2281431-1-heiko@sntech.de \ --to=heiko@sntech.de \ --cc=anup@brainfault.org \ --cc=atishp@atishpatra.org \ --cc=cmuellner@linux.com \ --cc=devicetree@vger.kernel.org \ --cc=guoren@kernel.org \ --cc=krzk+dt@kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mick@ics.forth.gr \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=philipp.tomsich@vrull.eu \ --cc=robh+dt@kernel.org \ --cc=samuel@sholland.org \ --cc=wefu@redhat.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.