From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data
Date: Thu, 10 Nov 2022 18:00:32 +0300 [thread overview]
Message-ID: <20221110150035.2824580-2-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index df05e60bed9a..c0f32054e472 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -27,6 +27,7 @@
#include <linux/interrupt.h>
#include <linux/bitfield.h>
#include <linux/pinctrl/consumer.h>
+#include <dt-bindings/mmc/meson-gx-mmc.h>
#define DRIVER_NAME "meson-gx-mmc"
@@ -36,8 +37,6 @@
#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
#define CLK_TX_PHASE_MASK GENMASK(11, 10)
#define CLK_RX_PHASE_MASK GENMASK(13, 12)
-#define CLK_PHASE_0 0
-#define CLK_PHASE_180 2
#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
#define CLK_V2_ALWAYS_ON BIT(24)
@@ -428,13 +427,22 @@ static int meson_mmc_clk_init(struct meson_host *host)
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
const char *clk_parent[1];
u32 clk_reg;
+ u32 phase[3]; // <core_phase, tx_phase, rx_phase>
+
+ if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
+ "amlogic,mmc-phase", phase, 3) < 0)) {
+ dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
+ phase[0] = CLK_PHASE_180;
+ phase[1] = CLK_PHASE_0;
+ phase[2] = CLK_PHASE_0;
+ }
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
clk_reg = CLK_ALWAYS_ON(host);
clk_reg |= CLK_DIV_MASK;
- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
- clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
- clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
+ clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
+ clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
writel(clk_reg, host->regs + SD_EMMC_CLOCK);
--
2.30.2
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data
Date: Thu, 10 Nov 2022 18:00:32 +0300 [thread overview]
Message-ID: <20221110150035.2824580-2-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index df05e60bed9a..c0f32054e472 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -27,6 +27,7 @@
#include <linux/interrupt.h>
#include <linux/bitfield.h>
#include <linux/pinctrl/consumer.h>
+#include <dt-bindings/mmc/meson-gx-mmc.h>
#define DRIVER_NAME "meson-gx-mmc"
@@ -36,8 +37,6 @@
#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
#define CLK_TX_PHASE_MASK GENMASK(11, 10)
#define CLK_RX_PHASE_MASK GENMASK(13, 12)
-#define CLK_PHASE_0 0
-#define CLK_PHASE_180 2
#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
#define CLK_V2_ALWAYS_ON BIT(24)
@@ -428,13 +427,22 @@ static int meson_mmc_clk_init(struct meson_host *host)
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
const char *clk_parent[1];
u32 clk_reg;
+ u32 phase[3]; // <core_phase, tx_phase, rx_phase>
+
+ if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
+ "amlogic,mmc-phase", phase, 3) < 0)) {
+ dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
+ phase[0] = CLK_PHASE_180;
+ phase[1] = CLK_PHASE_0;
+ phase[2] = CLK_PHASE_0;
+ }
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
clk_reg = CLK_ALWAYS_ON(host);
clk_reg |= CLK_DIV_MASK;
- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
- clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
- clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
+ clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
+ clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
writel(clk_reg, host->regs + SD_EMMC_CLOCK);
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data
Date: Thu, 10 Nov 2022 18:00:32 +0300 [thread overview]
Message-ID: <20221110150035.2824580-2-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index df05e60bed9a..c0f32054e472 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -27,6 +27,7 @@
#include <linux/interrupt.h>
#include <linux/bitfield.h>
#include <linux/pinctrl/consumer.h>
+#include <dt-bindings/mmc/meson-gx-mmc.h>
#define DRIVER_NAME "meson-gx-mmc"
@@ -36,8 +37,6 @@
#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
#define CLK_TX_PHASE_MASK GENMASK(11, 10)
#define CLK_RX_PHASE_MASK GENMASK(13, 12)
-#define CLK_PHASE_0 0
-#define CLK_PHASE_180 2
#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
#define CLK_V2_ALWAYS_ON BIT(24)
@@ -428,13 +427,22 @@ static int meson_mmc_clk_init(struct meson_host *host)
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
const char *clk_parent[1];
u32 clk_reg;
+ u32 phase[3]; // <core_phase, tx_phase, rx_phase>
+
+ if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
+ "amlogic,mmc-phase", phase, 3) < 0)) {
+ dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
+ phase[0] = CLK_PHASE_180;
+ phase[1] = CLK_PHASE_0;
+ phase[2] = CLK_PHASE_0;
+ }
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
clk_reg = CLK_ALWAYS_ON(host);
clk_reg |= CLK_DIV_MASK;
- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
- clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
- clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
+ clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
+ clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
writel(clk_reg, host->regs + SD_EMMC_CLOCK);
--
2.30.2
next prev parent reply other threads:[~2022-11-10 15:01 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 15:00 [PATCH 0/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov [this message]
2022-11-10 15:00 ` [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-12 22:57 ` Martin Blumenstingl
2022-11-12 22:57 ` Martin Blumenstingl
2022-11-12 22:57 ` Martin Blumenstingl
2022-11-10 15:00 ` [PATCH 2/4] arm64: amlogic: mmc: meson-gx: Add dts binding include for " Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-12 22:59 ` Martin Blumenstingl
2022-11-12 22:59 ` Martin Blumenstingl
2022-11-12 22:59 ` Martin Blumenstingl
2022-11-10 15:00 ` [PATCH 3/4] arm64: amlogic: dts: meson: update meson-axg device-tree for new core, tx, rx phase clock settings Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` [PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation for new config option amlogic,mmc-phase Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-12 23:01 ` Martin Blumenstingl
2022-11-12 23:01 ` Martin Blumenstingl
2022-11-12 23:01 ` Martin Blumenstingl
2022-11-23 16:23 ` Krzysztof Kozlowski
2022-11-23 16:23 ` Krzysztof Kozlowski
2022-11-23 16:23 ` Krzysztof Kozlowski
2022-11-13 20:06 ` [PATCH 0/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx Jerome Brunet
2022-11-13 20:06 ` Jerome Brunet
2022-11-13 20:06 ` Jerome Brunet
2022-11-24 6:22 ` Vyacheslav
2022-11-24 6:22 ` Vyacheslav
2022-11-24 6:22 ` Vyacheslav
2022-11-25 10:28 ` Jerome Brunet
2022-11-25 10:28 ` Jerome Brunet
2022-11-25 10:28 ` Jerome Brunet
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