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From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation for new config option amlogic,mmc-phase
Date: Thu, 10 Nov 2022 18:00:35 +0300	[thread overview]
Message-ID: <20221110150035.2824580-5-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>

- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
clock with values:
	0: CLK_PHASE_0 - 0 phase
	1: CLK_PHASE_90 - 90 phase
	2: CLK_PHASE_180 - 180 phase
	3: CLK_PHASE_270 - 270 phase
By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.

Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>

diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index ccc5358db131..98c89c5b3455 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -25,6 +25,12 @@ Required properties:
 Optional properties:
 - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
   DRAM memory, like on the G12A dedicated SDIO controller.
+- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values:
+	0: CLK_PHASE_0 - 0 phase
+	1: CLK_PHASE_90 - 90 phase
+	2: CLK_PHASE_180 - 180 phase
+	3: CLK_PHASE_270 - 270 phase
+  By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
 
 Example:
 
@@ -36,4 +42,5 @@ Example:
 		clock-names = "core", "clkin0", "clkin1";
 		pinctrl-0 = <&emmc_pins>;
 		resets = <&reset RESET_SD_EMMC_A>;
+		amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
 	};
-- 
2.30.2


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

WARNING: multiple messages have this Message-ID (diff)
From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation for new config option amlogic,mmc-phase
Date: Thu, 10 Nov 2022 18:00:35 +0300	[thread overview]
Message-ID: <20221110150035.2824580-5-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>

- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
clock with values:
	0: CLK_PHASE_0 - 0 phase
	1: CLK_PHASE_90 - 90 phase
	2: CLK_PHASE_180 - 180 phase
	3: CLK_PHASE_270 - 270 phase
By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.

Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>

diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index ccc5358db131..98c89c5b3455 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -25,6 +25,12 @@ Required properties:
 Optional properties:
 - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
   DRAM memory, like on the G12A dedicated SDIO controller.
+- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values:
+	0: CLK_PHASE_0 - 0 phase
+	1: CLK_PHASE_90 - 90 phase
+	2: CLK_PHASE_180 - 180 phase
+	3: CLK_PHASE_270 - 270 phase
+  By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
 
 Example:
 
@@ -36,4 +42,5 @@ Example:
 		clock-names = "core", "clkin0", "clkin1";
 		pinctrl-0 = <&emmc_pins>;
 		resets = <&reset RESET_SD_EMMC_A>;
+		amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
 	};
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation for new config option amlogic,mmc-phase
Date: Thu, 10 Nov 2022 18:00:35 +0300	[thread overview]
Message-ID: <20221110150035.2824580-5-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>

- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
clock with values:
	0: CLK_PHASE_0 - 0 phase
	1: CLK_PHASE_90 - 90 phase
	2: CLK_PHASE_180 - 180 phase
	3: CLK_PHASE_270 - 270 phase
By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.

Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>

diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index ccc5358db131..98c89c5b3455 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -25,6 +25,12 @@ Required properties:
 Optional properties:
 - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
   DRAM memory, like on the G12A dedicated SDIO controller.
+- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values:
+	0: CLK_PHASE_0 - 0 phase
+	1: CLK_PHASE_90 - 90 phase
+	2: CLK_PHASE_180 - 180 phase
+	3: CLK_PHASE_270 - 270 phase
+  By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
 
 Example:
 
@@ -36,4 +42,5 @@ Example:
 		clock-names = "core", "clkin0", "clkin1";
 		pinctrl-0 = <&emmc_pins>;
 		resets = <&reset RESET_SD_EMMC_A>;
+		amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
 	};
-- 
2.30.2


  parent reply	other threads:[~2022-11-10 15:01 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-10 15:00 [PATCH 0/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data Vyacheslav Bocharov
2022-11-10 15:00   ` Vyacheslav Bocharov
2022-11-10 15:00   ` Vyacheslav Bocharov
2022-11-12 22:57   ` Martin Blumenstingl
2022-11-12 22:57     ` Martin Blumenstingl
2022-11-12 22:57     ` Martin Blumenstingl
2022-11-10 15:00 ` [PATCH 2/4] arm64: amlogic: mmc: meson-gx: Add dts binding include for " Vyacheslav Bocharov
2022-11-10 15:00   ` Vyacheslav Bocharov
2022-11-10 15:00   ` Vyacheslav Bocharov
2022-11-12 22:59   ` Martin Blumenstingl
2022-11-12 22:59     ` Martin Blumenstingl
2022-11-12 22:59     ` Martin Blumenstingl
2022-11-10 15:00 ` [PATCH 3/4] arm64: amlogic: dts: meson: update meson-axg device-tree for new core, tx, rx phase clock settings Vyacheslav Bocharov
2022-11-10 15:00   ` Vyacheslav Bocharov
2022-11-10 15:00   ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov [this message]
2022-11-10 15:00   ` [PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation for new config option amlogic,mmc-phase Vyacheslav Bocharov
2022-11-10 15:00   ` Vyacheslav Bocharov
2022-11-12 23:01   ` Martin Blumenstingl
2022-11-12 23:01     ` Martin Blumenstingl
2022-11-12 23:01     ` Martin Blumenstingl
2022-11-23 16:23   ` Krzysztof Kozlowski
2022-11-23 16:23     ` Krzysztof Kozlowski
2022-11-23 16:23     ` Krzysztof Kozlowski
2022-11-13 20:06 ` [PATCH 0/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx Jerome Brunet
2022-11-13 20:06   ` Jerome Brunet
2022-11-13 20:06   ` Jerome Brunet
2022-11-24  6:22   ` Vyacheslav
2022-11-24  6:22     ` Vyacheslav
2022-11-24  6:22     ` Vyacheslav
2022-11-25 10:28     ` Jerome Brunet
2022-11-25 10:28       ` Jerome Brunet
2022-11-25 10:28       ` Jerome Brunet

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