From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v1 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Date: Fri, 20 Jan 2023 10:44:45 +0800 [thread overview] Message-ID: <20230120024445.244345-12-xingyu.wu@starfivetech.com> (raw) In-Reply-To: <20230120024445.244345-1-xingyu.wu@starfivetech.com> Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110 System-Top-Group, Image-Signal-Process and Video-Output clock and reset drivers for the JH7110 RISC-V SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index ab0822ce2095..cfbaff4ea64b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/clock/starfive,jh7110-crg.h> +#include <dt-bindings/power/starfive,jh7110-pmu.h> #include <dt-bindings/reset/starfive,jh7110-crg.h> / { @@ -324,6 +325,25 @@ uart2: serial@10020000 { status = "disabled"; }; + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -424,5 +444,44 @@ pwrc: power-controller@17030000 { interrupts = <111>; #power-domain-cells = <1>; }; + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x0 0x19810000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + reset-names = "isp_top_core", + "isp_top_axi", + "noc_bus_isp_axi"; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; + + voutcrg: clock-controller@295C0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x0 0x295C0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + reset-names = "vout_top_src"; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; }; }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v1 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Date: Fri, 20 Jan 2023 10:44:45 +0800 [thread overview] Message-ID: <20230120024445.244345-12-xingyu.wu@starfivetech.com> (raw) In-Reply-To: <20230120024445.244345-1-xingyu.wu@starfivetech.com> Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110 System-Top-Group, Image-Signal-Process and Video-Output clock and reset drivers for the JH7110 RISC-V SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index ab0822ce2095..cfbaff4ea64b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/clock/starfive,jh7110-crg.h> +#include <dt-bindings/power/starfive,jh7110-pmu.h> #include <dt-bindings/reset/starfive,jh7110-crg.h> / { @@ -324,6 +325,25 @@ uart2: serial@10020000 { status = "disabled"; }; + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -424,5 +444,44 @@ pwrc: power-controller@17030000 { interrupts = <111>; #power-domain-cells = <1>; }; + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x0 0x19810000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + reset-names = "isp_top_core", + "isp_top_axi", + "noc_bus_isp_axi"; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; + + voutcrg: clock-controller@295C0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x0 0x295C0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + reset-names = "vout_top_src"; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; }; }; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-20 2:45 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-20 2:44 [PATCH v1 00/11] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 01/11] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 8:11 ` Krzysztof Kozlowski 2023-01-20 8:11 ` Krzysztof Kozlowski 2023-01-30 6:17 ` Xingyu Wu 2023-01-30 6:17 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 02/11] reset: starfive: jh7110: Add StarFive System-Top-Group reset support Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 03/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-26 2:33 ` Stephen Boyd 2023-01-26 2:33 ` Stephen Boyd 2023-01-30 8:02 ` Xingyu Wu 2023-01-30 8:02 ` Xingyu Wu 2023-01-31 0:35 ` Stephen Boyd 2023-01-31 0:35 ` Stephen Boyd 2023-01-31 6:51 ` Xingyu Wu 2023-01-31 6:51 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 04/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 8:12 ` Krzysztof Kozlowski 2023-01-20 8:12 ` Krzysztof Kozlowski 2023-01-30 8:03 ` Xingyu Wu 2023-01-30 8:03 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 05/11] reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 06/11] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-26 2:35 ` Stephen Boyd 2023-01-26 2:35 ` Stephen Boyd 2023-01-30 8:09 ` Xingyu Wu 2023-01-30 8:09 ` Xingyu Wu 2023-01-31 0:38 ` Stephen Boyd 2023-01-31 0:38 ` Stephen Boyd 2023-01-31 6:52 ` Xingyu Wu 2023-01-31 6:52 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 07/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 8:13 ` Krzysztof Kozlowski 2023-01-20 8:13 ` Krzysztof Kozlowski 2023-01-30 8:10 ` Xingyu Wu 2023-01-30 8:10 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 08/11] reset: starfive: jh7110: Add StarFive Video-Output reset support Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 09/11] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 2:44 ` [PATCH v1 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu 2023-01-20 2:44 ` Xingyu Wu [this message] 2023-01-20 2:44 ` [PATCH v1 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
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