From: Prashant Gaikwad <pgaikwad@nvidia.com> To: linux-arm-kernel@lists.infradead.org Subject: Re: Device tree binding for DVFS table Date: Thu, 12 Jul 2012 04:34:40 +0000 [thread overview] Message-ID: <4FFE5110.8020803@nvidia.com> (raw) In-Reply-To: <20120711134956.GB9437@tbergstrom-lnx.Nvidia.com> On Wednesday 11 July 2012 07:19 PM, Peter De Schrijver wrote: > On Wed, Jul 11, 2012 at 03:08:14PM +0200, 함명주 wrote: >>> Hi, >>> >>> I am working on DT binding for Tegra DVFS. >>> >>> For Tegra, DVFS node mainly consists of frequency and voltage pairs. >>> Frequency in the pair may change for different process. E.g. for process >>> 1 CPU clock frequency could be 900MHz at 1V while for process 2 it could >>> be 1GHz at 1V. >>> Tegra uses vendor specific ids to identify the correct frequency table. >> Hello, >> >> It seems that in the example, the values in "voltage-array" and >> "frequencies" are switched. >> >> Anyway, what about SoCs that reads information from IEM (or any other module) >> to measure gate delays or some other value to set the appriorate voltage values >> for every possible frequency? I remember some of Exynos SoCs have been doing >> it; dynamically measure the characteristics at boot-up time and apply voltages >> accordingly; they couldn't identify it based on the chip-id or simply by reading >> a single register. >> > > But in that case you would have a nominal voltage for each OPP which gets > adjusted at boottime or runtime depending on the exact silicon characteristics? > I would say the DT binding should then specify 1 table with the nominal values > and leave the dynamics to the driver. It makes sense or is it different than this? > Cheers, > > Peter. >
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From: pgaikwad@nvidia.com (Prashant Gaikwad) To: linux-arm-kernel@lists.infradead.org Subject: Device tree binding for DVFS table Date: Thu, 12 Jul 2012 09:52:40 +0530 [thread overview] Message-ID: <4FFE5110.8020803@nvidia.com> (raw) In-Reply-To: <20120711134956.GB9437@tbergstrom-lnx.Nvidia.com> On Wednesday 11 July 2012 07:19 PM, Peter De Schrijver wrote: > On Wed, Jul 11, 2012 at 03:08:14PM +0200, ??? wrote: >>> Hi, >>> >>> I am working on DT binding for Tegra DVFS. >>> >>> For Tegra, DVFS node mainly consists of frequency and voltage pairs. >>> Frequency in the pair may change for different process. E.g. for process >>> 1 CPU clock frequency could be 900MHz at 1V while for process 2 it could >>> be 1GHz at 1V. >>> Tegra uses vendor specific ids to identify the correct frequency table. >> Hello, >> >> It seems that in the example, the values in "voltage-array" and >> "frequencies" are switched. >> >> Anyway, what about SoCs that reads information from IEM (or any other module) >> to measure gate delays or some other value to set the appriorate voltage values >> for every possible frequency? I remember some of Exynos SoCs have been doing >> it; dynamically measure the characteristics at boot-up time and apply voltages >> accordingly; they couldn't identify it based on the chip-id or simply by reading >> a single register. >> > > But in that case you would have a nominal voltage for each OPP which gets > adjusted at boottime or runtime depending on the exact silicon characteristics? > I would say the DT binding should then specify 1 table with the nominal values > and leave the dynamics to the driver. It makes sense or is it different than this? > Cheers, > > Peter. >
next prev parent reply other threads:[~2012-07-12 4:34 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2012-07-11 13:08 Device tree binding for DVFS table 함명주 2012-07-11 13:08 ` 함명주 2012-07-11 13:49 ` Peter De Schrijver 2012-07-11 13:49 ` Peter De Schrijver 2012-07-11 13:49 ` Peter De Schrijver 2012-07-11 13:49 ` Peter De Schrijver 2012-07-12 4:22 ` Prashant Gaikwad [this message] 2012-07-12 4:34 ` Prashant Gaikwad -- strict thread matches above, loose matches on Subject: below -- 2012-07-11 12:56 Prashant Gaikwad 2012-07-11 13:08 ` Prashant Gaikwad 2012-07-11 14:03 ` Rob Herring 2012-07-11 14:03 ` Rob Herring 2012-07-11 14:44 ` Mark Brown 2012-07-11 14:44 ` Mark Brown 2012-07-11 20:04 ` Mike Turquette 2012-07-11 20:04 ` Mike Turquette 2012-07-12 4:14 ` Prashant Gaikwad 2012-07-12 4:26 ` Prashant Gaikwad 2012-07-12 14:10 ` Peter De Schrijver 2012-07-12 14:10 ` Peter De Schrijver 2012-07-12 17:10 ` Mike Turquette 2012-07-12 17:10 ` Mike Turquette 2012-07-12 17:15 ` Mark Brown 2012-07-12 17:15 ` Mark Brown 2012-07-13 10:34 ` Peter De Schrijver 2012-07-13 10:34 ` Peter De Schrijver 2012-07-13 17:25 ` Mike Turquette 2012-07-13 17:25 ` Mike Turquette 2012-07-12 4:17 ` Prashant Gaikwad 2012-07-12 4:29 ` Prashant Gaikwad 2012-07-12 15:23 ` Mark Brown 2012-07-12 15:23 ` Mark Brown 2012-07-12 17:01 ` Mike Turquette 2012-07-12 17:01 ` Mike Turquette 2012-07-12 8:19 ` Peter De Schrijver 2012-07-12 8:19 ` Peter De Schrijver 2012-07-12 4:08 ` Prashant Gaikwad 2012-07-12 4:20 ` Prashant Gaikwad 2012-07-13 18:30 ` Prashant Gaikwad 2012-07-13 18:42 ` Prashant Gaikwad 2012-07-15 21:40 ` Mark Brown 2012-07-15 21:40 ` Mark Brown 2012-07-15 23:42 ` Rob Herring 2012-07-15 23:42 ` Rob Herring 2012-07-16 18:36 ` Turquette, Mike 2012-07-16 18:36 ` Turquette, Mike 2012-07-17 12:37 ` Prashant Gaikwad 2012-07-17 12:49 ` Prashant Gaikwad 2012-07-17 13:20 ` Mark Brown 2012-07-17 13:20 ` Mark Brown 2012-07-17 14:22 ` Prashant Gaikwad 2012-07-17 14:34 ` Prashant Gaikwad 2012-07-17 14:37 ` Mark Brown 2012-07-17 14:37 ` Mark Brown 2012-07-18 12:46 ` Prashant Gaikwad 2012-07-18 12:58 ` Prashant Gaikwad 2012-07-18 21:19 ` Mark Brown 2012-07-18 21:19 ` Mark Brown 2012-07-18 17:08 ` Shawn Guo 2012-07-18 17:08 ` Shawn Guo
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