From: James Morse <james.morse@arm.com> To: Xie XiuQi <xiexiuqi@huawei.com> Cc: christoffer.dall@linaro.org, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, fu.wei@linaro.org, rostedt@goodmis.org, hanjun.guo@linaro.org, shiju.jose@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, gengdongjiu@huawei.com, zhengqiang10@huawei.com, wuquanming@huawei.com, wangxiongfeng2@huawei.com Subject: Re: [PATCH v3 2/8] acpi: apei: handle SEI notification type for ARMv8 Date: Fri, 31 Mar 2017 17:20:26 +0100 [thread overview] Message-ID: <58DE81CA.3020803@arm.com> (raw) In-Reply-To: <1490869877-118713-3-git-send-email-xiexiuqi@huawei.com> Hi Xie XiuQi, On 30/03/17 11:31, Xie XiuQi wrote: > ARM APEI extension proposal added SEI (asynchronous SError interrupt) > notification type for ARMv8. > > Add a new GHES error source handling function for SEI. In firmware > first mode, if an error source's notification type is SEI. Then GHES > could parse and report the detail error information. The APEI additions are unsafe until patch 4 as SEA can interrupt SEI and deadlock while trying to take the same set of locks. This patch needs to be after that interaction is fixed/prevented, or we should prevent it by adding a depends-on-not to the Kconfig to prevent SEI and SEA being registered at the same time. (as a short term fix). (more comments on this on that later patch) > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index e52be6a..53710a2 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -625,6 +627,14 @@ asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) bad_mode() is called in other scenarios too, for example executing an undefined instruction at EL1. You split the SError path out of the vectors in patch 7, I think we should do that here. > handler[reason], smp_processor_id(), esr, > esr_get_class_string(esr)); > > + /* > + * In firmware first mode, we could assume firmware will only generate one > + * of cper records at a time. There is no risk for one cpu to parse ghes table. > + */ I don't follow this comment, is this saying SError can't interrupt SError? We already get this guarantee as the CPU masks SError when it takes an exception. Firmware can generate multiple CPER records for a single 'event'. The CPER records are the 'Data' in ACPI:Table 18-343 Generic Error Data Entry, and there are 'zero or more' of these with a 'Generic Error Status Block' header that describes the overall event. (Table 18-342). I don't think we need this comment. > + if (IS_ENABLED(CONFIG_ACPI_APEI_SEI) && ESR_ELx_EC(esr) == ESR_ELx_EC_SERROR) { > + ghes_notify_sei(); > + } > die("Oops - bad mode", regs, 0); > local_irq_disable(); > panic("bad mode"); Thanks, James
WARNING: multiple messages have this Message-ID (diff)
From: james.morse@arm.com (James Morse) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/8] acpi: apei: handle SEI notification type for ARMv8 Date: Fri, 31 Mar 2017 17:20:26 +0100 [thread overview] Message-ID: <58DE81CA.3020803@arm.com> (raw) In-Reply-To: <1490869877-118713-3-git-send-email-xiexiuqi@huawei.com> Hi Xie XiuQi, On 30/03/17 11:31, Xie XiuQi wrote: > ARM APEI extension proposal added SEI (asynchronous SError interrupt) > notification type for ARMv8. > > Add a new GHES error source handling function for SEI. In firmware > first mode, if an error source's notification type is SEI. Then GHES > could parse and report the detail error information. The APEI additions are unsafe until patch 4 as SEA can interrupt SEI and deadlock while trying to take the same set of locks. This patch needs to be after that interaction is fixed/prevented, or we should prevent it by adding a depends-on-not to the Kconfig to prevent SEI and SEA being registered at the same time. (as a short term fix). (more comments on this on that later patch) > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index e52be6a..53710a2 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -625,6 +627,14 @@ asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) bad_mode() is called in other scenarios too, for example executing an undefined instruction at EL1. You split the SError path out of the vectors in patch 7, I think we should do that here. > handler[reason], smp_processor_id(), esr, > esr_get_class_string(esr)); > > + /* > + * In firmware first mode, we could assume firmware will only generate one > + * of cper records at a time. There is no risk for one cpu to parse ghes table. > + */ I don't follow this comment, is this saying SError can't interrupt SError? We already get this guarantee as the CPU masks SError when it takes an exception. Firmware can generate multiple CPER records for a single 'event'. The CPER records are the 'Data' in ACPI:Table 18-343 Generic Error Data Entry, and there are 'zero or more' of these with a 'Generic Error Status Block' header that describes the overall event. (Table 18-342). I don't think we need this comment. > + if (IS_ENABLED(CONFIG_ACPI_APEI_SEI) && ESR_ELx_EC(esr) == ESR_ELx_EC_SERROR) { > + ghes_notify_sei(); > + } > die("Oops - bad mode", regs, 0); > local_irq_disable(); > panic("bad mode"); Thanks, James
next prev parent reply other threads:[~2017-03-31 16:20 UTC|newest] Thread overview: 139+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-30 10:31 [PATCH v3 0/8] arm64: acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 1/8] trace: ras: add ARM processor error information trace event Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 16:02 ` Steven Rostedt 2017-03-30 16:02 ` Steven Rostedt 2017-03-30 16:02 ` Steven Rostedt 2017-04-06 9:03 ` Xie XiuQi 2017-04-06 9:03 ` Xie XiuQi 2017-04-06 9:03 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 2/8] acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-31 16:20 ` James Morse [this message] 2017-03-31 16:20 ` James Morse 2017-04-06 9:11 ` Xie XiuQi 2017-04-06 9:11 ` Xie XiuQi 2017-04-06 9:11 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 3/8] arm64: apei: add a per-cpu variable to indecate sei is processing Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 4/8] APEI: GHES: reserve a virtual page for SEI context Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-31 16:22 ` James Morse 2017-03-31 16:22 ` James Morse 2017-04-06 9:25 ` Xie XiuQi 2017-04-06 9:25 ` Xie XiuQi 2017-04-06 9:25 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 5/8] arm64: KVM: add guest SEI support Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 6/8] arm64: RAS: add ras extension runtime detection Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 7/8] arm64: exception: handle asynchronous SError interrupt Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-04-13 8:44 ` Xiongfeng Wang 2017-04-13 8:44 ` Xiongfeng Wang 2017-04-13 8:44 ` Xiongfeng Wang 2017-04-13 10:51 ` Mark Rutland 2017-04-13 10:51 ` Mark Rutland 2017-04-13 10:51 ` Mark Rutland 2017-04-14 7:03 ` Xie XiuQi 2017-04-14 7:03 ` Xie XiuQi 2017-04-14 7:03 ` Xie XiuQi 2017-04-18 1:09 ` Xiongfeng Wang 2017-04-18 1:09 ` Xiongfeng Wang 2017-04-18 1:09 ` Xiongfeng Wang 2017-04-18 10:51 ` James Morse 2017-04-18 10:51 ` James Morse 2017-04-18 10:51 ` James Morse 2017-04-19 2:37 ` Xiongfeng Wang 2017-04-19 2:37 ` Xiongfeng Wang 2017-04-19 2:37 ` Xiongfeng Wang 2017-04-20 8:52 ` James Morse 2017-04-20 8:52 ` James Morse 2017-04-20 8:52 ` James Morse 2017-04-21 11:33 ` Xiongfeng Wang 2017-04-21 11:33 ` Xiongfeng Wang 2017-04-21 11:33 ` Xiongfeng Wang 2017-04-24 17:14 ` James Morse 2017-04-24 17:14 ` James Morse 2017-04-24 17:14 ` James Morse 2017-04-28 2:55 ` Xiongfeng Wang 2017-04-28 2:55 ` Xiongfeng Wang 2017-04-28 2:55 ` Xiongfeng Wang 2017-05-08 17:27 ` James Morse 2017-05-08 17:27 ` James Morse 2017-05-09 2:16 ` Xiongfeng Wang 2017-05-09 2:16 ` Xiongfeng Wang 2017-05-09 2:16 ` Xiongfeng Wang 2017-04-21 10:46 ` Xiongfeng Wang 2017-04-21 10:46 ` Xiongfeng Wang 2017-04-21 10:46 ` Xiongfeng Wang 2017-03-30 10:31 ` [PATCH v3 8/8] arm64: exception: check shared writable page in SEI handler Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-04-07 15:56 ` James Morse 2017-04-07 15:56 ` James Morse 2017-04-07 15:56 ` James Morse 2017-04-12 8:35 ` Xiongfeng Wang 2017-04-12 8:35 ` Xiongfeng Wang 2017-04-12 8:35 ` Xiongfeng Wang 2017-03-30 10:31 ` [PATCH v3 0/8] arm64: acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 1/8] trace: ras: add ARM processor error information trace event Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-04-14 20:36 ` Baicar, Tyler 2017-04-14 20:36 ` Baicar, Tyler 2017-04-17 3:08 ` Xie XiuQi 2017-04-17 3:08 ` Xie XiuQi 2017-04-17 3:08 ` Xie XiuQi 2017-04-17 3:16 ` Xie XiuQi 2017-04-17 3:16 ` Xie XiuQi 2017-04-17 3:16 ` Xie XiuQi 2017-04-17 17:18 ` Baicar, Tyler 2017-04-17 17:18 ` Baicar, Tyler 2017-04-18 2:22 ` Xie XiuQi 2017-04-18 2:22 ` Xie XiuQi 2017-04-18 2:22 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 2/8] acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 3/8] arm64: apei: add a per-cpu variable to indecate sei is processing Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 4/8] APEI: GHES: reserve a virtual page for SEI context Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 5/8] arm64: KVM: add guest SEI support Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 6/8] arm64: RAS: add ras extension runtime detection Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 7/8] arm64: exception: handle asynchronous SError interrupt Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` [PATCH v3 8/8] arm64: exception: check shared writable page in SEI handler Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi 2017-03-30 10:31 ` Xie XiuQi
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=58DE81CA.3020803@arm.com \ --to=james.morse@arm.com \ --cc=catalin.marinas@arm.com \ --cc=christoffer.dall@linaro.org \ --cc=fu.wei@linaro.org \ --cc=gengdongjiu@huawei.com \ --cc=hanjun.guo@linaro.org \ --cc=kvm@vger.kernel.org \ --cc=kvmarm@lists.cs.columbia.edu \ --cc=linux-acpi@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=marc.zyngier@arm.com \ --cc=rostedt@goodmis.org \ --cc=shiju.jose@huawei.com \ --cc=wangxiongfeng2@huawei.com \ --cc=will.deacon@arm.com \ --cc=wuquanming@huawei.com \ --cc=xiexiuqi@huawei.com \ --cc=zhengqiang10@huawei.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.