From: Bin Meng <bmeng.cn@gmail.com> To: David Laight <David.Laight@aculab.com> Cc: Matteo Croce <mcroce@linux.microsoft.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atish.patra@wdc.com>, Emil Renner Berthing <kernel@esmil.dk>, Akira Tsukamoto <akira.tsukamoto@gmail.com>, Drew Fustini <drew@beagleboard.org> Subject: Re: [PATCH 1/3] riscv: optimized memcpy Date: Tue, 15 Jun 2021 21:08:50 +0800 [thread overview] Message-ID: <CAEUhbmV+Vi0Ssyzq1B2RTkbjMpE21xjdj2MSKdLydgW6WuCKtA@mail.gmail.com> (raw) In-Reply-To: <6cff2a895db94e6fadd4ddffb8906a73@AcuMS.aculab.com> On Tue, Jun 15, 2021 at 4:57 PM David Laight <David.Laight@aculab.com> wrote: > > From: Matteo Croce > > Sent: 15 June 2021 03:38 > > > > Write a C version of memcpy() which uses the biggest data size allowed, > > without generating unaligned accesses. > > I'm surprised that the C loop: > > > + for (; count >= bytes_long; count -= bytes_long) > > + *d.ulong++ = *s.ulong++; > > ends up being faster than the ASM 'read lots' - 'write lots' loop. I believe that's because the assembly version has some unaligned access cases, which end up being trap-n-emulated in the OpenSBI firmware, and that is a big overhead. > > Especially since there was an earlier patch to convert > copy_to/from_user() to use the ASM 'read lots' - 'write lots' loop > instead of a tight single register copy loop. > > I'd also guess that the performance needs to be measured on > different classes of riscv cpu. > > A simple cpu will behave differently to one that can execute > multiple instructions per clock. > Any form of 'out of order' execution also changes things. > The other big change is whether the cpu can to a memory > read and write in the same clock. > > I'd guess that riscv exist with some/all of those features. Regards, Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: David Laight <David.Laight@aculab.com> Cc: Matteo Croce <mcroce@linux.microsoft.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atish.patra@wdc.com>, Emil Renner Berthing <kernel@esmil.dk>, Akira Tsukamoto <akira.tsukamoto@gmail.com>, Drew Fustini <drew@beagleboard.org> Subject: Re: [PATCH 1/3] riscv: optimized memcpy Date: Tue, 15 Jun 2021 21:08:50 +0800 [thread overview] Message-ID: <CAEUhbmV+Vi0Ssyzq1B2RTkbjMpE21xjdj2MSKdLydgW6WuCKtA@mail.gmail.com> (raw) In-Reply-To: <6cff2a895db94e6fadd4ddffb8906a73@AcuMS.aculab.com> On Tue, Jun 15, 2021 at 4:57 PM David Laight <David.Laight@aculab.com> wrote: > > From: Matteo Croce > > Sent: 15 June 2021 03:38 > > > > Write a C version of memcpy() which uses the biggest data size allowed, > > without generating unaligned accesses. > > I'm surprised that the C loop: > > > + for (; count >= bytes_long; count -= bytes_long) > > + *d.ulong++ = *s.ulong++; > > ends up being faster than the ASM 'read lots' - 'write lots' loop. I believe that's because the assembly version has some unaligned access cases, which end up being trap-n-emulated in the OpenSBI firmware, and that is a big overhead. > > Especially since there was an earlier patch to convert > copy_to/from_user() to use the ASM 'read lots' - 'write lots' loop > instead of a tight single register copy loop. > > I'd also guess that the performance needs to be measured on > different classes of riscv cpu. > > A simple cpu will behave differently to one that can execute > multiple instructions per clock. > Any form of 'out of order' execution also changes things. > The other big change is whether the cpu can to a memory > read and write in the same clock. > > I'd guess that riscv exist with some/all of those features. Regards, Bin _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-06-15 13:09 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-15 2:38 [PATCH 0/3] riscv: optimized mem* functions Matteo Croce 2021-06-15 2:38 ` Matteo Croce 2021-06-15 2:38 ` [PATCH 1/3] riscv: optimized memcpy Matteo Croce 2021-06-15 2:38 ` Matteo Croce 2021-06-15 8:57 ` David Laight 2021-06-15 8:57 ` David Laight 2021-06-15 13:08 ` Bin Meng [this message] 2021-06-15 13:08 ` Bin Meng 2021-06-15 13:18 ` David Laight 2021-06-15 13:18 ` David Laight 2021-06-15 13:28 ` Bin Meng 2021-06-15 13:28 ` Bin Meng 2021-06-15 16:12 ` Emil Renner Berthing 2021-06-15 16:12 ` Emil Renner Berthing 2021-06-16 0:33 ` Bin Meng 2021-06-16 0:33 ` Bin Meng 2021-06-16 2:01 ` Matteo Croce 2021-06-16 2:01 ` Matteo Croce 2021-06-16 8:24 ` David Laight 2021-06-16 8:24 ` David Laight 2021-06-16 10:48 ` Akira Tsukamoto 2021-06-16 10:48 ` Akira Tsukamoto 2021-06-16 19:06 ` Matteo Croce 2021-06-16 19:06 ` Matteo Croce 2021-06-15 13:44 ` Matteo Croce 2021-06-15 13:44 ` Matteo Croce 2021-06-16 11:46 ` Guo Ren 2021-06-16 11:46 ` Guo Ren 2021-06-16 18:52 ` Matteo Croce 2021-06-16 18:52 ` Matteo Croce 2021-06-17 21:30 ` David Laight 2021-06-17 21:30 ` David Laight 2021-06-17 21:48 ` Matteo Croce 2021-06-17 21:48 ` Matteo Croce 2021-06-18 0:32 ` Matteo Croce 2021-06-18 0:32 ` Matteo Croce 2021-06-18 1:05 ` Matteo Croce 2021-06-18 1:05 ` Matteo Croce 2021-06-18 8:32 ` David Laight 2021-06-18 8:32 ` David Laight 2021-06-15 2:38 ` [PATCH 2/3] riscv: optimized memmove Matteo Croce 2021-06-15 2:38 ` Matteo Croce 2021-06-15 2:38 ` [PATCH 3/3] riscv: optimized memset Matteo Croce 2021-06-15 2:38 ` Matteo Croce 2021-06-15 2:43 ` [PATCH 0/3] riscv: optimized mem* functions Bin Meng 2021-06-15 2:43 ` Bin Meng 2024-01-28 11:10 [PATCH 0/3] riscv: optimize memcpy/memmove/memset Jisheng Zhang 2024-01-28 11:10 ` [PATCH 1/3] riscv: optimized memcpy Jisheng Zhang 2024-01-28 11:10 ` Jisheng Zhang 2024-01-28 12:35 ` David Laight 2024-01-28 12:35 ` David Laight 2024-01-30 12:11 ` Nick Kossifidis 2024-01-30 12:11 ` Nick Kossifidis 2024-01-30 22:44 ` kernel test robot 2024-01-31 0:19 ` kernel test robot 2024-01-31 0:19 ` kernel test robot
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=CAEUhbmV+Vi0Ssyzq1B2RTkbjMpE21xjdj2MSKdLydgW6WuCKtA@mail.gmail.com \ --to=bmeng.cn@gmail.com \ --cc=David.Laight@aculab.com \ --cc=akira.tsukamoto@gmail.com \ --cc=aou@eecs.berkeley.edu \ --cc=atish.patra@wdc.com \ --cc=drew@beagleboard.org \ --cc=kernel@esmil.dk \ --cc=linux-arch@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mcroce@linux.microsoft.com \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.