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From: David Laight <David.Laight@ACULAB.COM>
To: 'Jisheng Zhang' <jszhang@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Matteo Croce <mcroce@microsoft.com>,
	kernel test robot <lkp@intel.com>
Subject: RE: [PATCH 1/3] riscv: optimized memcpy
Date: Sun, 28 Jan 2024 12:35:53 +0000	[thread overview]
Message-ID: <dc1f54f90642401ca6135c75e399c06d@AcuMS.aculab.com> (raw)
In-Reply-To: <20240128111013.2450-2-jszhang@kernel.org>

From: Jisheng Zhang
> Sent: 28 January 2024 11:10
> 
> From: Matteo Croce <mcroce@microsoft.com>
> 
> Write a C version of memcpy() which uses the biggest data size allowed,
> without generating unaligned accesses.
> 
> The procedure is made of three steps:
> First copy data one byte at time until the destination buffer is aligned
> to a long boundary.
> Then copy the data one long at time shifting the current and the next u8
> to compose a long at every cycle.
> Finally, copy the remainder one byte at time.
> 
> On a BeagleV, the TCP RX throughput increased by 45%:
...
> +static void __memcpy_aligned(unsigned long *dest, const unsigned long *src, size_t count)
> +{

You should be able to remove an instruction from the loop by using:
	const unsigned long *src_lim = src + count;
	for (; src < src_lim; ) {

> +	for (; count > 0; count -= BYTES_LONG * 8) {
> +		register unsigned long d0, d1, d2, d3, d4, d5, d6, d7;

register is completely ignored and pointless.
(More annoyingly auto is also ignored.)

> +		d0 = src[0];
> +		d1 = src[1];
> +		d2 = src[2];
> +		d3 = src[3];
> +		d4 = src[4];
> +		d5 = src[5];
> +		d6 = src[6];
> +		d7 = src[7];
> +		dest[0] = d0;
> +		dest[1] = d1;
> +		dest[2] = d2;
> +		dest[3] = d3;
> +		dest[4] = d4;
> +		dest[5] = d5;
> +		dest[6] = d6;
> +		dest[7] = d7;
> +		dest += 8;
> +		src += 8;

There two lines belong in the for (...) statement.

> +	}
> +}

If you __always_inline the function you can pass &src and &dest
and use the updated pointers following the loop.

I don't believe that risc-v supports 'reg+reg+(imm5<<3)' addressing
(although there is probably space in the instruction for it.
Actually 'reg+reg' addressing could be supported for loads but
not stores - since the latter would require 3 registers be read.

We use the Nios-II cpu in some fpgas. Intel are removing support
in favour of Risc-V - we are thinking of re-implementing Nios-II
ourselves!
I don't think they understand what the cpu get used for!

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)


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WARNING: multiple messages have this Message-ID (diff)
From: David Laight <David.Laight@ACULAB.COM>
To: 'Jisheng Zhang' <jszhang@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Matteo Croce <mcroce@microsoft.com>,
	kernel test robot <lkp@intel.com>
Subject: RE: [PATCH 1/3] riscv: optimized memcpy
Date: Sun, 28 Jan 2024 12:35:53 +0000	[thread overview]
Message-ID: <dc1f54f90642401ca6135c75e399c06d@AcuMS.aculab.com> (raw)
In-Reply-To: <20240128111013.2450-2-jszhang@kernel.org>

From: Jisheng Zhang
> Sent: 28 January 2024 11:10
> 
> From: Matteo Croce <mcroce@microsoft.com>
> 
> Write a C version of memcpy() which uses the biggest data size allowed,
> without generating unaligned accesses.
> 
> The procedure is made of three steps:
> First copy data one byte at time until the destination buffer is aligned
> to a long boundary.
> Then copy the data one long at time shifting the current and the next u8
> to compose a long at every cycle.
> Finally, copy the remainder one byte at time.
> 
> On a BeagleV, the TCP RX throughput increased by 45%:
...
> +static void __memcpy_aligned(unsigned long *dest, const unsigned long *src, size_t count)
> +{

You should be able to remove an instruction from the loop by using:
	const unsigned long *src_lim = src + count;
	for (; src < src_lim; ) {

> +	for (; count > 0; count -= BYTES_LONG * 8) {
> +		register unsigned long d0, d1, d2, d3, d4, d5, d6, d7;

register is completely ignored and pointless.
(More annoyingly auto is also ignored.)

> +		d0 = src[0];
> +		d1 = src[1];
> +		d2 = src[2];
> +		d3 = src[3];
> +		d4 = src[4];
> +		d5 = src[5];
> +		d6 = src[6];
> +		d7 = src[7];
> +		dest[0] = d0;
> +		dest[1] = d1;
> +		dest[2] = d2;
> +		dest[3] = d3;
> +		dest[4] = d4;
> +		dest[5] = d5;
> +		dest[6] = d6;
> +		dest[7] = d7;
> +		dest += 8;
> +		src += 8;

There two lines belong in the for (...) statement.

> +	}
> +}

If you __always_inline the function you can pass &src and &dest
and use the updated pointers following the loop.

I don't believe that risc-v supports 'reg+reg+(imm5<<3)' addressing
(although there is probably space in the instruction for it.
Actually 'reg+reg' addressing could be supported for loads but
not stores - since the latter would require 3 registers be read.

We use the Nios-II cpu in some fpgas. Intel are removing support
in favour of Risc-V - we are thinking of re-implementing Nios-II
ourselves!
I don't think they understand what the cpu get used for!

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)


  reply	other threads:[~2024-01-28 12:36 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-28 11:10 [PATCH 0/3] riscv: optimize memcpy/memmove/memset Jisheng Zhang
2024-01-28 11:10 ` Jisheng Zhang
2024-01-28 11:10 ` [PATCH 1/3] riscv: optimized memcpy Jisheng Zhang
2024-01-28 11:10   ` Jisheng Zhang
2024-01-28 12:35   ` David Laight [this message]
2024-01-28 12:35     ` David Laight
2024-01-30 12:11   ` Nick Kossifidis
2024-01-30 12:11     ` Nick Kossifidis
2024-01-30 22:44   ` kernel test robot
2024-01-31  0:19   ` kernel test robot
2024-01-31  0:19   ` kernel test robot
2024-01-28 11:10 ` [PATCH 2/3] riscv: optimized memmove Jisheng Zhang
2024-01-28 11:10   ` Jisheng Zhang
2024-01-28 12:47   ` David Laight
2024-01-28 12:47     ` David Laight
2024-01-30 11:30     ` Jisheng Zhang
2024-01-30 11:30       ` Jisheng Zhang
2024-01-30 11:51       ` David Laight
2024-01-30 11:51         ` David Laight
2024-01-30 11:39   ` Nick Kossifidis
2024-01-30 11:39     ` Nick Kossifidis
2024-01-30 13:12     ` Jisheng Zhang
2024-01-30 13:12       ` Jisheng Zhang
2024-01-30 16:52       ` Nick Kossifidis
2024-01-30 16:52         ` Nick Kossifidis
2024-01-31  5:25         ` Jisheng Zhang
2024-01-31  5:25           ` Jisheng Zhang
2024-01-31  9:13           ` Nick Kossifidis
2024-01-31  9:13             ` Nick Kossifidis
2024-01-28 11:10 ` [PATCH 3/3] riscv: optimized memset Jisheng Zhang
2024-01-28 11:10   ` Jisheng Zhang
2024-01-30 12:07   ` Nick Kossifidis
2024-01-30 12:07     ` Nick Kossifidis
2024-01-30 13:25     ` Jisheng Zhang
2024-01-30 13:25       ` Jisheng Zhang
2024-02-01 23:04     ` David Laight
2024-02-01 23:04       ` David Laight
2024-01-29 18:16 ` [PATCH 0/3] riscv: optimize memcpy/memmove/memset Conor Dooley
2024-01-29 18:16   ` Conor Dooley
2024-01-30  2:28   ` Jisheng Zhang
2024-01-30  2:28     ` Jisheng Zhang
  -- strict thread matches above, loose matches on Subject: below --
2021-06-15  2:38 [PATCH 0/3] riscv: optimized mem* functions Matteo Croce
2021-06-15  2:38 ` [PATCH 1/3] riscv: optimized memcpy Matteo Croce
2021-06-15  2:38   ` Matteo Croce
2021-06-15  8:57   ` David Laight
2021-06-15  8:57     ` David Laight
2021-06-15 13:08     ` Bin Meng
2021-06-15 13:08       ` Bin Meng
2021-06-15 13:18       ` David Laight
2021-06-15 13:18         ` David Laight
2021-06-15 13:28         ` Bin Meng
2021-06-15 13:28           ` Bin Meng
2021-06-15 16:12           ` Emil Renner Berthing
2021-06-15 16:12             ` Emil Renner Berthing
2021-06-16  0:33             ` Bin Meng
2021-06-16  0:33               ` Bin Meng
2021-06-16  2:01               ` Matteo Croce
2021-06-16  2:01                 ` Matteo Croce
2021-06-16  8:24                 ` David Laight
2021-06-16  8:24                   ` David Laight
2021-06-16 10:48                   ` Akira Tsukamoto
2021-06-16 10:48                     ` Akira Tsukamoto
2021-06-16 19:06                   ` Matteo Croce
2021-06-16 19:06                     ` Matteo Croce
2021-06-15 13:44         ` Matteo Croce
2021-06-15 13:44           ` Matteo Croce
2021-06-16 11:46   ` Guo Ren
2021-06-16 11:46     ` Guo Ren
2021-06-16 18:52     ` Matteo Croce
2021-06-16 18:52       ` Matteo Croce
2021-06-17 21:30       ` David Laight
2021-06-17 21:30         ` David Laight
2021-06-17 21:48         ` Matteo Croce
2021-06-17 21:48           ` Matteo Croce
2021-06-18  0:32           ` Matteo Croce
2021-06-18  0:32             ` Matteo Croce
2021-06-18  1:05             ` Matteo Croce
2021-06-18  1:05               ` Matteo Croce
2021-06-18  8:32               ` David Laight
2021-06-18  8:32                 ` David Laight

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