From: Alistair Francis <alistair23@gmail.com>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Richard Henderson <richard.henderson@linaro.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Date: Wed, 23 Jan 2019 13:22:19 -0800 [thread overview]
Message-ID: <CAKmqyKM8NKY5uzYezWbR5cxfpMpy=VFof3BrOhRaDZsbFHLrig@mail.gmail.com> (raw)
In-Reply-To: <66fd9695-c511-b068-7cf1-b529d9f44d9d@mail.uni-paderborn.de>
On Wed, Jan 23, 2019 at 1:15 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
>
> On 1/22/19 10:38 PM, Richard Henderson wrote:
> > On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >> Hi,
> >>
> >> this patchset converts the RISC-V decoder to decodetree in four major steps:
> >>
> >> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >> Many of the gen_* functions are called by the decode functions for 16-bit
> >> and 32-bit functions. If we move translation code from the gen_*
> >> functions to the generated trans_* functions of decode-tree, we get a lot of
> >> duplication. Therefore, we mostly generate calls to the old gen_* function
> >> which are properly replaced after step 2).
> >>
> >> Each of the trans_ functions are grouped into files corresponding to their
> >> ISA extension, e.g. addi which is in RV32I is translated in the file
> >> 'trans_rvi.inc.c'.
> >>
> >> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> >> we convert the arguments in the 16 bit trans_ function to the arguments of
> >> the corresponding 32 bit instruction and call the 32 bit trans_ function.
> >>
> >> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >> this move all manual translation code into the trans_* instructions of
> >> decode tree, such that we can remove the old decode_* functions.
> >>
> >> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> >> by Richard. [Patch 31-35]
> >>
> >> full tree available at
> >> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> >>
> >> Cheers,
> >> Bastian
> >>
> >> v4 -> v5:
> >> - fixed rebase error
> >> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> >> - removed extra sign extension of sraiw
> >> - removed rs2 == 0 special cases in sraw/srlw
> > All looks good to me now. Thanks for persevering.
>
>
> Thanks for your great reviews. I'll do a final respin to fix the funky
> indentations. Alistair do you want to pick up the series?
Thanks, the series looks good :)
Palmer is in charge of pull requests for RISC-V QEMU. So it will have
to go through him.
Alistair
>
> Cheers,
>
> Bastian
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Richard Henderson <richard.henderson@linaro.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Date: Wed, 23 Jan 2019 13:22:19 -0800 [thread overview]
Message-ID: <CAKmqyKM8NKY5uzYezWbR5cxfpMpy=VFof3BrOhRaDZsbFHLrig@mail.gmail.com> (raw)
In-Reply-To: <66fd9695-c511-b068-7cf1-b529d9f44d9d@mail.uni-paderborn.de>
On Wed, Jan 23, 2019 at 1:15 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
>
> On 1/22/19 10:38 PM, Richard Henderson wrote:
> > On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >> Hi,
> >>
> >> this patchset converts the RISC-V decoder to decodetree in four major steps:
> >>
> >> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >> Many of the gen_* functions are called by the decode functions for 16-bit
> >> and 32-bit functions. If we move translation code from the gen_*
> >> functions to the generated trans_* functions of decode-tree, we get a lot of
> >> duplication. Therefore, we mostly generate calls to the old gen_* function
> >> which are properly replaced after step 2).
> >>
> >> Each of the trans_ functions are grouped into files corresponding to their
> >> ISA extension, e.g. addi which is in RV32I is translated in the file
> >> 'trans_rvi.inc.c'.
> >>
> >> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> >> we convert the arguments in the 16 bit trans_ function to the arguments of
> >> the corresponding 32 bit instruction and call the 32 bit trans_ function.
> >>
> >> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >> this move all manual translation code into the trans_* instructions of
> >> decode tree, such that we can remove the old decode_* functions.
> >>
> >> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> >> by Richard. [Patch 31-35]
> >>
> >> full tree available at
> >> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> >>
> >> Cheers,
> >> Bastian
> >>
> >> v4 -> v5:
> >> - fixed rebase error
> >> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> >> - removed extra sign extension of sraiw
> >> - removed rs2 == 0 special cases in sraw/srlw
> > All looks good to me now. Thanks for persevering.
>
>
> Thanks for your great reviews. I'll do a final respin to fix the funky
> indentations. Alistair do you want to pick up the series?
Thanks, the series looks good :)
Palmer is in charge of pull requests for RISC-V QEMU. So it will have
to go through him.
Alistair
>
> Cheers,
>
> Bastian
>
>
next prev parent reply other threads:[~2019-01-23 21:22 UTC|newest]
Thread overview: 164+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-22 9:28 [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:03 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:03 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:38 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:38 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:43 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:43 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:00 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:00 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:10 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:10 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 1:00 ` [Qemu-devel] " Alistair Francis
2019-01-23 1:00 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:32 ` [Qemu-devel] " Richard Henderson
2019-01-22 21:32 ` [Qemu-riscv] " Richard Henderson
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:36 ` [Qemu-devel] " Richard Henderson
2019-01-22 21:36 ` [Qemu-riscv] " Richard Henderson
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:38 ` [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Richard Henderson
2019-01-22 21:38 ` [Qemu-riscv] " Richard Henderson
2019-01-23 9:15 ` [Qemu-devel] " Bastian Koppelmann
2019-01-23 9:15 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 21:22 ` Alistair Francis [this message]
2019-01-23 21:22 ` Alistair Francis
2019-01-25 23:54 ` Palmer Dabbelt
2019-01-25 23:54 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-26 8:51 ` [Qemu-devel] " Bastian Koppelmann
2019-01-26 8:51 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-29 19:22 ` Palmer Dabbelt
2019-01-29 19:22 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-29 21:13 ` Alistair Francis
2019-01-29 21:13 ` [Qemu-riscv] " Alistair Francis
2019-01-30 9:08 ` Bastian Koppelmann
2019-01-30 9:08 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-30 18:47 ` Palmer Dabbelt
2019-01-30 18:47 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-31 18:06 ` no-reply
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