From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
Date: Wed, 31 Mar 2021 11:51:41 -0400 [thread overview]
Message-ID: <CAKmqyKMCTFVs9dhFza+GnTM-EqRngPmTEfWbuX=BaVMGAEpbCg@mail.gmail.com> (raw)
In-Reply-To: <20210331021825.537484-2-bmeng.cn@gmail.com>
On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The following check:
>
> if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> return -RISCV_EXCP_ILLEGAL_INST;
> }
>
> is redundant in fflags/frm/fcsr read/write routines, as the check was
> already done in fs().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/csr.c | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 2bad396f64..7c24318f75 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -193,11 +193,6 @@ static int pmp(CPURISCVState *env, int csrno)
> /* User Floating-Point CSRs */
> static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = riscv_cpu_get_fflags(env);
> return 0;
> }
> @@ -205,9 +200,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> @@ -216,11 +208,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>
> static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = env->frm;
> return 0;
> }
> @@ -228,9 +215,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
> static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
> @@ -239,11 +223,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>
> static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> if (vs(env, csrno) >= 0) {
> @@ -256,9 +235,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> --
> 2.25.1
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
Date: Wed, 31 Mar 2021 11:51:41 -0400 [thread overview]
Message-ID: <CAKmqyKMCTFVs9dhFza+GnTM-EqRngPmTEfWbuX=BaVMGAEpbCg@mail.gmail.com> (raw)
In-Reply-To: <20210331021825.537484-2-bmeng.cn@gmail.com>
On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The following check:
>
> if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> return -RISCV_EXCP_ILLEGAL_INST;
> }
>
> is redundant in fflags/frm/fcsr read/write routines, as the check was
> already done in fs().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/csr.c | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 2bad396f64..7c24318f75 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -193,11 +193,6 @@ static int pmp(CPURISCVState *env, int csrno)
> /* User Floating-Point CSRs */
> static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = riscv_cpu_get_fflags(env);
> return 0;
> }
> @@ -205,9 +200,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> @@ -216,11 +208,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>
> static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = env->frm;
> return 0;
> }
> @@ -228,9 +215,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
> static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
> @@ -239,11 +223,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>
> static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> if (vs(env, csrno) >= 0) {
> @@ -256,9 +235,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return -RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-03-31 15:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 2:18 [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Bin Meng
2021-03-31 2:18 ` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng
2021-03-31 15:51 ` Alistair Francis [this message]
2021-03-31 15:51 ` Alistair Francis
2021-06-15 9:07 ` Bin Meng
2021-06-15 9:07 ` Bin Meng
2021-06-15 10:42 ` Alistair Francis
2021-06-15 10:42 ` Alistair Francis
2021-03-31 15:03 ` [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Alistair Francis
2021-03-31 15:03 ` Alistair Francis
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