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From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64
Date: Wed, 31 Mar 2021 11:03:48 -0400	[thread overview]
Message-ID: <CAKmqyKNo9UN-sm7y_ooMrm833NVJ6=5v2OwWebvL_ibGe00=3Q@mail.gmail.com> (raw)
In-Reply-To: <20210331021825.537484-1-bmeng.cn@gmail.com>

On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Thanks for the patch.

There is already a patch on list to fix this: "target/riscv: Fix
32-bit HS mode access permissions"

Alistair

> ---
>
>  target/riscv/csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d2585395bf..2bad396f64 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -177,7 +177,7 @@ static int hmode(CPURISCVState *env, int csrno)
>  static int hmode32(CPURISCVState *env, int csrno)
>  {
>      if (!riscv_cpu_is_32bit(env)) {
> -        return 0;
> +        return -RISCV_EXCP_ILLEGAL_INST;
>      }
>
>      return hmode(env, csrno);
> --
> 2.25.1
>
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64
Date: Wed, 31 Mar 2021 11:03:48 -0400	[thread overview]
Message-ID: <CAKmqyKNo9UN-sm7y_ooMrm833NVJ6=5v2OwWebvL_ibGe00=3Q@mail.gmail.com> (raw)
In-Reply-To: <20210331021825.537484-1-bmeng.cn@gmail.com>

On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Thanks for the patch.

There is already a patch on list to fix this: "target/riscv: Fix
32-bit HS mode access permissions"

Alistair

> ---
>
>  target/riscv/csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d2585395bf..2bad396f64 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -177,7 +177,7 @@ static int hmode(CPURISCVState *env, int csrno)
>  static int hmode32(CPURISCVState *env, int csrno)
>  {
>      if (!riscv_cpu_is_32bit(env)) {
> -        return 0;
> +        return -RISCV_EXCP_ILLEGAL_INST;
>      }
>
>      return hmode(env, csrno);
> --
> 2.25.1
>
>


  parent reply	other threads:[~2021-03-31 15:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-31  2:18 [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Bin Meng
2021-03-31  2:18 ` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng
2021-03-31 15:51   ` Alistair Francis
2021-03-31 15:51     ` Alistair Francis
2021-06-15  9:07     ` Bin Meng
2021-06-15  9:07       ` Bin Meng
2021-06-15 10:42       ` Alistair Francis
2021-06-15 10:42         ` Alistair Francis
2021-03-31 15:03 ` Alistair Francis [this message]
2021-03-31 15:03   ` [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Alistair Francis

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