From: Mark Rutland <mark.rutland@arm.com> To: Marc Zyngier <maz@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon <will@kernel.org>, Hector Martin <marcan@marcan.st>, Sven Peter <sven@svenpeter.dev>, Alyssa Rosenzweig <alyssa@rosenzweig.io>, Rob Herring <robh+dt@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Dougall <dougallj@gmail.com>, kernel-team@android.com Subject: Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores Date: Wed, 1 Dec 2021 16:08:13 +0000 [thread overview] Message-ID: <Yaed7VAlwwCBcP13@FVFF77S0Q05N> (raw) In-Reply-To: <20211201134909.390490-4-maz@kernel.org> On Wed, Dec 01, 2021 at 01:49:04PM +0000, Marc Zyngier wrote: > In order to be able to tell the core IRQ code about the affinity > of the PMU interrupt in later patches, compute the cpumasks of the > P and E cores at boot time. > > This relies on the affinity scheme used by the vendor, which seems > to work for the couple of SoCs that are out in the wild. ... but may change at any arbitrary point in future? Can we please put the affinity in the DT, like we do for other SoCs and devices? I don't think we should treat this HW specially in this regard; we certaintly don't want other folk hard-coding system topology in their irqchip driver, and it should be possible to do something like the ppi-partitions binding, no? Thanks, Mark. > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > drivers/irqchip/irq-apple-aic.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c > index 3759dc36cc8f..30ca80ccda8b 100644 > --- a/drivers/irqchip/irq-apple-aic.c > +++ b/drivers/irqchip/irq-apple-aic.c > @@ -177,6 +177,8 @@ struct aic_irq_chip { > void __iomem *base; > struct irq_domain *hw_domain; > struct irq_domain *ipi_domain; > + struct cpumask ecore_mask; > + struct cpumask pcore_mask; > int nr_hw; > int ipi_hwirq; > }; > @@ -200,6 +202,11 @@ static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val) > writel_relaxed(val, ic->base + reg); > } > > +static bool __is_pcore(u64 mpidr) > +{ > + return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1; > +} > + > /* > * IRQ irqchip > */ > @@ -833,6 +840,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p > return -ENODEV; > } > > + for_each_possible_cpu(i) { > + if (__is_pcore(cpu_logical_map(i))) > + cpumask_set_cpu(i, &irqc->pcore_mask); > + else > + cpumask_set_cpu(i, &irqc->ecore_mask); > + } > + > set_handle_irq(aic_handle_irq); > set_handle_fiq(aic_handle_fiq); > > -- > 2.30.2 >
WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com> To: Marc Zyngier <maz@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon <will@kernel.org>, Hector Martin <marcan@marcan.st>, Sven Peter <sven@svenpeter.dev>, Alyssa Rosenzweig <alyssa@rosenzweig.io>, Rob Herring <robh+dt@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Dougall <dougallj@gmail.com>, kernel-team@android.com Subject: Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores Date: Wed, 1 Dec 2021 16:08:13 +0000 [thread overview] Message-ID: <Yaed7VAlwwCBcP13@FVFF77S0Q05N> (raw) In-Reply-To: <20211201134909.390490-4-maz@kernel.org> On Wed, Dec 01, 2021 at 01:49:04PM +0000, Marc Zyngier wrote: > In order to be able to tell the core IRQ code about the affinity > of the PMU interrupt in later patches, compute the cpumasks of the > P and E cores at boot time. > > This relies on the affinity scheme used by the vendor, which seems > to work for the couple of SoCs that are out in the wild. ... but may change at any arbitrary point in future? Can we please put the affinity in the DT, like we do for other SoCs and devices? I don't think we should treat this HW specially in this regard; we certaintly don't want other folk hard-coding system topology in their irqchip driver, and it should be possible to do something like the ppi-partitions binding, no? Thanks, Mark. > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > drivers/irqchip/irq-apple-aic.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c > index 3759dc36cc8f..30ca80ccda8b 100644 > --- a/drivers/irqchip/irq-apple-aic.c > +++ b/drivers/irqchip/irq-apple-aic.c > @@ -177,6 +177,8 @@ struct aic_irq_chip { > void __iomem *base; > struct irq_domain *hw_domain; > struct irq_domain *ipi_domain; > + struct cpumask ecore_mask; > + struct cpumask pcore_mask; > int nr_hw; > int ipi_hwirq; > }; > @@ -200,6 +202,11 @@ static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val) > writel_relaxed(val, ic->base + reg); > } > > +static bool __is_pcore(u64 mpidr) > +{ > + return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1; > +} > + > /* > * IRQ irqchip > */ > @@ -833,6 +840,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p > return -ENODEV; > } > > + for_each_possible_cpu(i) { > + if (__is_pcore(cpu_logical_map(i))) > + cpumask_set_cpu(i, &irqc->pcore_mask); > + else > + cpumask_set_cpu(i, &irqc->ecore_mask); > + } > + > set_handle_irq(aic_handle_irq); > set_handle_fiq(aic_handle_fiq); > > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-01 16:08 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-01 13:49 [PATCH v2 0/8] drivers/perf: CPU PMU driver for Apple M1 Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-01 13:49 ` [PATCH v2 1/8] dt-bindings: arm-pmu: Document Apple PMU compatible strings Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-12 7:27 ` Hector Martin 2021-12-12 7:27 ` Hector Martin 2021-12-01 13:49 ` [PATCH v2 2/8] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Marc Zyngier 2021-12-01 13:49 ` [PATCH v2 2/8] dt-bindings: apple, aic: " Marc Zyngier 2021-12-12 7:26 ` [PATCH v2 2/8] dt-bindings: apple,aic: " Hector Martin 2021-12-12 7:26 ` Hector Martin 2021-12-01 13:49 ` [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-01 16:08 ` Mark Rutland [this message] 2021-12-01 16:08 ` Mark Rutland 2021-12-03 16:32 ` Marc Zyngier 2021-12-03 16:32 ` Marc Zyngier 2021-12-12 7:22 ` Hector Martin 2021-12-12 7:22 ` Hector Martin 2021-12-12 7:30 ` Hector Martin 2021-12-12 7:30 ` Hector Martin 2021-12-13 14:43 ` Marc Zyngier 2021-12-13 14:43 ` Marc Zyngier 2021-12-01 13:49 ` [PATCH v2 4/8] irqchip/apple-aic: Wire PMU interrupts Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-12 7:25 ` Hector Martin 2021-12-12 7:25 ` Hector Martin 2021-12-01 13:49 ` [PATCH v2 5/8] irqchip/apple-aic: Move PMU-specific registers to their own include file Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-12 7:23 ` Hector Martin 2021-12-12 7:23 ` Hector Martin 2021-12-01 13:49 ` [PATCH v2 6/8] arm64: apple: t8301: Add PMU nodes Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-12 7:26 ` Hector Martin 2021-12-12 7:26 ` Hector Martin 2021-12-01 13:49 ` [PATCH v2 7/8] drivers/perf: arm_pmu: Handle 47 bit counters Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-12 7:26 ` Hector Martin 2021-12-12 7:26 ` Hector Martin 2021-12-01 13:49 ` [PATCH v2 8/8] drivers/perf: Add Apple icestorm/firestorm CPU PMU driver Marc Zyngier 2021-12-01 13:49 ` Marc Zyngier 2021-12-01 16:58 ` Mark Rutland 2021-12-01 16:58 ` Mark Rutland 2021-12-01 17:56 ` Alyssa Rosenzweig 2021-12-01 17:56 ` Alyssa Rosenzweig 2021-12-02 15:39 ` Marc Zyngier 2021-12-02 15:39 ` Marc Zyngier 2021-12-02 16:14 ` Mark Rutland 2021-12-02 16:14 ` Mark Rutland 2021-12-03 11:22 ` Marc Zyngier 2021-12-03 11:22 ` Marc Zyngier 2021-12-03 12:04 ` Mark Rutland 2021-12-03 12:04 ` Mark Rutland 2021-12-03 16:22 ` Marc Zyngier 2021-12-03 16:22 ` Marc Zyngier
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