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From: Sia Jee Heng <jee.heng.sia@intel.com>
To: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com
Cc: andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 15/15] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Date: Mon, 12 Oct 2020 12:22:00 +0800	[thread overview]
Message-ID: <20201012042200.29787-16-jee.heng.sia@intel.com> (raw)
In-Reply-To: <20201012042200.29787-1-jee.heng.sia@intel.com>

Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.

Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++++++
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h          | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index d4fca3ffe67f..bd56e21663c3 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
 #include <linux/device.h>
 #include <linux/dmaengine.h>
 #include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
@@ -1407,6 +1408,13 @@ static int dw_probe(struct platform_device *pdev)
 	dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
 	dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
 
+	/*
+	 * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+	 * supported blocks is 1024. Device register width is 4 bytes.
+	 * Therefore, set constraint to 1024 * 4.
+	 */
+	dw->dma.dev->dma_parms = &dw->dma_parms;
+	dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
 	platform_set_drvdata(pdev, chip);
 
 	pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index f64e8d33b127..67669049cead 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
 struct dw_axi_dma {
 	struct dma_device	dma;
 	struct dw_axi_dma_hcfg	*hdata;
+	struct device_dma_parameters	dma_parms;
 
 	/* channels */
 	struct axi_dma_chan	*chan;
-- 
2.18.0


  parent reply	other threads:[~2020-10-12  4:39 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-12  4:21 [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-10-12  4:21 ` [PATCH 01/15] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-10-12  4:21 ` [PATCH 02/15] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2020-10-12  4:21 ` [PATCH 03/15] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2020-10-12  4:21 ` [PATCH 04/15] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2020-10-12  4:21 ` [PATCH 05/15] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2020-10-12  4:21 ` [PATCH 06/15] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2020-10-12  4:21 ` [PATCH 07/15] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2020-10-12  4:21 ` [PATCH 08/15] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2020-10-12  4:21 ` [PATCH 09/15] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2020-10-12  4:21 ` [PATCH 10/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2020-10-12  4:21 ` [PATCH 11/15] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2020-10-12  4:21 ` [PATCH 12/15] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
2020-10-12  4:21 ` [PATCH 13/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2020-10-12  4:21 ` [PATCH 14/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
2020-10-12  4:22 ` Sia Jee Heng [this message]
2020-10-12 13:59 ` [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Andy Shevchenko
2020-10-13  5:49   ` Sia, Jee Heng
2020-10-13  7:01     ` Vinod Koul
2020-10-13  7:12       ` Sia, Jee Heng
2020-10-13  7:16         ` Vinod Koul
2020-10-16 14:51 ` Eugeniy Paltsev
2020-10-19  1:22   ` Sia, Jee Heng
2020-10-19 11:39     ` andriy.shevchenko
2020-10-21  1:54       ` Sia, Jee Heng

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