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From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Lucas De Marchi" <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce DG1
Date: Thu, 21 May 2020 01:26:35 -0000	[thread overview]
Message-ID: <159002439538.4440.14868821936965432658@emeril.freedesktop.org> (raw)
In-Reply-To: <20200521003803.18936-1-lucas.demarchi@intel.com>

== Series Details ==

Series: Introduce DG1
URL   : https://patchwork.freedesktop.org/series/77496/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17740
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17740/index.html

Known issues
------------

  Here are the changes found in Patchwork_17740 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - {fi-tgl-dsi}:       [INCOMPLETE][1] ([i915#1803]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17740/fi-tgl-dsi/igt@i915_selftest@live@execlists.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803


Participating hosts (49 -> 41)
------------------------------

  Missing    (8): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-hsw-4770 fi-kbl-7560u fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8515 -> Patchwork_17740

  CI-20190529: 20190529
  CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17740: bc44bd9a82afa9176ff124f0b0772fb0e76f6851 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bc44bd9a82af drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
c2d80f1b6f74 drm/i915/dg1: Add initial DG1 workarounds
78c4ae0c9519 drm/i915/dg1: Load DMC
193af3a3fa98 drm/i915/dg1: enable PORT C/D aka D/E
f4fbfddf277b drm/i915/dg1: map/unmap pll clocks
4a55aec7a032 drm/i915/dg1: provide port/phy mapping for vbt
aa02226ddf5c drm/i915/dg1: Update voltage swing tables for DP
4b16f7612edc drm/i915/dg1: Update comp master/slave relationships for PHYs
abb9e6fb2b34 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
f09b2dfb4b4b drm/i915/dg1: Enable first 2 ports for DG1
1dade3145d62 drm/i915/dg1: Log counter on SLM ECC error
f97a2a7d014c drm/i915/dg1: Handle GRF/IC ECC error irq
cc507b9ee4a3 drm/i915/dg1: gmbus pin mapping
ec9aba37c1bc drm/i915/dg1: invert HPD pins
ee35c0b01372 drm/i915/dg1: add hpd interrupt handling
b71cffc572c1 drm/i915/dg1: Enable DPLL for DG1
a479afd96b2f drm/i915/dg1: Add and setup DPLLs for DG1
8ce1edf79a8b drm/i915/dg1: Add DPLL macros for DG1
1374e1028fdd drm/i915/dg1: Wait for pcode/uncore handshake at startup
ae8f9beefdc3 drm/i915/dg1: add support for the master unit interrupt
c3003b9fc682 drm/i915/dg1: Increase mmio size to 4MB
afeb7e41f94f drm/i915/dg1: Add DG1 power wells
56eeab2dc631 drm/i915/dg1: Define MOCS table for DG1
3dbe2b7cdf3b drm/i915/dg1: Initialize RAWCLK properly
cb1bcd5b7bed drm/i915/dg1: Add fake PCH
40ca1f1b6295 drm/i915/dg1: Add DG1 PCI IDs
5b325ece80ab drm/i915/dg1: add initial DG-1 definitions
24d7987fb08f drm/i915: add pcie snoop flag
4aa7cd7024ae drm/i915: Add has_master_unit_irq flag
84c20511222a drm/i915: make intel_{uncore, de}_rmw() more useful
7afbe335b525 drm/i915/rkl: Add initial workarounds
33974ed52c17 drm/i915/rkl: Handle comp master/slave relationships for PHYs
a33d8a84bd52 drm/i915/rkl: Handle HTI
03cb728ff5e5 drm/i915/rkl: provide port/phy mapping for vbt
470f943d8711 drm/i915/rkl: Setup ports/phys
8eb7430370e7 drm/i915/rkl: Add DDC pin mapping
eb8bcc051bcb drm/i915/rkl: Add DPLL4 support

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17740/index.html
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  parent reply	other threads:[~2020-05-21  1:26 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-21  0:37 [Intel-gfx] [PATCH 00/37] Introduce DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 01/37] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 02/37] drm/i915/rkl: Add DDC pin mapping Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 03/37] drm/i915/rkl: Setup ports/phys Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 04/37] drm/i915/rkl: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 05/37] drm/i915/rkl: Handle HTI Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 06/37] drm/i915/rkl: Handle comp master/slave relationships for PHYs Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 07/37] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 08/37] drm/i915: make intel_{uncore, de}_rmw() more useful Lucas De Marchi
2020-05-21 17:24   ` Souza, Jose
2020-05-21 17:30     ` Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 09/37] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-05-26 18:10   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 10/37] drm/i915: add pcie snoop flag Lucas De Marchi
2020-05-21  8:15   ` Chris Wilson
2020-05-21  0:37 ` [Intel-gfx] [PATCH 11/37] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-05-26 17:34   ` Souza, Jose
2020-05-26 17:51     ` Lucas De Marchi
2020-05-26 18:02       ` Souza, Jose
2020-05-26 17:51   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 12/37] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-05-26 17:35   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 13/37] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 14/37] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 15/37] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 16/37] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 17/37] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 18/37] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-05-26 18:02   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 19/37] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 20/37] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 21/37] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 22/37] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 23/37] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 24/37] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 25/37] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 26/37] drm/i915/dg1: Handle GRF/IC ECC error irq Lucas De Marchi
2020-05-21  8:19   ` Chris Wilson
2020-05-21  0:37 ` [Intel-gfx] [PATCH 27/37] drm/i915/dg1: Log counter on SLM ECC error Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 28/37] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 29/37] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 30/37] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 31/37] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 32/37] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 33/37] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 34/37] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 35/37] drm/i915/dg1: Load DMC Lucas De Marchi
2020-05-26 17:42   ` Souza, Jose
2020-05-26 17:49     ` Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 36/37] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 37/37] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-05-26 17:44   ` Souza, Jose
2020-05-21  1:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-05-21  1:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-05-21  1:26 ` Patchwork [this message]
2020-05-21 18:34 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] " Lucas De Marchi
2020-10-12 22:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork

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