From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: fernando.pacheco@intel.com, Matthew Auld <matthew.auld@intel.com>
Subject: [Intel-gfx] [PATCH 36/37] drm/i915/dg1: Add initial DG1 workarounds
Date: Wed, 20 May 2020 17:38:02 -0700 [thread overview]
Message-ID: <20200521003803.18936-37-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20200521003803.18936-1-lucas.demarchi@intel.com>
From: Stuart Summers <stuart.summers@intel.com>
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 5 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 17 +++-
5 files changed, 105 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 265183694c62..70e7bf57acda 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5455,8 +5455,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
const struct buddy_page_mask *table;
int i;
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
- /* Wa_1409767108: tgl */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ /* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 20eea81118da..1b7108b65d7d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0],rkl[all] */
- if (IS_ROCKETLAKE(dev_priv) ||
+ /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 31c5b85a5cf5..b19395f8a001 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -617,6 +617,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
FF_MODE2_TDS_TIMER_128, 0);
}
+static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
+ /* Wa_1409044764 */
+ WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
+
+ /* Wa_22010493298 */
+ WA_SET_BIT_MASKED(HIZ_CHICKEN,
+ DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -629,7 +643,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_ctx_workarounds_init(engine, wal);
+ else if (IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 12))
gen12_ctx_workarounds_init(engine, wal);
@@ -964,10 +980,30 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
}
+static void
+dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
+
+ /* Wa_1607087056:dg1 */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+ wa_write_or(wal,
+ SLICE_UNIT_LEVEL_CLKGATE,
+ L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+ /* Wa_1409420604:dg1 */
+ if (IS_DG1(i915))
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_gt_workarounds_init(i915, wal);
+ else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 12))
gen12_gt_workarounds_init(i915, wal);
@@ -1297,6 +1333,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
}
}
+static void dg1_whitelist_build(struct intel_engine_cs *engine)
+{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ tgl_whitelist_build(engine);
+
+ /* GEN:BUG:1409280441:dg1 */
+ if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+ (engine->class == RENDER_CLASS ||
+ engine->class == COPY_ENGINE_CLASS))
+ whitelist_reg_ext(w, RING_ID(engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1304,7 +1354,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_DG1(i915))
+ dg1_whitelist_build(engine);
+ else if (IS_GEN(i915, 12))
tgl_whitelist_build(engine);
else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
@@ -1356,15 +1408,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
- * Wa_1607138336:tgl
- * Wa_1607063988:tgl
+ * Wa_1607138336:tgl[a0],dg1[a0]
+ * Wa_1607063988:tgl[a0],dg1[a0]
*/
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+ }
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
@@ -1377,32 +1432,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_or(wal,
GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
+ }
- /* Wa_1408615072:tgl */
+ if (IS_DG1(i915) || IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ /* Wa_1408615072:tgl[a0],dg1 */
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl,rkl */
+ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl,dg1 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ }
- /* Wa_1409804808:tgl,rkl */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1409804808:tgl,rkl,dg1[a0] */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl,rkl
+ * Wa_14010229206:tgl,rkl,dg1[a0]
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
/*
* Wa_1607030317:tgl
* Wa_1607186500:tgl
- * Wa_1607297627:tgl,rkl there are multiple entries for this
- * WA in the BSpec; some indicate this is an A0-only WA,
- * others indicate it applies to all steppings.
+ * Wa_1607297627:tgl,rkl,dg1[a0]
+ *
+ * On TGL and RKL there are multiple entries for this WA in the
+ * BSpec; some indicate this is an A0-only WA, others indicate
+ * it applies to all steppings so we trust the "all steppings."
+ * For DG1 this only applies to A0.
*/
wa_masked_en(wal,
GEN6_RC_SLEEP_PSMI_CONTROL,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da8aebac3fac..068dfe6284cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2520,6 +2520,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define RING_ID(base) _MMIO((base) + 0x8c)
#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
#define RESET_CTL_CAT_ERROR REG_BIT(2)
@@ -4131,6 +4132,7 @@ enum {
#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
#define TGL_VRH_GATING_DIS REG_BIT(31)
+#define DPT_GATING_DIS REG_BIT(22)
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
@@ -7960,12 +7962,14 @@ enum hardware_error {
#define GEN8_L3CNTLREG _MMIO(0x7034)
#define GEN8_ERRDETBCTRL (1 << 9)
-#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
- #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
- #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+ #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
+ #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
+ #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
+# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE (1 << 14)
# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4d885ef0bac5..05e7d4461acb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7153,6 +7153,19 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
0, DFR_DISABLE);
}
+static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ /*
+ * As opposed to TGL, we should not touch the registers for media power
+ * gating
+ */
+
+ /* Wa_14010096844:dg1[a0] */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+ I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+ DPT_GATING_DIS);
+}
+
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (!HAS_PCH_CNP(dev_priv))
@@ -7670,7 +7683,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 12))
+ if (IS_DG1(dev_priv))
+ dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ else if (IS_GEN(dev_priv, 12))
dev_priv->display.init_clock_gating = tgl_init_clock_gating;
else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
--
2.26.2
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next prev parent reply other threads:[~2020-05-21 0:38 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 0:37 [Intel-gfx] [PATCH 00/37] Introduce DG1 Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 01/37] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 02/37] drm/i915/rkl: Add DDC pin mapping Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 03/37] drm/i915/rkl: Setup ports/phys Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 04/37] drm/i915/rkl: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 05/37] drm/i915/rkl: Handle HTI Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 06/37] drm/i915/rkl: Handle comp master/slave relationships for PHYs Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 07/37] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 08/37] drm/i915: make intel_{uncore, de}_rmw() more useful Lucas De Marchi
2020-05-21 17:24 ` Souza, Jose
2020-05-21 17:30 ` Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 09/37] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-05-26 18:10 ` Souza, Jose
2020-05-21 0:37 ` [Intel-gfx] [PATCH 10/37] drm/i915: add pcie snoop flag Lucas De Marchi
2020-05-21 8:15 ` Chris Wilson
2020-05-21 0:37 ` [Intel-gfx] [PATCH 11/37] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-05-26 17:34 ` Souza, Jose
2020-05-26 17:51 ` Lucas De Marchi
2020-05-26 18:02 ` Souza, Jose
2020-05-26 17:51 ` Souza, Jose
2020-05-21 0:37 ` [Intel-gfx] [PATCH 12/37] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-05-26 17:35 ` Souza, Jose
2020-05-21 0:37 ` [Intel-gfx] [PATCH 13/37] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 14/37] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 15/37] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 16/37] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 17/37] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 18/37] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-05-26 18:02 ` Souza, Jose
2020-05-21 0:37 ` [Intel-gfx] [PATCH 19/37] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 20/37] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 21/37] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 22/37] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 23/37] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 24/37] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 25/37] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 26/37] drm/i915/dg1: Handle GRF/IC ECC error irq Lucas De Marchi
2020-05-21 8:19 ` Chris Wilson
2020-05-21 0:37 ` [Intel-gfx] [PATCH 27/37] drm/i915/dg1: Log counter on SLM ECC error Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 28/37] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 29/37] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 30/37] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 31/37] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 32/37] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21 0:37 ` [Intel-gfx] [PATCH 33/37] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-05-21 0:38 ` [Intel-gfx] [PATCH 34/37] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-05-21 0:38 ` [Intel-gfx] [PATCH 35/37] drm/i915/dg1: Load DMC Lucas De Marchi
2020-05-26 17:42 ` Souza, Jose
2020-05-26 17:49 ` Lucas De Marchi
2020-05-21 0:38 ` Lucas De Marchi [this message]
2020-05-21 0:38 ` [Intel-gfx] [PATCH 37/37] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-05-26 17:44 ` Souza, Jose
2020-05-21 1:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-05-21 1:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-05-21 1:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-21 18:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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