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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI v5 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path
Date: Fri, 22 Jan 2021 15:26:41 -0800	[thread overview]
Message-ID: <20210122232647.22688-12-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20210122232647.22688-1-manasi.d.navare@intel.com>

This patch disables the VRR enable and VRR PUSH
bits in the HW during commit modeset disable sequence.

Thsi disable will happen when the port is disabled
or when the userspace sets VRR prop to false and
requests to disable VRR.

v2:
* Use intel_de_rmw (Jani N)

v3:
* Remove rmw (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  1 +
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d1cb0499a5c4..704856b445b1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4060,6 +4060,8 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 
 		intel_disable_pipe(old_crtc_state);
 
+		intel_vrr_disable(old_crtc_state);
+
 		intel_ddi_disable_transcoder_func(old_crtc_state);
 
 		intel_dsc_disable(old_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4596a18857fe..776b8c5f93a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -134,3 +134,16 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
 		       TRANS_PUSH_EN | TRANS_PUSH_SEND);
 }
+
+void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+
+	if (!old_crtc_state->vrr.enable)
+		return;
+
+	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
+	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 1b7c53b5604a..43379c2bd4d9 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -23,5 +23,6 @@ void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 void intel_vrr_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state);
 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
+void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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  parent reply	other threads:[~2021-01-22 23:22 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-22 23:26 [Intel-gfx] [CI v5 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-25 11:41   ` Ville Syrjälä
2021-01-22 23:26 ` [Intel-gfx] [CI v5 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-22 23:26 ` Manasi Navare [this message]
2021-01-22 23:26 ` [Intel-gfx] [CI v5 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-25 11:42   ` Ville Syrjälä
2021-01-22 23:26 ` [Intel-gfx] [CI v5 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-23  2:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v5,01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Patchwork
2021-01-23  2:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-23  3:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-23 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-25 20:08 ` [Intel-gfx] [CI v6] " Manasi Navare
2021-01-25 20:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v6] drm/i915/display/vrr: Create VRR file and add VRR capability check (rev2) Patchwork
2021-01-25 20:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-25 21:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-26  2:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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