From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI v5 14/18] drm/i915/display: Add HW state readout for VRR
Date: Fri, 22 Jan 2021 15:26:43 -0800 [thread overview]
Message-ID: <20210122232647.22688-14-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20210122232647.22688-1-manasi.d.navare@intel.com>
This functions gets the VRR config from the VRR registers
to match the crtc state variables for VRR.
v2:
* Rebase (Manasi)
* Use HAS_VRR (Jani N)
v3:
* Get pipeline_full, flipline (Ville)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/display/intel_vrr.c | 20 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7fc3ffdbc9b6..1372cb042317 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8978,6 +8978,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
intel_get_transcoder_timings(crtc, pipe_config);
}
+ if (HAS_VRR(dev_priv))
+ intel_vrr_get_config(crtc, pipe_config);
+
intel_get_pipe_src_size(crtc, pipe_config);
if (IS_HASWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 776b8c5f93a4..c71254563a10 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -147,3 +147,23 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
}
+
+void intel_vrr_get_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 trans_vrr_ctl;
+
+ trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
+ crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (!crtc_state->vrr.enable)
+ return;
+
+ if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
+ crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
+ if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
+ crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
+ crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
+ crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 43379c2bd4d9..7610051edad2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -15,6 +15,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_dp;
struct intel_encoder;
+struct intel_crtc;
bool intel_vrr_is_capable(struct drm_connector *connector);
void intel_vrr_check_modeset(struct intel_atomic_state *state);
@@ -24,5 +25,7 @@ void intel_vrr_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
+void intel_vrr_get_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VRR_H__ */
--
2.19.1
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next prev parent reply other threads:[~2021-01-22 23:22 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-22 23:26 [Intel-gfx] [CI v5 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-25 11:41 ` Ville Syrjälä
2021-01-22 23:26 ` [Intel-gfx] [CI v5 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-22 23:26 ` Manasi Navare [this message]
2021-01-22 23:26 ` [Intel-gfx] [CI v5 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-25 11:42 ` Ville Syrjälä
2021-01-22 23:26 ` [Intel-gfx] [CI v5 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-23 2:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v5,01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Patchwork
2021-01-23 2:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-23 3:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-23 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-25 20:08 ` [Intel-gfx] [CI v6] " Manasi Navare
2021-01-25 20:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v6] drm/i915/display/vrr: Create VRR file and add VRR capability check (rev2) Patchwork
2021-01-25 20:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-25 21:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-26 2:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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